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Redmine MicroTESK - Task #8481 (New): Need a way to specify the termination address for the test programhttps://forge.ispras.ru/issues/84812017-10-05T07:38:41ZAndrei Tatarnikovandrewt@ispras.ru
<p>When generation is finished MicroTESK checks whether the execution reaches the end of the program.<br />Currently, MicroTESK considers the end of the program to be the last instruction of the last sequence (e.g. the program's epilogue).<br />However, the end of epilogue might contain some supplementary code that does not necessarily executed last (handlers, termination for different PEs).<br />In such cases, MicroTESK mistakenly says that execution cannot reach the termination point. This causes generation to fail.</p>
<p>To avoid such situation, there must be a way to explicitly specify the termination point for each PE.<br />It can be a special pseudo instruction that marks the termination point or a way to specify the termination address for a PE.</p> MicroTESK - Task #7678 (New): Generation of LLVM configuration files from nML specificationshttps://forge.ispras.ru/issues/76782016-11-04T08:41:14ZAndrei Tatarnikovandrewt@ispras.ru
<p>Subject. To solve this task, you need implement an extension in Java that will traverse nML IR and generated the required files.</p>
<p>Such extensions implement the <code>TranslatorHandler</code> interface and are registered in the constuctor of the <code>NmlTranslator</code> class (see the code fragment below).</p>
<pre><code class="java syntaxhl" data-language="java"><span class="kd">public</span> <span class="kd">final</span> <span class="kd">class</span> <span class="nc">NmlTranslator</span> <span class="kd">extends</span> <span class="nc">Translator</span><span class="o"><</span><span class="nc">Ir</span><span class="o">></span> <span class="o">{</span>
<span class="kd">private</span> <span class="kd">static</span> <span class="kd">final</span> <span class="nc">Set</span><span class="o"><</span><span class="nc">String</span><span class="o">></span> <span class="no">FILTER</span> <span class="o">=</span> <span class="nc">Collections</span><span class="o">.</span><span class="na">singleton</span><span class="o">(</span><span class="s">".nml"</span><span class="o">);</span>
<span class="kd">public</span> <span class="nf">NmlTranslator</span><span class="o">()</span> <span class="o">{</span>
<span class="kd">super</span><span class="o">(</span><span class="no">FILTER</span><span class="o">);</span>
<span class="n">getSymbols</span><span class="o">().</span><span class="na">defineReserved</span><span class="o">(</span><span class="nc">NmlSymbolKind</span><span class="o">.</span><span class="na">KEYWORD</span><span class="o">,</span> <span class="nc">ReservedKeywords</span><span class="o">.</span><span class="na">JAVA</span><span class="o">);</span>
<span class="n">getSymbols</span><span class="o">().</span><span class="na">defineReserved</span><span class="o">(</span><span class="nc">NmlSymbolKind</span><span class="o">.</span><span class="na">KEYWORD</span><span class="o">,</span> <span class="nc">ReservedKeywords</span><span class="o">.</span><span class="na">RUBY</span><span class="o">);</span>
<span class="c1">// Detects parent-child connections between primitives</span>
<span class="n">addHandler</span><span class="o">(</span><span class="k">new</span> <span class="nc">ReferenceDetector</span><span class="o">());</span>
<span class="c1">// Adds the list of root operations to IR </span>
<span class="n">addHandler</span><span class="o">(</span><span class="k">new</span> <span class="nc">RootDetector</span><span class="o">());</span>
<span class="n">addHandler</span><span class="o">(</span><span class="k">new</span> <span class="nc">ArgumentModeDetector</span><span class="o">());</span>
<span class="n">addHandler</span><span class="o">(</span><span class="k">new</span> <span class="nc">BranchDetector</span><span class="o">());</span>
<span class="n">addHandler</span><span class="o">(</span><span class="k">new</span> <span class="nc">MemoryAccessDetector</span><span class="o">());</span>
<span class="n">addHandler</span><span class="o">(</span><span class="k">new</span> <span class="nc">Analyzer</span><span class="o">(</span><span class="k">this</span><span class="o">));</span>
<span class="n">addHandler</span><span class="o">(</span><span class="k">new</span> <span class="nc">PrimitiveSyntesizer</span><span class="o">(</span><span class="k">this</span><span class="o">));</span>
<span class="n">addHandler</span><span class="o">(</span><span class="k">new</span> <span class="nc">ExceptionDetector</span><span class="o">());</span>
<span class="c1">// Generate Java code of the ISA model</span>
<span class="n">addHandler</span><span class="o">(</span><span class="k">new</span> <span class="nc">MetaDataGenerator</span><span class="o">(</span><span class="k">this</span><span class="o">));</span>
<span class="n">addHandler</span><span class="o">(</span><span class="k">new</span> <span class="nc">Generator</span><span class="o">(</span><span class="k">this</span><span class="o">));</span>
<span class="o">}</span>
</code></pre>
<p>All these handlers are examples of how to implement logic traversing IR. Some of them perform analysis and some generate code. Code generation is done using the <a href="http://www.stringtemplate.org/" class="external">StringTemplate</a> library (STG files + java classes).</p>
<p>To traverse the IR, the following classes and interfaces can be used: <code>IrVisitor</code>, <code>IrVisitorDefault</code> and <code>IrWalker</code> (or its variations <code>IrWalkerFlow</code>, <code>IrWalkerShortcuts</code>) defined in the <code>ru.ispras.microtesk.translator.nml.ir</code> package. You need to implement <code>IrVisitor</code> (use <code>IrVisitorDefault</code> as default implementation with empty methods) and pass it to the most suitable walker. <em>NOTE: implementation of IR walker and visitor is raw and a subject to improvements. Any questions/feedback are appreciated.</em></p>
<p>Expressions require using a separate walker and visitor implemented in Fortress: <code>ExprTreeVisitor</code>, <code>ExprTreeVisitorDefault</code> and <code>ExprTreeWalker</code> (<code>ru.ispras.fortress.expression</code>). Examples of using them you can find both in MicroTESK and in Fortress.</p> MicroTESK - Task #7534 (Closed): Configuration option to manage reservation of explicitly specifi...https://forge.ispras.ru/issues/75342016-08-26T12:23:33ZAndrei Tatarnikovandrewt@ispras.ru
<p>It should be a possibility to inform the generator not to reserve registers specified explicitly. E.g.,</p>
<pre><code class="ruby syntaxhl" data-language="ruby"><span class="n">mov</span> <span class="n">reg</span><span class="p">(</span><span class="mi">0</span><span class="p">),</span> <span class="o">...</span> <span class="n">reg</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span> <span class="c1"># is not marked as busy</span>
<span class="n">mov</span> <span class="n">reg</span><span class="p">(</span><span class="n">_</span><span class="p">),</span> <span class="o">...</span> <span class="c1"># an allocated register is marked as busy</span>
</code></pre>
<p>Configuration option: <code>--reserve-explicit-registers</code>.</p> MicroTESK - Task #7300 (Closed): More timing metrics in generation statisticshttps://forge.ispras.ru/issues/73002016-06-17T12:03:13ZAndrei Tatarnikovandrewt@ispras.ru
<p>Additional timing metrics in generation statistics are needed. This is important to know on what tasks MicroTESK is spending its time. Such metrics include:</p>
<ol>
<li><strong>Template parsing time</strong></li>
<li>Sequence construction time</li>
<li>Data generation time</li>
<li><strong>Simulation time</strong></li>
<li>etc.</li>
</ol> MicroTESK - Task #7298 (Closed): Command-line option to disable simulation on the reference modelhttps://forge.ispras.ru/issues/72982016-06-17T11:43:44ZAndrei Tatarnikovandrewt@ispras.ru
<p>Subj. is needed.</p> MicroTESK - Task #7012 (Closed): Implement means of managing the use of registers in a test programhttps://forge.ispras.ru/issues/70122016-03-31T07:27:10ZAndrei Tatarnikovandrewt@ispras.ru
<p>Need facilities to choose registers that are not in use and to make them free.</p>
<p>"Task 4 – get_register/free_register that talks to the model. Used by the branch engine as well to get/free registers that it requires. Must support parameters such as exclusion, and cpuID (or a function to reset which registers are reserved)"</p> MicroTESK - Task #6973 (Closed): Support for atomic sequences that will never be interrupted/reor...https://forge.ispras.ru/issues/69732016-03-16T13:44:05ZAndrei Tatarnikovandrewt@ispras.ru
<p>See subject. Syntax is the following:</p>
<pre><code class="ruby syntaxhl" data-language="ruby"><span class="n">atomic</span> <span class="p">{</span>
<span class="o">...</span>
<span class="p">}</span>
</code></pre> Fortress - Task #5819 (Closed): Calculator for bit vectorshttps://forge.ispras.ru/issues/58192015-04-09T13:18:19ZAndrei Tatarnikovandrewt@ispras.ru
<p>Subj. must be implemented.</p> MicroTESK - Task #5716 (Closed): Implement the possibility to process template code multiple time...https://forge.ispras.ru/issues/57162015-03-17T13:26:50ZAndrei Tatarnikovandrewt@ispras.ru
<p>See my comments in Bug <a class="issue tracker-1 status-5 priority-6 priority-high2 closed" title="Bug: Error: Your application used more memory than the safety cap of 1024M. (Closed)" href="https://forge.ispras.ru/issues/5691">#5691</a>. Need a construct like this:</p>
<pre><code class="ruby syntaxhl" data-language="ruby"><span class="n">atomic</span> <span class="p">(</span><span class="ss">:repeat</span> <span class="o">=></span> <span class="mi">1000000</span><span class="p">)</span> <span class="p">{</span>
<span class="o">...</span>
<span class="p">}</span>
</code></pre>
<p>This is needed to repeat fragments of a test template and gives the following advantages over the "1000000.times { ... }" Ruby construct, which is now used:</p>
<ul>
<li>Only one copy which is processed N times (the iterator returns the same sequence N times).</li>
<li>No processor time is spent to create N identical objects (no time-consuming interactions between Ruby and Java).</li>
<li>No memory is wasted to store N identical objects.</li>
<li>This will work in any place in a test template (not only for top-level blocks)</li>
</ul> MicroTESK - Task #5678 (Closed): Support for named branches in ISA specificationshttps://forge.ispras.ru/issues/56782015-03-03T10:46:59ZAndrei Tatarnikovandrewt@ispras.ru
<p>Named branches in ISA specifications must be supported:</p>
<ol>
<li>Support the construct "<code>branch("BranchName");</code>" in the nML translator;</li>
<li>Support situations for named branches in the coverage extractor.</li>
</ol> MicroTESK - Task #5676 (Closed): [generator] Random generation - weighting / biasing distribution https://forge.ispras.ru/issues/56762015-03-03T09:20:51ZAndrei Tatarnikovandrewt@ispras.ru
<p>Subj. must be implemented.</p>
<p>Discussion about the randomisation/seeding/biasing/buckets point (Randomisation and seeding / Biasing – not just :min, :max , but buckets):</p>
<blockquote>
<p>we were thinking about something available in languages with support for constrained-random activity, like Specman 'e' and SystemVerilog.</p>
<p>For instance this is a SystemVerilog example taken from <a class="external" href="http://www.asic-world.com/systemverilog/random_constraint7.html">http://www.asic-world.com/systemverilog/random_constraint7.html</a> :<br /><pre>
constraint src {
src_port dist {
0 := 1,
1 := 1,
2 := 5,
4 := 1
};
}
constraint des {
des_port dist {
[0 : 5 ] :/ 5,
[6 : 100 ] := 1,
[101 : 200 ] := 1,
[201 : 255 ] := 1
};
}
</pre><br />Basically the "dist" construct allows a "distribution" of probability to be specified.</p>
<p>For instance the value of "src_port" can have values 0,1,2,4, where values 0,1,4 all have the same weight whereas value 2 has five times the weight of the others.</p>
<p>As the total sum of all the weights is 8, values 0,1,4 will be extracted 1/8 of the time each (i.e. 12.5%), whereas value 2 will have a probability of 5/8 (i.e. 62.5%).</p>
<p>The second example for "dst_port" is a bit more complex (you can find an explanation of the operators here: <a class="external" href="http://www.testbench.in/CR_15_CONSTRAINT_EXPRESSION.html">http://www.testbench.in/CR_15_CONSTRAINT_EXPRESSION.html</a> ).</p>
<p>Basically all the values comprised for instance in the second range [6:100] will all have a weight of 1 each; whereas those in the first range will share the same weight of 5 (so the six numbers will have a weight of 5/6 each).</p>
<p>Each of these ranges can be considered a "bucket" (but we usually refer to this as "distributions" at the time of generation and "bucketing" at the time of collecting coverage).</p>
<p>In addition of getting generating values match the desired distribution across multiple generated tests, it is desirable to be able to generate exactly the same test again if the generator is invoked with the same randomization seed (typically from the command line).</p>
<p>Please note that the probability distribution doesn't necessarily have to only work with numbers, for instance something like this could be envisaged for load instructions:<br /><pre>
constraint c_LD_instr {
LD_instr dist {
LDR := 1,
LDRB := 1,
LDRH := 5,
LDUR := 1
};
}
</pre></p>
</blockquote> MicroTESK - Task #5674 (Rejected): Description of test data generation mechanisms (test situation...https://forge.ispras.ru/issues/56742015-03-03T08:59:36ZAndrei Tatarnikovandrewt@ispras.ru
<p>Subj. Need public documentation on this.</p> MicroTESK - Task #5673 (Closed): Memory scalability for large memory ranges (address space for 48...https://forge.ispras.ru/issues/56732015-03-03T08:54:58ZAndrei Tatarnikovandrewt@ispras.ru
<p>Verify and review (if needed) the scalability of memory in the simulator for large memory ranges (address space for 48 and 64 bit addresses).</p>
<p>Question:</p>
<blockquote>
<p>o ISPRAS to review and confirm the sparseness of the implementation of memory<br />• Does memory use of generation scale with number of locations touched or the range of (min, max)</p>
</blockquote>
<p>Answer</p>
<blockquote>
<p>In the current implementation of the simulator, memory is divided into 4KB regions which are allocated only when touched (written to).</p>
</blockquote>
<p>Check whether the current way to avoid excessive memory consumption is sufficient. This includes more intensive testing. If not, the algorithm must be reviewed.</p>
<p>Basic ideas on sparse distributed memory:</p>
<p><a class="external" href="http://en.wikipedia.org/wiki/Sparse_distributed_memory">http://en.wikipedia.org/wiki/Sparse_distributed_memory</a></p> MicroTESK - Task #5672 (Closed): Support for UNPREDICTED and UNDEFINEDhttps://forge.ispras.ru/issues/56722015-03-03T08:35:05ZAndrei Tatarnikovandrewt@ispras.ru
<p>Support for handling branches of instruction logic marked as UNPREDICTED and UNDEFINED:</p>
<ol>
<li>In the nML translator (keywords UNPREDICTED or UNDEFINED);</li>
<li>In the coverage extractor (corresponding constraints)</li>
</ol> MicroTESK - Task #5670 (Closed): Examples of test templates using memory-related test situations ...https://forge.ispras.ru/issues/56702015-03-03T08:04:19ZAndrei Tatarnikovandrewt@ispras.ru
<p>Examples must be created an published.</p>