Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692020-06-18T06:07:31ZOpen-Source Projects
Redmine Verilog Translator - Bug #10382 (Closed): java.lang.IllegalArgumentException: expression=(BVREPEA...https://forge.ispras.ru/issues/103822020-06-18T06:07:31ZSergey Smolovsmolov@ispras.ru
<pre>
java.lang.IllegalArgumentException: expression=(BVREPEAT test.uut._saxi_maskwidth 1)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:109)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.defineParameter(VerilogElaborator.java:1074)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:526)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariablesAndBindings(VerilogElaborator.java:910)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariablesAndBindings(VerilogElaborator.java:883)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:330)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:231)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:212)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.sample.VerilogPrinterTestCase.runTest(VerilogPrinterTestCase.java:50)
</pre> Verilog Translator - Bug #10214 (Rejected): ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest...https://forge.ispras.ru/issues/102142020-04-06T08:16:08ZSergey Smolovsmolov@ispras.ru
<pre>
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\nut_000\nut_000_lut.v line 7:0 no viable alternative at input 'module'
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 30417:21 mismatched tree node: <unexpected: [@116916,240:245='module',<123>,7:0], resync=modulecarry_sum(sin,cin,sout,cout);inputsin;inputcin;outputsout;outputcout;> expecting AST_MODULE_ITEMS
ERROR: [Internal] null
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.verilog.parser.core.AbstractNode.add(AbstractNode.java:382)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:718)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:665)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:443)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:448)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:474)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:478)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:206)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogQuipTestSuite.runTest_nut_000(VerilogQuipTestSuite.java:302)
</pre> Verilog Translator - Bug #9848 (Closed): ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.r...https://forge.ispras.ru/issues/98482019-10-04T15:24:16ZSergey Smolovsmolov@ispras.ru
<pre>
ERROR: Function declaration '$ND' has not been found
ERROR: [Internal] null
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkFalse(InvariantChecks.java:68)
at ru.ispras.verilog.parser.VerilogTranslator.exit(VerilogTranslator.java:112)
at ru.ispras.verilog.parser.backends.syntax.checker.VerilogStaticChecker.checkFunctionCall(VerilogStaticChecker.java:651)
at ru.ispras.verilog.parser.backends.syntax.checker.VerilogStaticChecker.access$000(VerilogStaticChecker.java:72)
at ru.ispras.verilog.parser.backends.syntax.checker.VerilogStaticChecker$ExprTreeVisitor.onOperationBegin(VerilogStaticChecker.java:97)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:139)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.verilog.parser.backends.syntax.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:468)
at ru.ispras.verilog.parser.backends.syntax.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:480)
at ru.ispras.verilog.parser.backends.syntax.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:497)
at ru.ispras.verilog.parser.backends.syntax.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:527)
at ru.ispras.verilog.parser.backends.syntax.checker.VerilogStaticChecker.onAssignBegin(VerilogStaticChecker.java:129)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$2.onBegin(VerilogNodeVisitor.java:253)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:87)
at ru.ispras.verilog.parser.VerilogSyntaxBackend.start(VerilogSyntaxBackend.java:80)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:187)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:72)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:58)
at ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_Pci_Bus_Verilog_Mv_files_PciNorm(VerilogTexas97TestCase.java:514)
</pre> Verilog Translator - Bug #9822 (Closed): ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_...https://forge.ispras.ru/issues/98222019-09-16T13:19:45ZSergey Smolovsmolov@ispras.ru
<pre>
ERROR: Starting points limit has been exhausted: 513
ERROR: [Internal] null
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkFalse(InvariantChecks.java:68)
at ru.ispras.verilog.parser.VerilogTranslator.exit(VerilogTranslator.java:112)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:211)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:187)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:72)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:58)
at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1(VerilogIeeeTestCase.java:933)
</pre> Retrascope IDE - Bug #9816 (New): Retrascope IDE does not appear in "Installed Software" menuhttps://forge.ispras.ru/issues/98162019-09-09T09:08:34ZSergey Smolovsmolov@ispras.ru
<p>The plugin does not appear in Help->About Eclipse IDE->Installed Software menu</p> Verilog Translator - Bug #9784 (Closed): mul_fifo.v: wrong Fortress-based node representation of ...https://forge.ispras.ru/issues/97842019-08-01T15:18:29ZSergey Smolovsmolov@ispras.ru
<p>Representation that VeriTrans produces on <em>fifo0/mul_fifo.v</em> module contains errors in assignments - Fortress expressions of left-hand side targets are incorrect. For example, one may contain SELECT(x 0), where <em>x</em> is NOT array (map), in the node field of assignment's reference.</p>
<p>In the above Verilog example the situation arises via the following code's processing. The assignment from <em>myfifo.v</em> Verilog file has (SELECT one_fifo.DO_tmp 00000000000000000000000000000000)<br />Fortress expression in it's left hand side, where <em>one_fifo.DO_tmp</em> has (BIT_VECTOR 8) data type.<br /><pre>
mul_fifo.v:
module mul_fifo(
...
//------Parameters declaration:---------
parameter FCOUNT_SIZE = 2;
parameter DATA_SIZE = 8;
//--------------------------------------
wire [(DATA_SIZE-1):0] DO_tmp [((1 << FCOUNT_SIZE)-1):0];
...
generate
genvar i;
for (i=0; i!=(1 << FCOUNT_SIZE); i=i+1) begin
myfifo #(ADDR_SIZE,DATA_SIZE) one_fifo(
.DO(DO_tmp[i]),
...
end
endgenerate
endmodule
myfifo.v:
`ifndef _MY_FIFO_
`define _MY_FIFO_
`define NAME myfifo
...
module `NAME (
DO,
...);
//------Parameters declaration:---------
parameter ADDR_SIZE = 4;
parameter DATA_SIZE = 8;
//--------------------------------------
output [(DATA_SIZE-1):0] DO; // Data Output
...
wire [(DATA_SIZE-1):0] DO_tmp;
always @(posedge CLK) begin
...
DO <= DO_tmp;
...
end
...
endmodule
`endif
</pre></p> Retrascope RISC-V Benchmark - Bug #9478 (New): ERROR: retrascope-riscv\src\main\verilog\rocket-ch...https://forge.ispras.ru/issues/94782019-02-06T10:20:27ZSergey Smolovsmolov@ispras.ru
<p>The <strong>ru.ispras.verilog.parser.sample.RocketChipTestDriverVerilogPrinterTestCase</strong> test case falls with the following error:<br /><pre>
ERROR: L:\work\retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:6 mismatched input 'unsigned' expecting LPAREN
ERROR: L:\work\retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 31:4 missing KW_BEGIN at 'void'
ERROR: [Internal] null
</pre><br />The related Verilog code is as follows:<br /><pre><code class="text syntaxhl" data-language="text">int unsigned rand_value;
</code></pre></p> MicroTESK - Bug #9437 (Closed): ru.ispras.microtesk.model.minimips.BufferPreparatorTestCase: QEMU...https://forge.ispras.ru/issues/94372019-01-18T13:41:47ZSergey Smolovsmolov@ispras.ru
<p>When running the ru.ispras.microtesk.model.minimips.BufferPreparatorTestCase test case at Jenkins server, the following error takes place:<br /><pre>
java.lang.AssertionError: Process has returned '139': "/srv/jenkins/workspace/MicroTESK/build/tools/qemu/bin/qemu-system-mips -M mips -cpu mips32r6-generic -d unimp,nochain,in_asm -nographic -singlestep -D /srv/jenkins/workspace/MicroTESK/build/test/minimips/buffer_preparator/buffer_preparator_0000-qemu.log -bios /srv/jenkins/workspace/MicroTESK/build/test/minimips/buffer_preparator/buffer_preparator_0000.elf"
No error log is found, try to run command in terminal.
at org.junit.Assert.fail(Assert.java:88)
at ru.ispras.microtesk.model.minimips.MiniMipsTest.runCommand(MiniMipsTest.java:556)
at ru.ispras.microtesk.model.minimips.MiniMipsTest.runCommand(MiniMipsTest.java:477)
at ru.ispras.microtesk.model.minimips.MiniMipsTest.emulate(MiniMipsTest.java:311)
at ru.ispras.microtesk.model.minimips.MiniMipsTest.compileAndEmulate(MiniMipsTest.java:273)
</pre></p>
<p>At Jenkins this event causes the general protection error as it is described in /var/log/messages (/var/log/kern.log):<br /><pre>
kernel: [19535.492676] traps: qemu-system-mip[1930] general protection ip:56360bb9966c sp:7f50ad4776b8 error:0 in qemu-system-mips[56360b8eb000+8ff000]
</pre></p>
<p>To preproduce the error,uncomment ru.ispras.microtesk.model.minimips.BufferPreparatorTestCase class' code.</p> Verilog Translator - Bug #9231 (Closed): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_...https://forge.ispras.ru/issues/92312018-08-17T07:50:34ZSergey Smolovsmolov@ispras.ru
<p>The test case produces the following exception:<br /><pre>
java.lang.NullPointerException
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_binary_operation(VerilogTreeBuilder.java:6931)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_operation(VerilogTreeBuilder.java:6225)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_expression(VerilogTreeBuilder.java:6060)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_binary_operation(VerilogTreeBuilder.java:6923)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_operation(VerilogTreeBuilder.java:6225)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_expression(VerilogTreeBuilder.java:6060)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_if_statement(VerilogTreeBuilder.java:4671)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4087)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:5171)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4117)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_case_statement_item(VerilogTreeBuilder.java:5513)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_case_statement(VerilogTreeBuilder.java:4835)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4097)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:5171)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4117)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_delayed_statement(VerilogTreeBuilder.java:4620)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4077)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_process(VerilogTreeBuilder.java:3202)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_item(VerilogTreeBuilder.java:946)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_module(VerilogTreeBuilder.java:674)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:516)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:466)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:250)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:255)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:270)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:274)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:168)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:72)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:58)
at ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2(VerilogTexas97TestCase.java:515)
</pre></p>
<p>The tool error log is:<br /><pre><code class="text syntaxhl" data-language="text">ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 155:23 no viable alternative at input ')'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 165:27 no viable alternative at input ')'
DEBUG: Expanding macro '3'b101' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 167:27 no viable alternative at input ')'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 167:42 no viable alternative at input ')'
DEBUG: Expanding macro '3'b011' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 176:23 no viable alternative at input ')'
DEBUG: Expanding macro '3'b011' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b100' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b100' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 192:23 no viable alternative at input ')'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 202:27 no viable alternative at input ')'
DEBUG: Expanding macro '3'b101' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 204:25 no viable alternative at input ')'
DEBUG: Expanding macro '3'b100' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b001' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b101' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b010' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b001' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b00' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b00' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b01' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b01' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b10' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b10' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b00' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b01' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b10' ...
DEBUG: End of the token source 'null'
ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 155:12 no viable alternative at input ')'
</code></pre></p> Veritool - Bug #9184 (New): ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veri...https://forge.ispras.ru/issues/91842018-08-01T13:04:10ZSergey Smolovsmolov@ispras.ru
<p>Running the tool on the attached Verilog module with such parameters, as '--c --module=blocks --clk=clk --rst=rst --all blocks.v', causes the following error trace:<br /><pre>
ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veritool.conf
: error: target_design entry point is missing.
error: Code generator failure: -2
veritool failed
</pre></p> Retrascope Test Suite - Bug #9012 (Closed): VisBufferAllocVerilogPrinterTestCase: java.lang.Illeg...https://forge.ispras.ru/issues/90122018-06-27T09:16:02ZSergey Smolovsmolov@ispras.ru
<pre>
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:95)
at ru.ispras.verilog.parser.processor.VerilogExprTransformer$1.apply(VerilogExprTransformer.java:144)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:166)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:226)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
at ru.ispras.verilog.parser.processor.VerilogExprTransformer.transform(VerilogExprTransformer.java:62)
at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:159)
at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:170)
at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:189)
at ru.ispras.verilog.parser.elaborator.VerilogTransformer.onAssignStatementBegin(VerilogTransformer.java:78)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(VerilogNodeVisitor.java:265)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:100)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:79)
at ru.ispras.verilog.parser.elaborator.VerilogTransformer.run(VerilogTransformer.java:53)
at ru.ispras.verilog.parser.elaborator.VerilogVariableSubstitutor.transform(VerilogVariableSubstitutor.java:44)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateProcess(VerilogInstantiator.java:88)
at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:185)
at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:173)
at ru.ispras.verilog.parser.sample.VerilogDesignPrinter.start(VerilogDesignPrinter.java:36)
at ru.ispras.verilog.parser.VerilogDesignBackends.start(VerilogDesignBackends.java:56)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:169)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.sample.VerilogPrinterTest.runTest(VerilogPrinterTest.java:49)
</pre> MicroTESK - Bug #5966 (Closed): mark shell scripts as executable in the distribution tar.gz archivehttps://forge.ispras.ru/issues/59662015-05-20T13:57:22ZSergey Smolovsmolov@ispras.ru
<p>When unpacked the <code>tar.gz</code> tool distribution contains shell scripts like <code>compile.sh</code> and <code>generate.sh</code> that are not marked as executable.</p> Retrascope IDE - Bug #5547 (New): save Retrascope result not to ECLIPSE_HOME folderhttps://forge.ispras.ru/issues/55472015-01-05T19:24:18ZSergey Smolovsmolov@ispras.ru
<p>While using Retrascope IDE Configurator menu, engines that generate output file can be selected (like test-xml-printer, which generates test.xml file by default).<br />But if the full path to the output file is not specified, the Retrascope IDE saves output file to the ECLIPSE_HOME folder. Which causes an error, for example, in Windows 7 OS, where Eclipse IDE can be installed to the protected-for-writing folder like C:\Program Files.</p> C++TESK Testing ToolKit - Bug #4004 (Closed): Из build'а пропал скрипт install-eclipse-plugin.shhttps://forge.ispras.ru/issues/40042013-03-14T17:36:57ZSergey Smolovsmolov@ispras.ru
<p>Т.е. в trunk проекта он есть, а в сборке не присутствует. <br />Без данного скрипта пропадает возможность установить C++TesK Eclipse plug-in из командной строки.</p>
<p>Просьба починить.</p> C++TESK Testing ToolKit - Bug #3590 (Closed): C++TesK installation fails on OpenSUSE 12.2 x64https://forge.ispras.ru/issues/35902012-10-15T11:18:40ZSergey Smolovsmolov@ispras.ru
<p>Попробовал установить subj на OpenSUSE 12.2 x64. Системные требования были удовлетворены (в соответствии с C++TESK.InstallationGuide.ru.pdf), скрипт установки запускался с опцией --force-install-veritool (Veritool и Icarus Verilog предварительно установлены не были, подключение к сети, естественно, есть).</p>
<p>По-видимому, Icarus Verilog установился корректно, а Veritool - нет.</p>
<p>Лог установочного скрипта в аттаче.</p>