Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692020-04-09T13:28:43ZOpen-Source Projects
Redmine Verilog Translator - Bug #10246 (Rejected): ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest...https://forge.ispras.ru/issues/102462020-04-09T13:28:43ZSergey Smolovsmolov@ispras.ru
<p>The tool takes 'lut_output.v' Verilog files as input, but reports it's absence.<br /><pre>
ERROR: Module 'lut_output' has not been found
ERROR: [Internal] null
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkFalse(InvariantChecks.java:68)
at ru.ispras.verilog.parser.VerilogTranslator.exit(VerilogTranslator.java:126)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:397)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:231)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:212)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogQuipTestSuite.runTest_nut_001(VerilogQuipTestSuite.java:355)
</pre></p> Retrascope - Bug #10236 (Rejected): efsm-test-generator hangs at opencores/mips16/data_mem.vhttps://forge.ispras.ru/issues/102362020-04-08T06:37:12ZSergey Smolovsmolov@ispras.ru
<pre>
2020.04.04 13:47:13.604. INFO: Retrascope is starting
2020.04.04 13:47:13.604. INFO: Running: verilog-parser
2020.04.04 13:47:13.604. INFO: Options: {args=/srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16/data_mem.v --target verilog-testbench --include-path /srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16 --module-name data_mem --engine efsm-test-generator:test-verilog-testbench-printer --overwrite --loop-limit 5, v=[/srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16/data_mem.v]}
2020.04.04 13:47:13.648. INFO: Storing: cfg
2020.04.04 13:47:13.648. INFO: Running: cfg-gadd-transformer
2020.04.04 13:47:13.648. INFO: Options: {args=/srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16/data_mem.v --target verilog-testbench --include-path /srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16 --module-name data_mem --engine efsm-test-generator:test-verilog-testbench-printer --overwrite --loop-limit 5, cfg=<cfg>}
2020.04.04 13:47:13.773. INFO: Clock-like variables (CLV): data_mem.clk.
2020.04.04 13:47:13.774. INFO: Storing: gadd
2020.04.04 13:47:13.774. INFO: Running: gadd-efsm-transformer
2020.04.04 13:47:13.774. INFO: Options: {args=/srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16/data_mem.v --target verilog-testbench --include-path /srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16 --module-name data_mem --engine efsm-test-generator:test-verilog-testbench-printer --overwrite --loop-limit 5, gadd=<gadd>}
2020.04.04 13:47:13.802. INFO: Execution path number: 264
2020.04.04 13:47:13.802. INFO: ======================================
2020.04.04 13:47:13.802. INFO: Transforming the process 'data_mem process'.
2020.04.04 13:47:13.802. INFO: State-like variables: <none>.
2020.04.04 13:47:13.802. INFO: Model states number: 1.
2020.04.04 13:47:13.802. INFO: Model transitions number: 1.
2020.04.04 13:47:13.802. INFO: ======================================
2020.04.04 13:47:13.802. INFO: Transforming the process 'data_mem process (posedge of data_mem.clk)'.
2020.04.04 13:47:13.802. INFO: State-like variables: <none>.
2020.04.04 13:47:19.833. INFO: Model states number: 262.
2020.04.04 13:47:19.833. INFO: Model transitions number: 519.
2020.04.04 13:47:19.833. INFO: ======================================
2020.04.04 13:47:19.833. INFO: Transforming the process 'data_mem process'.
2020.04.04 13:47:19.833. INFO: State-like variables: <none>.
2020.04.04 13:47:19.833. INFO: Model states number: 1.
2020.04.04 13:47:19.833. INFO: Model transitions number: 1.
2020.04.04 13:47:19.833. INFO: ======================================
2020.04.04 13:47:19.833. INFO: The number of extracted models: 3.
2020.04.04 13:47:19.833. INFO: The total number of states: 264.
2020.04.04 13:47:19.834. INFO: The total number of transitions: 521.
2020.04.04 13:47:19.834. INFO: ======================================
2020.04.04 13:47:19.834. INFO: The initial state for data_mem process (40bc96d3): node=true phase=0
2020.04.04 13:47:19.834. INFO: ======================================
2020.04.04 13:47:19.834. INFO: The initial state for data_mem process (posedge of data_mem.clk) (6b3c814f): node=true phase=0
2020.04.04 13:47:20.002. WARNING: Can't find resetting transition for data_mem process (posedge of data_mem.clk) (6b3c814f)
2020.04.04 13:47:20.002. WARNING: The extracted EFSM is not single testable: data_mem process (posedge of data_mem.clk) (6b3c814f)
2020.04.04 13:47:20.002. WARNING: The initial state is selected arbitrarily: node=true phase=0
2020.04.04 13:47:20.002. INFO: ======================================
2020.04.04 13:47:20.019. INFO: The initial state for data_mem process (1ef0e6ca): node=true phase=0
2020.04.04 13:47:20.020. WARNING: Can't find resetting transition for data_mem process (1ef0e6ca)
2020.04.04 13:47:20.020. WARNING: The extracted EFSM is not single testable: data_mem process (1ef0e6ca)
2020.04.04 13:47:20.020. WARNING: The initial state is selected arbitrarily: node=true phase=0
2020.04.04 13:47:20.020. INFO: ======================================
2020.04.04 13:47:20.020. INFO: Storing: efsm
2020.04.04 13:47:20.020. INFO: Running: cfg-cfginterface-extractor
2020.04.04 13:47:20.020. INFO: Options: {args=/srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16/data_mem.v --target verilog-testbench --include-path /srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16 --module-name data_mem --engine efsm-test-generator:test-verilog-testbench-printer --overwrite --loop-limit 5, cfg=<cfg>}
2020.04.04 13:47:20.020. INFO: Storing: cfg-iface
2020.04.04 13:47:20.020. INFO: Running: efsm-test-generator
2020.04.04 13:47:20.020. INFO: Options: {args=/srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16/data_mem.v --target verilog-testbench --include-path /srv/****/workspace/Retrascope_Weekly_Build/build/resources/test/opencores/mips16 --module-name data_mem --engine efsm-test-generator:test-verilog-testbench-printer --overwrite --loop-limit 5, efsm=<efsm>}
2020.04.04 13:47:20.020. INFO: EFSM.TestGenerator: module data_mem: starting test generation
2020.04.04 13:47:20.024. WARNING: The efsm can't be tested as a single one: data_mem process (posedge of data_mem.clk) (6b3c814f)
2020.04.04 13:47:20.024. WARNING: The efsm can't be tested as a single one: data_mem process (1ef0e6ca)
2020.04.04 13:47:20.024. WARNING: Wrong init value for 'data_mem.ram_addr': (BVEXTRACT 7 0 data_mem.mem_access_addr)
2020.04.04 13:47:20.024. WARNING: The efsm can't be tested as a single one: data_mem process (posedge of data_mem.clk) (6b3c814f)
2020.04.04 13:47:20.024. WARNING: The efsm can't be tested as a single one: data_mem process (1ef0e6ca)
2020.04.04 13:47:20.027. WARNING: Wrong init value for 'data_mem.ram_addr': (BVEXTRACT 7 0 data_mem.mem_access_addr)
</pre> Verilog Translator - Bug #10214 (Rejected): ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest...https://forge.ispras.ru/issues/102142020-04-06T08:16:08ZSergey Smolovsmolov@ispras.ru
<pre>
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\nut_000\nut_000_lut.v line 7:0 no viable alternative at input 'module'
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 30417:21 mismatched tree node: <unexpected: [@116916,240:245='module',<123>,7:0], resync=modulecarry_sum(sin,cin,sout,cout);inputsin;inputcin;outputsout;outputcout;> expecting AST_MODULE_ITEMS
ERROR: [Internal] null
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.verilog.parser.core.AbstractNode.add(AbstractNode.java:382)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:718)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:665)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:443)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:448)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:474)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:478)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:206)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogQuipTestSuite.runTest_nut_000(VerilogQuipTestSuite.java:302)
</pre> Retrascope Test Suite - Bug #9844 (Rejected): Bash scripts that run side tools (EBMC, SymbiYosys,...https://forge.ispras.ru/issues/98442019-10-02T12:52:00ZSergey Smolovsmolov@ispras.ru
<p>Bash scripts for side tools (EBMC, SymbiYosys, Verilog2SMV) running unable to extract names of several Verilog modules:</p>
<pre>
/home/ssedai/projects/retrascope-mc-benchmark/src/main/bash/../benchmarks/texas97/PI_BUS/single_master/master2.v
/home/ssedai/projects/retrascope-mc-benchmark/src/main/bash/../benchmarks/texas97/PI_BUS/single_master/bus.v
/home/ssedai/projects/retrascope-mc-benchmark/src/main/bash/../benchmarks/texas97/PI_BUS/multi_master/master2.v
/home/ssedai/projects/retrascope-mc-benchmark/src/main/bash/../benchmarks/texas97/PI_BUS/multi_master/bus.v
/home/ssedai/projects/retrascope-mc-benchmark/src/main/bash/../benchmarks/texas97/PPC60X_bus/src/cpu.v
/home/ssedai/projects/retrascope-mc-benchmark/src/main/bash/../benchmarks/texas97/PPC60X_bus/src/arbiter.v
/home/ssedai/projects/retrascope-mc-benchmark/src/main/bash/../benchmarks/texas97/PPC60X_bus/src/mem.v
/home/ssedai/projects/retrascope-mc-benchmark/src/main/bash/../benchmarks/verilog2smv/VCEGAR/pi_bus/pi_bus.v
/home/ssedai/projects/retrascope-mc-benchmark/src/main/bash/../benchmarks/verilog2smv/VCEGAR/zaher/zdlx_impl.v_for_pred.v
/home/ssedai/projects/retrascope-mc-benchmark/src/main/bash/../benchmarks/verilog2smv/VIS/Miim/vMiim_p2.v
/home/ssedai/projects/retrascope-mc-benchmark/src/main/bash/../benchmarks/verilog2smv/VIS/Miim/vMiim_p1.v
/home/ssedai/projects/retrascope-mc-benchmark/src/main/bash/../benchmarks/vcegar/miim/vMiim.v
/home/ssedai/projects/retrascope-mc-benchmark/src/main/bash/../benchmarks/vcegar/pi_bus/main_1.v
</pre>
<p>For these modules their top level names are empty. Note, that all the scripts have a precondition: top level name is it's first declared module name.</p>
<p>The problem is in the following code:<br /><pre><code class="shell syntaxhl" data-language="shell"><span class="nv">top_name</span><span class="o">=</span><span class="si">$(</span><span class="nb">echo</span> <span class="s2">"</span><span class="k">${</span><span class="nv">line</span><span class="k">}</span><span class="s2">"</span> | <span class="nb">sed</span> <span class="nt">-n</span> <span class="s1">'s/^module \([a-zA-Z0-9_]*\)[ |(||;].*$/\1/p'</span><span class="si">)</span>
</code></pre></p> Verilog Translator - Bug #9773 (Rejected): ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_1...https://forge.ispras.ru/issues/97732019-07-26T08:36:42ZSergey Smolovsmolov@ispras.ru
<pre>
java.lang.ClassCastException: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.checkFunctionCall(VerilogStaticChecker.java:642)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.access$000(VerilogStaticChecker.java:71)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker$ExprTreeVisitor.onOperationBegin(VerilogStaticChecker.java:96)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:139)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:464)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:476)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:493)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:523)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:536)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.onAssignStatementBegin(VerilogStaticChecker.java:134)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(VerilogNodeVisitor.java:265)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:87)
at ru.ispras.verilog.parser.VerilogSyntaxBackend.start(VerilogSyntaxBackend.java:80)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:181)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:72)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:58)
at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1(VerilogIeeeTestCase.java:928)
</pre> Verilog Translator - Bug #9276 (Rejected): no errors returned for bug-with-macro-containing modulehttps://forge.ispras.ru/issues/92762018-09-12T08:34:43ZSergey Smolovsmolov@ispras.ru
<p>The Texas'97 'three_processor.v' module has bugs with macro usages (sometimes "MACRO_NAME" is used, not "`MACRO_NAME"), but the Verilog Translator does not return any error.</p>
<p>Run ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_cache_coherence_three_processor test method.</p> Verilog Translator - Bug #9215 (Rejected): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTes...https://forge.ispras.ru/issues/92152018-08-11T15:24:15ZSergey Smolovsmolov@ispras.ru
<pre>
Module name: mem
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 47:19 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 50:19 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 147:5 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 148:12 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 171:5 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 179:5 mismatched input 'reg' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 47:8 required (...)+ loop did not match anything at input 'wire'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 47:8 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Starting the backend 'printer'...
module mem(.clkclk /* DECL: clk */, .TS_TS_ /* DECL: TS_ */, .TTTT /* DECL: TT */, .GBL_GBL_ /* DECL: GBL_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .DBB_DBB_ /* DECL: DBB_ */, .TA_TA_ /* DECL: TA_ */, .DRTRY_DRTRY_ /* DECL: DRTRY_ */, .BG1_BG1_ /* DECL: BG1_ */, .BG2_BG2_ /* DECL: BG2_ */, .DBG1_DBG1_ /* DECL: DBG1_ */, clk /* DECL: clk */, TS_ /* DECL: TS_ */, TT /* DECL: TT */, GBL_ /* DECL: GBL_ */, AACK_ /* DECL: AACK_ */, ARTRY_ /* DECL: ARTRY_ */, DBB_ /* DECL: DBB_ */, TA_ /* DECL: TA_ */, DRTRY_ /* DECL: DRTRY_ */, BG1_ /* DECL: BG1_ */, BG2_ /* DECL: BG2_ */, DBG1_ /* DECL: DBG1_ */);
input clk;
input TS_;
input [00000000000000000000000000000000:00000000000000000000000000000100] TT;
input GBL_;
output AACK_;
input ARTRY_;
input DBB_;
output TA_;
output DRTRY_;
input BG1_;
input BG2_;
input DBG1_;
/* DECL: null */
AddrStatus null
(
);
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(mem)'...
Bindings: {clk=clk, TS_=TS_, TT=TT, GBL_=GBL_, AACK_=AACK_, ARTRY_=ARTRY_, DBB_=DBB_, TA_=TA_, DRTRY_=DRTRY_, BG1_=BG1_, BG2_=BG2_, DBG1_=DBG1_}
Variables: {clk=DECLARATION(clk), TS_=DECLARATION(TS_), TT=DECLARATION(TT), GBL_=DECLARATION(GBL_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), DBB_=DECLARATION(DBB_), TA_=DECLARATION(TA_), DRTRY_=DECLARATION(DRTRY_), BG1_=DECLARATION(BG1_), BG2_=DECLARATION(BG2_), DBG1_=DECLARATION(DBG1_)}
Module 'AddrStatus' cannot be found
</pre>
<p>To reproduce the bug, uncomment the <strong>runTest_PPC60X_bus_src_mem</strong> method in <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase</strong> and run it.</p> Verilog Translator - Bug #9214 (Rejected): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTes...https://forge.ispras.ru/issues/92142018-08-11T15:16:52ZSergey Smolovsmolov@ispras.ru
<pre>
Module name: cpu
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 155:17 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 157:14 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 159:16 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 161:14 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 228:37 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 229:44 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 230:36 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 233:26 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 234:33 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 235:27 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 236:34 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 321:33 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 322:33 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 323:32 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 324:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 325:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 326:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 327:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 328:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 329:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 330:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 331:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 332:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 333:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 334:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 338:39 extraneous input '&&' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 339:28 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 341:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 342:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 346:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 347:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 348:36 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 349:43 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 350:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 351:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 352:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 353:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 354:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 356:40 mismatched input '&&' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 356:46 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 359:36 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 360:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 361:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 362:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 363:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 364:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 365:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 387:47 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 388:43 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 389:46 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 390:19 extraneous input ')' expecting SEMI
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 403:51 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 404:58 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 407:44 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 408:51 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 409:45 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 410:52 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 436:14 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 643:74 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 644:46 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 645:39 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 646:45 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 647:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 648:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 649:44 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 650:42 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 651:39 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 652:48 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 653:56 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 654:41 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 655:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 656:47 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 885:6 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 906:29 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 907:32 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 908:29 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 909:29 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 909:57 mismatched input ')' expecting COLON
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 939:16 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 941:16 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 943:16 mismatched input 'wire' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 155:3 required (...)+ loop did not match anything at input 'reg'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 155:3 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR_[]' has been found: DECLARATION(BR_)
Declaration of 'BG_[]' has been found: DECLARATION(BG_)
Declaration of 'ABB_[]' has been found: DECLARATION(ABB_)
Declaration of 'ABB1_[]' has been found: DECLARATION(ABB1_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TS1_[]' has been found: DECLARATION(TS1_)
Declaration of 'AP[]' has been found: DECLARATION(AP)
Declaration of 'APE_[]' has been found: DECLARATION(APE_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'TT1[]' has been found: DECLARATION(TT1)
Declaration of 'TSIZ[]' has been found: DECLARATION(TSIZ)
Declaration of 'TBST_[]' has been found: DECLARATION(TBST_)
Declaration of 'TBST1_[]' has been found: DECLARATION(TBST1_)
Declaration of 'TC[]' has been found: DECLARATION(TC)
Declaration of 'CI_[]' has been found: DECLARATION(CI_)
Declaration of 'WT_[]' has been found: DECLARATION(WT_)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'GBL1_[]' has been found: DECLARATION(GBL1_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'ARTRY1_[]' has been found: DECLARATION(ARTRY1_)
Declaration of 'SHD_[]' has been found: DECLARATION(SHD_)
Declaration of 'DBG_[]' has been found: DECLARATION(DBG_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'DBB1_[]' has been found: DECLARATION(DBB1_)
Declaration of 'DP[]' has been found: DECLARATION(DP)
Declaration of 'DPE_[]' has been found: DECLARATION(DPE_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR_[]' has been found: DECLARATION(BR_)
Declaration of 'BG_[]' has been found: DECLARATION(BG_)
Declaration of 'ABB_[]' has been found: DECLARATION(ABB_)
Declaration of 'ABB1_[]' has been found: DECLARATION(ABB1_)
Declaration of 'TS1_[]' has been found: DECLARATION(TS1_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'AP[]' has been found: DECLARATION(AP)
Declaration of 'APE_[]' has been found: DECLARATION(APE_)
Declaration of 'TT1[]' has been found: DECLARATION(TT1)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'TSIZ[]' has been found: DECLARATION(TSIZ)
Declaration of 'TBST1_[]' has been found: DECLARATION(TBST1_)
Declaration of 'TBST_[]' has been found: DECLARATION(TBST_)
Declaration of 'TC[]' has been found: DECLARATION(TC)
Declaration of 'CI_[]' has been found: DECLARATION(CI_)
Declaration of 'WT_[]' has been found: DECLARATION(WT_)
Declaration of 'GBL1_[]' has been found: DECLARATION(GBL1_)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY1_[]' has been found: DECLARATION(ARTRY1_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'SHD_[]' has been found: DECLARATION(SHD_)
Declaration of 'DBG_[]' has been found: DECLARATION(DBG_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'DBB1_[]' has been found: DECLARATION(DBB1_)
Declaration of 'DP[]' has been found: DECLARATION(DP)
Declaration of 'DPE_[]' has been found: DECLARATION(DPE_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Starting the backend 'printer'...
module cpu(.clkclk /* DECL: clk */, .BR_BR_ /* DECL: BR_ */, .BG_BG_ /* DECL: BG_ */, .ABB_ABB_ /* DECL: ABB_ */, .ABB1_ABB1_ /* DECL: ABB1_ */, .TS_TS_ /* DECL: TS_ */, .TS1_TS1_ /* DECL: TS1_ */, .APAP /* DECL: AP */, .APE_APE_ /* DECL: APE_ */, .TTTT /* DECL: TT */, .TT1TT1 /* DECL: TT1 */, .TSIZTSIZ /* DECL: TSIZ */, .TBST_TBST_ /* DECL: TBST_ */, .TBST1_TBST1_ /* DECL: TBST1_ */, .TCTC /* DECL: TC */, .CI_CI_ /* DECL: CI_ */, .WT_WT_ /* DECL: WT_ */, .GBL_GBL_ /* DECL: GBL_ */, .GBL1_GBL1_ /* DECL: GBL1_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .ARTRY1_ARTRY1_ /* DECL: ARTRY1_ */, .SHD_SHD_ /* DECL: SHD_ */, .DBG_DBG_ /* DECL: DBG_ */, .DBB_DBB_ /* DECL: DBB_ */, .DBB1_DBB1_ /* DECL: DBB1_ */, .DPDP /* DECL: DP */, .DPE_DPE_ /* DECL: DPE_ */, .TA_TA_ /* DECL: TA_ */, .DRTRY_DRTRY_ /* DECL: DRTRY_ */, clk /* DECL: clk */, BR_ /* DECL: BR_ */, BG_ /* DECL: BG_ */, ABB_ /* DECL: ABB_ */, ABB1_ /* DECL: ABB1_ */, TS1_ /* DECL: TS1_ */, TS_ /* DECL: TS_ */, AP /* DECL: AP */, APE_ /* DECL: APE_ */, TT1 /* DECL: TT1 */, TT /* DECL: TT */, TSIZ /* DECL: TSIZ */, TBST1_ /* DECL: TBST1_ */, TBST_ /* DECL: TBST_ */, TC /* DECL: TC */, CI_ /* DECL: CI_ */, WT_ /* DECL: WT_ */, GBL1_ /* DECL: GBL1_ */, GBL_ /* DECL: GBL_ */, AACK_ /* DECL: AACK_ */, ARTRY1_ /* DECL: ARTRY1_ */, ARTRY_ /* DECL: ARTRY_ */, SHD_ /* DECL: SHD_ */, DBG_ /* DECL: DBG_ */, DBB_ /* DECL: DBB_ */, DBB1_ /* DECL: DBB1_ */, DP /* DECL: DP */, DPE_ /* DECL: DPE_ */, TA_ /* DECL: TA_ */, DRTRY_ /* DECL: DRTRY_ */);
input clk;
output BR_;
input BG_;
input ABB_;
output ABB1_;
output TS1_;
input TS_;
output [00000000000000000000000000000000:00000000000000000000000000000011] AP;
output APE_;
output [00000000000000000000000000000100:00000000000000000000000000000000] TT1;
input [00000000000000000000000000000100:00000000000000000000000000000000] TT;
output [00000000000000000000000000000010:00000000000000000000000000000000] TSIZ;
output TBST1_;
input TBST_;
output [00000000000000000000000000000000:00000000000000000000000000000010] TC;
output CI_;
output WT_;
output GBL1_;
input GBL_;
input AACK_;
output ARTRY1_;
input ARTRY_;
output SHD_;
input DBG_;
input DBB_;
output DBB1_;
output [00000000000000000000000000000000:00000000000000000000000000000111] DP;
output DPE_;
input TA_;
input DRTRY_;
/* DECL: null */
AddressTenure null
(
);
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(cpu)'...
Bindings: {clk=clk, BR_=BR_, BG_=BG_, ABB_=ABB_, ABB1_=ABB1_, TS_=TS_, TS1_=TS1_, AP=AP, APE_=APE_, TT=TT, TT1=TT1, TSIZ=TSIZ, TBST_=TBST_, TBST1_=TBST1_, TC=TC, CI_=CI_, WT_=WT_, GBL_=GBL_, GBL1_=GBL1_, AACK_=AACK_, ARTRY_=ARTRY_, ARTRY1_=ARTRY1_, SHD_=SHD_, DBG_=DBG_, DBB_=DBB_, DBB1_=DBB1_, DP=DP, DPE_=DPE_, TA_=TA_, DRTRY_=DRTRY_}
Variables: {clk=DECLARATION(clk), BR_=DECLARATION(BR_), BG_=DECLARATION(BG_), ABB_=DECLARATION(ABB_), ABB1_=DECLARATION(ABB1_), TS_=DECLARATION(TS_), TS1_=DECLARATION(TS1_), AP=DECLARATION(AP), APE_=DECLARATION(APE_), TT=DECLARATION(TT), TT1=DECLARATION(TT1), TSIZ=DECLARATION(TSIZ), TBST_=DECLARATION(TBST_), TBST1_=DECLARATION(TBST1_), TC=DECLARATION(TC), CI_=DECLARATION(CI_), WT_=DECLARATION(WT_), GBL_=DECLARATION(GBL_), GBL1_=DECLARATION(GBL1_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), ARTRY1_=DECLARATION(ARTRY1_), SHD_=DECLARATION(SHD_), DBG_=DECLARATION(DBG_), DBB_=DECLARATION(DBB_), DBB1_=DECLARATION(DBB1_), DP=DECLARATION(DP), DPE_=DECLARATION(DPE_), TA_=DECLARATION(TA_), DRTRY_=DECLARATION(DRTRY_)}
Module 'AddressTenure' cannot be found
</pre>
<p>To reproduce the bug, uncomment the <strong>runTest_PPC60X_bus_src_cpu</strong> method in <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase</strong> and run it.</p> Verilog Translator - Bug #9213 (Rejected): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTes...https://forge.ispras.ru/issues/92132018-08-11T15:14:35ZSergey Smolovsmolov@ispras.ru
<pre>
Module name: arb2
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/arbiter.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/arbiter.v line 60:15 mismatched input 'reg' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 60:1 required (...)+ loop did not match anything at input 'reg'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 60:1 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR1_[]' has been found: DECLARATION(BR1_)
Declaration of 'BR2_[]' has been found: DECLARATION(BR2_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Declaration of 'DBG2_[]' has been found: DECLARATION(DBG2_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR1_[]' has been found: DECLARATION(BR1_)
Declaration of 'BR2_[]' has been found: DECLARATION(BR2_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Declaration of 'DBG2_[]' has been found: DECLARATION(DBG2_)
Starting the backend 'printer'...
module arb2(.clkclk /* DECL: clk */, .BR1_BR1_ /* DECL: BR1_ */, .BR2_BR2_ /* DECL: BR2_ */, .BG1_BG1_ /* DECL: BG1_ */, .BG2_BG2_ /* DECL: BG2_ */, .TS_TS_ /* DECL: TS_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .DBG1_DBG1_ /* DECL: DBG1_ */, .DBG2_DBG2_ /* DECL: DBG2_ */, clk /* DECL: clk */, BR1_ /* DECL: BR1_ */, BR2_ /* DECL: BR2_ */, BG1_ /* DECL: BG1_ */, BG2_ /* DECL: BG2_ */, TS_ /* DECL: TS_ */, AACK_ /* DECL: AACK_ */, ARTRY_ /* DECL: ARTRY_ */, DBG1_ /* DECL: DBG1_ */, DBG2_ /* DECL: DBG2_ */);
input clk;
input BR1_;
input BR2_;
output BG1_;
output BG2_;
input TS_;
input AACK_;
input ARTRY_;
output DBG1_;
output DBG2_;
wire bus_request;
/* DECL: null */
ArbiterStatus null
(
);
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(arb2)'...
Bindings: {clk=clk, BR1_=BR1_, BR2_=BR2_, BG1_=BG1_, BG2_=BG2_, TS_=TS_, AACK_=AACK_, ARTRY_=ARTRY_, DBG1_=DBG1_, DBG2_=DBG2_, bus_request=bus_request}
Variables: {clk=DECLARATION(clk), BR1_=DECLARATION(BR1_), BR2_=DECLARATION(BR2_), BG1_=DECLARATION(BG1_), BG2_=DECLARATION(BG2_), TS_=DECLARATION(TS_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), DBG1_=DECLARATION(DBG1_), DBG2_=DECLARATION(DBG2_), bus_request=DECLARATION(bus_request)}
Module 'ArbiterStatus' cannot be found
</pre>
<p>To reproduce the bug, uncomment the <strong>runTest_PPC60X_bus_src_arbiter</strong> method in <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase</strong> and run it.</p> Retrascope - Bug #7594 (Rejected): ModelSim shows error when TST file contains multiple commentshttps://forge.ispras.ru/issues/75942016-10-10T11:26:48ZSergey Smolovsmolov@ispras.ru
<ol>
<li>** Fatal: (vsim-3551) TEXTIO : Read past end of file "B02_test.tst".</li>
<li> Time: 325 ns Iteration: 0 Process: /b02_testbench/read_stimuli File: B02_testbench.vhd</li>
<li>Fatal error in Process read_stimuli at B02_testbench.vhd line 66</li>
<li></li>
<li>HDL call sequence:</li>
<li>Stopped at B02_testbench.vhd 66 Process read_stimuli
#</li>
</ol> Retrascope - Bug #7423 (Rejected): rnd_fsm.vhd: empty tst filehttps://forge.ispras.ru/issues/74232016-07-26T09:17:40ZSergey Smolovsmolov@ispras.ru
<p>The RETGA-based test generation engine produces an <strong>empty</strong> test for the attached VHDL design.<br />Here is the tool cmdline:<br /><pre>
<path-to-design>/rnd_fsm.vhd --target vhdl-testbench --engine efsm-test-generator --overwrite-existing --loop-limit 25
</pre></p> Retrascope - Task #6808 (Rejected): Split CFG processes into independent partshttps://forge.ispras.ru/issues/68082016-02-04T09:18:30ZSergey Smolovsmolov@ispras.ru
<p>1. Annotate CFG representation basic block statements with information about control flow (from parent switch statements) and data flow (from other basic blocks) dependencies.<br />2. Create an oriented graph of such dependencies.<br />3. Split the graph into connected components.<br />4. Split CFG representation objects into connected components are received from step 3.</p> Retrascope - Bug #6366 (Rejected): src/test/vhdl/example/test.vhd: Efsm.UNINITIALISED_STATE isn't...https://forge.ispras.ru/issues/63662015-10-23T12:02:54ZSergey Smolovsmolov@ispras.ru
<p>2015.10.23 14:49:36.729. INFO: Retrascope is starting<br />2015.10.23 14:49:36.729. INFO: Running: vhdl-parser</p>
<p>2015.10.23 14:49:36.729. INFO: Options: {args=/home/ssedai/projects/retrascope.svn/build/resources/test/example/test.vhd --target vhdl-testbench --toplevel test --engine efsm-test-generator --overwrite-existing --loop-limit 25, vhd=[/home/ssedai/projects/retrascope.svn/build/resources/test/example/test.vhd]}</p>
<p>2015.10.23 14:49:37.164. INFO: Storing: cfg</p>
<p>2015.10.23 14:49:37.165. INFO: Running: cfg-cfginterface-extractor</p>
<p>2015.10.23 14:49:37.165. INFO: Options: {args=/home/ssedai/projects/retrascope.svn/build/resources/test/example/test.vhd --target vhdl-testbench --toplevel test --engine efsm-test-generator --overwrite-existing --loop-limit 25, cfg=<cfg>}</p>
<p>2015.10.23 14:49:37.165. INFO: Storing: cfg-iface</p>
<p>2015.10.23 14:49:37.165. INFO: Running: cfg-cgaa-transformer</p>
<p>2015.10.23 14:49:37.165. INFO: Options: {args=/home/ssedai/projects/retrascope.svn/build/resources/test/example/test.vhd --target vhdl-testbench --toplevel test --engine efsm-test-generator --overwrite-existing --loop-limit 25, cfg=<cfg>}</p>
<p>2015.10.23 14:49:37.165. INFO: Storing: cgaa</p>
<p>2015.10.23 14:49:37.165. INFO: Running: cgaa-efsm-transformer</p>
<p>2015.10.23 14:49:37.165. INFO: Options: {cgaa=<cgaa>, args=/home/ssedai/projects/retrascope.svn/build/resources/test/example/test.vhd --target vhdl-testbench --toplevel test --engine efsm-test-generator --overwrite-existing --loop-limit 25}</p>
<p>2015.10.23 14:49:37.287. INFO: Number of GADD paths: 4<br />2015.10.23 14:49:37.287. INFO: ======================================<br />2015.10.23 14:49:37.287. INFO: Clock-like variables: [CLK, RESET].<br />2015.10.23 14:49:37.287. INFO: Transforming the process of module: TEST.<br />2015.10.23 14:49:37.287. INFO: 1 states are extracted.<br />2015.10.23 14:49:37.288. INFO: The state-like variables are: [].<br />2015.10.23 14:49:37.288. INFO: 2 transitions are extracted.<br />2015.10.23 14:49:37.288. WARNING: Extra resetting transition has been found: {source state: true; destination state: true; guarded action: {{posedge of CLK}: {true; (EQ RESET 0); (NOT (EQ RESET 1))}->{{C[0:0] := 1}}}}<br />2015.10.23 14:49:37.289. INFO: 1 <abbr title="s">EFSM</abbr> are extracted.<br />2015.10.23 14:49:37.289. INFO: Storing: efsm</p>
<p>2015.10.23 14:49:37.289. INFO: Running: efsm-test-generator</p>
<p>2015.10.23 14:49:37.289. INFO: Options: {efsm=<efsm>, args=/home/ssedai/projects/retrascope.svn/build/resources/test/example/test.vhd --target vhdl-testbench --toplevel test --engine efsm-test-generator --overwrite-existing --loop-limit 25}</p>
<p>2015.10.23 14:49:37.289. INFO: EFSM.TestGenerator: module TEST: starting test generation</p>
<p>Efsm.UNINITIALISED_STATE isn't supported yet<br />ru.ispras.retrascope.basis.exception.RetrascopeRuntimeException: Efsm.UNINITIALISED_STATE isn't supported yet<br /> at ru.ispras.retrascope.engine.efsm.simulator.ProcessSimulator.reset(ProcessSimulator.java:167)<br /> at ru.ispras.retrascope.engine.efsm.simulator.ProcessSimulator.<init>(ProcessSimulator.java:108)<br /> at ru.ispras.retrascope.engine.efsm.simulator.ModuleSimulator.<init>(ModuleSimulator.java:79)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.Generator.<init>(Generator.java:75)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.EfsmTestGenerator.start(EfsmTestGenerator.java:117)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.EfsmTestGenerator.start(EfsmTestGenerator.java:43)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:217)<br /> at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:110)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:217)<br /> at ru.ispras.retrascope.Retrascope$ToolRun.start(Retrascope.java:199)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:375)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:395)<br /> at ru.ispras.retrascope.util.VhdlUtilTest.runRetrascope(VhdlUtilTest.java:169)<br /> at ru.ispras.retrascope.util.VhdlUtilTest.runVhdl(VhdlUtilTest.java:81)<br /> at ru.ispras.retrascope.util.HdlUtilTest.runVhdl(HdlUtilTest.java:97)<br /> at ru.ispras.retrascope.engine.test.printer.testbench.vhdl.TestVhdlTestbenchPrinterVhdlTestCase.generate(TestVhdlTestbenchPrinterVhdlTestCase.java:38)</p> Retrascope - Bug #5648 (Rejected): EfsmSimulator.executeAssignment -> Unsupported data type of ra...https://forge.ispras.ru/issues/56482015-02-22T16:18:15ZSergey Smolovsmolov@ispras.ru
<p>Command line arguments: src\test\vhdl\itc99-poli2\b12\b12.vhd --target test --toplevel b12 --engine efsm-fate-test-generator</p>
<pre>
java.lang.IllegalArgumentException: Unsupported data type of ranged variable: (MAP LOGIC_INTEGER LOGIC_INTEGER)
at ru.ispras.retrascope.engine.efsm.simulator.EfsmSimulator.executeAssignment(EfsmSimulator.java:623)
at ru.ispras.retrascope.engine.efsm.simulator.EfsmSimulator.executeAction(EfsmSimulator.java:578)
at ru.ispras.retrascope.engine.efsm.simulator.EfsmSimulator.initialise(EfsmSimulator.java:300)
at ru.ispras.retrascope.engine.efsm.simulator.EfsmSimulator.processEvents(EfsmSimulator.java:259)
at ru.ispras.retrascope.engine.efsm.generator.test.fate.RandomFateGenerator.generateInputVectorRandomly(RandomFateGenerator.java:194)
at ru.ispras.retrascope.engine.efsm.generator.test.fate.RandomFateGenerator$RandomFateSequenceIterator.next(RandomFateGenerator.java:506)
at ru.ispras.retrascope.engine.efsm.generator.test.fate.RandomFateGenerator$RandomFateSequenceIterator.next(RandomFateGenerator.java:490)
at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGenerator.start(EfsmFateTestGenerator.java:264)
at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGenerator.start(EfsmFateTestGenerator.java:51)
at ru.ispras.retrascope.basis.Engine.start(Engine.java:199)
at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:106)
at ru.ispras.retrascope.basis.Engine.start(Engine.java:199)
at ru.ispras.retrascope.Retrascope$Run.start(Retrascope.java:115)
at ru.ispras.retrascope.Retrascope.main(Retrascope.java:331)
at ru.ispras.retrascope.Retrascope.main(Retrascope.java:353)
</pre> Retrascope - Bug #5263 (Rejected): [efsm][generator][test] EfsmTestGeneratorTestCase -> java.lang...https://forge.ispras.ru/issues/52632014-09-11T10:29:41ZSergey Smolovsmolov@ispras.ru
<p>Тест падает спустя два часа работы с ошибкой:</p>
<p><code>java.lang.OutOfMemoryError: Java heap space</code></p>
<p>Характеристики машины, на которой выполнялся тест:</p>
<p>cpu: AMD Athlon(tm) 64 X2 Dual Core Processor 4200+, 2211 MHz<br />RAM: 2 GB</p>