Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692020-04-09T13:28:43ZOpen-Source Projects
Redmine Verilog Translator - Bug #10246 (Rejected): ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest...https://forge.ispras.ru/issues/102462020-04-09T13:28:43ZSergey Smolovsmolov@ispras.ru
<p>The tool takes 'lut_output.v' Verilog files as input, but reports it's absence.<br /><pre>
ERROR: Module 'lut_output' has not been found
ERROR: [Internal] null
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkFalse(InvariantChecks.java:68)
at ru.ispras.verilog.parser.VerilogTranslator.exit(VerilogTranslator.java:126)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:397)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:231)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:212)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogQuipTestSuite.runTest_nut_001(VerilogQuipTestSuite.java:355)
</pre></p> Verilog Translator - Bug #10214 (Rejected): ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest...https://forge.ispras.ru/issues/102142020-04-06T08:16:08ZSergey Smolovsmolov@ispras.ru
<pre>
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\nut_000\nut_000_lut.v line 7:0 no viable alternative at input 'module'
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 30417:21 mismatched tree node: <unexpected: [@116916,240:245='module',<123>,7:0], resync=modulecarry_sum(sin,cin,sout,cout);inputsin;inputcin;outputsout;outputcout;> expecting AST_MODULE_ITEMS
ERROR: [Internal] null
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.verilog.parser.core.AbstractNode.add(AbstractNode.java:382)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:718)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:665)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:443)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:448)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:474)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:478)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:206)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogQuipTestSuite.runTest_nut_000(VerilogQuipTestSuite.java:302)
</pre> Verilog Translator - Bug #9773 (Rejected): ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_1...https://forge.ispras.ru/issues/97732019-07-26T08:36:42ZSergey Smolovsmolov@ispras.ru
<pre>
java.lang.ClassCastException: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.checkFunctionCall(VerilogStaticChecker.java:642)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.access$000(VerilogStaticChecker.java:71)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker$ExprTreeVisitor.onOperationBegin(VerilogStaticChecker.java:96)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:139)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:464)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:476)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:493)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:523)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:536)
at ru.ispras.verilog.parser.checker.VerilogStaticChecker.onAssignStatementBegin(VerilogStaticChecker.java:134)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(VerilogNodeVisitor.java:265)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:87)
at ru.ispras.verilog.parser.VerilogSyntaxBackend.start(VerilogSyntaxBackend.java:80)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:181)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:72)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:58)
at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1(VerilogIeeeTestCase.java:928)
</pre> Verilog Translator - Bug #9276 (Rejected): no errors returned for bug-with-macro-containing modulehttps://forge.ispras.ru/issues/92762018-09-12T08:34:43ZSergey Smolovsmolov@ispras.ru
<p>The Texas'97 'three_processor.v' module has bugs with macro usages (sometimes "MACRO_NAME" is used, not "`MACRO_NAME"), but the Verilog Translator does not return any error.</p>
<p>Run ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_cache_coherence_three_processor test method.</p> Verilog Translator - Bug #9215 (Rejected): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTes...https://forge.ispras.ru/issues/92152018-08-11T15:24:15ZSergey Smolovsmolov@ispras.ru
<pre>
Module name: mem
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 47:19 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 50:19 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 147:5 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 148:12 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 171:5 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 179:5 mismatched input 'reg' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 47:8 required (...)+ loop did not match anything at input 'wire'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 47:8 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Starting the backend 'printer'...
module mem(.clkclk /* DECL: clk */, .TS_TS_ /* DECL: TS_ */, .TTTT /* DECL: TT */, .GBL_GBL_ /* DECL: GBL_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .DBB_DBB_ /* DECL: DBB_ */, .TA_TA_ /* DECL: TA_ */, .DRTRY_DRTRY_ /* DECL: DRTRY_ */, .BG1_BG1_ /* DECL: BG1_ */, .BG2_BG2_ /* DECL: BG2_ */, .DBG1_DBG1_ /* DECL: DBG1_ */, clk /* DECL: clk */, TS_ /* DECL: TS_ */, TT /* DECL: TT */, GBL_ /* DECL: GBL_ */, AACK_ /* DECL: AACK_ */, ARTRY_ /* DECL: ARTRY_ */, DBB_ /* DECL: DBB_ */, TA_ /* DECL: TA_ */, DRTRY_ /* DECL: DRTRY_ */, BG1_ /* DECL: BG1_ */, BG2_ /* DECL: BG2_ */, DBG1_ /* DECL: DBG1_ */);
input clk;
input TS_;
input [00000000000000000000000000000000:00000000000000000000000000000100] TT;
input GBL_;
output AACK_;
input ARTRY_;
input DBB_;
output TA_;
output DRTRY_;
input BG1_;
input BG2_;
input DBG1_;
/* DECL: null */
AddrStatus null
(
);
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(mem)'...
Bindings: {clk=clk, TS_=TS_, TT=TT, GBL_=GBL_, AACK_=AACK_, ARTRY_=ARTRY_, DBB_=DBB_, TA_=TA_, DRTRY_=DRTRY_, BG1_=BG1_, BG2_=BG2_, DBG1_=DBG1_}
Variables: {clk=DECLARATION(clk), TS_=DECLARATION(TS_), TT=DECLARATION(TT), GBL_=DECLARATION(GBL_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), DBB_=DECLARATION(DBB_), TA_=DECLARATION(TA_), DRTRY_=DECLARATION(DRTRY_), BG1_=DECLARATION(BG1_), BG2_=DECLARATION(BG2_), DBG1_=DECLARATION(DBG1_)}
Module 'AddrStatus' cannot be found
</pre>
<p>To reproduce the bug, uncomment the <strong>runTest_PPC60X_bus_src_mem</strong> method in <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase</strong> and run it.</p> Verilog Translator - Bug #9214 (Rejected): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTes...https://forge.ispras.ru/issues/92142018-08-11T15:16:52ZSergey Smolovsmolov@ispras.ru
<pre>
Module name: cpu
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 155:17 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 157:14 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 159:16 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 161:14 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 228:37 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 229:44 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 230:36 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 233:26 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 234:33 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 235:27 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 236:34 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 321:33 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 322:33 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 323:32 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 324:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 325:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 326:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 327:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 328:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 329:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 330:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 331:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 332:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 333:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 334:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 338:39 extraneous input '&&' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 339:28 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 341:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 342:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 346:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 347:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 348:36 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 349:43 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 350:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 351:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 352:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 353:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 354:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 356:40 mismatched input '&&' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 356:46 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 359:36 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 360:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 361:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 362:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 363:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 364:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 365:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 387:47 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 388:43 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 389:46 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 390:19 extraneous input ')' expecting SEMI
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 403:51 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 404:58 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 407:44 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 408:51 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 409:45 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 410:52 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 436:14 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 643:74 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 644:46 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 645:39 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 646:45 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 647:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 648:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 649:44 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 650:42 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 651:39 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 652:48 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 653:56 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 654:41 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 655:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 656:47 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 885:6 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 906:29 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 907:32 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 908:29 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 909:29 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 909:57 mismatched input ')' expecting COLON
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 939:16 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 941:16 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 943:16 mismatched input 'wire' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 155:3 required (...)+ loop did not match anything at input 'reg'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 155:3 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR_[]' has been found: DECLARATION(BR_)
Declaration of 'BG_[]' has been found: DECLARATION(BG_)
Declaration of 'ABB_[]' has been found: DECLARATION(ABB_)
Declaration of 'ABB1_[]' has been found: DECLARATION(ABB1_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TS1_[]' has been found: DECLARATION(TS1_)
Declaration of 'AP[]' has been found: DECLARATION(AP)
Declaration of 'APE_[]' has been found: DECLARATION(APE_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'TT1[]' has been found: DECLARATION(TT1)
Declaration of 'TSIZ[]' has been found: DECLARATION(TSIZ)
Declaration of 'TBST_[]' has been found: DECLARATION(TBST_)
Declaration of 'TBST1_[]' has been found: DECLARATION(TBST1_)
Declaration of 'TC[]' has been found: DECLARATION(TC)
Declaration of 'CI_[]' has been found: DECLARATION(CI_)
Declaration of 'WT_[]' has been found: DECLARATION(WT_)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'GBL1_[]' has been found: DECLARATION(GBL1_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'ARTRY1_[]' has been found: DECLARATION(ARTRY1_)
Declaration of 'SHD_[]' has been found: DECLARATION(SHD_)
Declaration of 'DBG_[]' has been found: DECLARATION(DBG_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'DBB1_[]' has been found: DECLARATION(DBB1_)
Declaration of 'DP[]' has been found: DECLARATION(DP)
Declaration of 'DPE_[]' has been found: DECLARATION(DPE_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR_[]' has been found: DECLARATION(BR_)
Declaration of 'BG_[]' has been found: DECLARATION(BG_)
Declaration of 'ABB_[]' has been found: DECLARATION(ABB_)
Declaration of 'ABB1_[]' has been found: DECLARATION(ABB1_)
Declaration of 'TS1_[]' has been found: DECLARATION(TS1_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'AP[]' has been found: DECLARATION(AP)
Declaration of 'APE_[]' has been found: DECLARATION(APE_)
Declaration of 'TT1[]' has been found: DECLARATION(TT1)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'TSIZ[]' has been found: DECLARATION(TSIZ)
Declaration of 'TBST1_[]' has been found: DECLARATION(TBST1_)
Declaration of 'TBST_[]' has been found: DECLARATION(TBST_)
Declaration of 'TC[]' has been found: DECLARATION(TC)
Declaration of 'CI_[]' has been found: DECLARATION(CI_)
Declaration of 'WT_[]' has been found: DECLARATION(WT_)
Declaration of 'GBL1_[]' has been found: DECLARATION(GBL1_)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY1_[]' has been found: DECLARATION(ARTRY1_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'SHD_[]' has been found: DECLARATION(SHD_)
Declaration of 'DBG_[]' has been found: DECLARATION(DBG_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'DBB1_[]' has been found: DECLARATION(DBB1_)
Declaration of 'DP[]' has been found: DECLARATION(DP)
Declaration of 'DPE_[]' has been found: DECLARATION(DPE_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Starting the backend 'printer'...
module cpu(.clkclk /* DECL: clk */, .BR_BR_ /* DECL: BR_ */, .BG_BG_ /* DECL: BG_ */, .ABB_ABB_ /* DECL: ABB_ */, .ABB1_ABB1_ /* DECL: ABB1_ */, .TS_TS_ /* DECL: TS_ */, .TS1_TS1_ /* DECL: TS1_ */, .APAP /* DECL: AP */, .APE_APE_ /* DECL: APE_ */, .TTTT /* DECL: TT */, .TT1TT1 /* DECL: TT1 */, .TSIZTSIZ /* DECL: TSIZ */, .TBST_TBST_ /* DECL: TBST_ */, .TBST1_TBST1_ /* DECL: TBST1_ */, .TCTC /* DECL: TC */, .CI_CI_ /* DECL: CI_ */, .WT_WT_ /* DECL: WT_ */, .GBL_GBL_ /* DECL: GBL_ */, .GBL1_GBL1_ /* DECL: GBL1_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .ARTRY1_ARTRY1_ /* DECL: ARTRY1_ */, .SHD_SHD_ /* DECL: SHD_ */, .DBG_DBG_ /* DECL: DBG_ */, .DBB_DBB_ /* DECL: DBB_ */, .DBB1_DBB1_ /* DECL: DBB1_ */, .DPDP /* DECL: DP */, .DPE_DPE_ /* DECL: DPE_ */, .TA_TA_ /* DECL: TA_ */, .DRTRY_DRTRY_ /* DECL: DRTRY_ */, clk /* DECL: clk */, BR_ /* DECL: BR_ */, BG_ /* DECL: BG_ */, ABB_ /* DECL: ABB_ */, ABB1_ /* DECL: ABB1_ */, TS1_ /* DECL: TS1_ */, TS_ /* DECL: TS_ */, AP /* DECL: AP */, APE_ /* DECL: APE_ */, TT1 /* DECL: TT1 */, TT /* DECL: TT */, TSIZ /* DECL: TSIZ */, TBST1_ /* DECL: TBST1_ */, TBST_ /* DECL: TBST_ */, TC /* DECL: TC */, CI_ /* DECL: CI_ */, WT_ /* DECL: WT_ */, GBL1_ /* DECL: GBL1_ */, GBL_ /* DECL: GBL_ */, AACK_ /* DECL: AACK_ */, ARTRY1_ /* DECL: ARTRY1_ */, ARTRY_ /* DECL: ARTRY_ */, SHD_ /* DECL: SHD_ */, DBG_ /* DECL: DBG_ */, DBB_ /* DECL: DBB_ */, DBB1_ /* DECL: DBB1_ */, DP /* DECL: DP */, DPE_ /* DECL: DPE_ */, TA_ /* DECL: TA_ */, DRTRY_ /* DECL: DRTRY_ */);
input clk;
output BR_;
input BG_;
input ABB_;
output ABB1_;
output TS1_;
input TS_;
output [00000000000000000000000000000000:00000000000000000000000000000011] AP;
output APE_;
output [00000000000000000000000000000100:00000000000000000000000000000000] TT1;
input [00000000000000000000000000000100:00000000000000000000000000000000] TT;
output [00000000000000000000000000000010:00000000000000000000000000000000] TSIZ;
output TBST1_;
input TBST_;
output [00000000000000000000000000000000:00000000000000000000000000000010] TC;
output CI_;
output WT_;
output GBL1_;
input GBL_;
input AACK_;
output ARTRY1_;
input ARTRY_;
output SHD_;
input DBG_;
input DBB_;
output DBB1_;
output [00000000000000000000000000000000:00000000000000000000000000000111] DP;
output DPE_;
input TA_;
input DRTRY_;
/* DECL: null */
AddressTenure null
(
);
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(cpu)'...
Bindings: {clk=clk, BR_=BR_, BG_=BG_, ABB_=ABB_, ABB1_=ABB1_, TS_=TS_, TS1_=TS1_, AP=AP, APE_=APE_, TT=TT, TT1=TT1, TSIZ=TSIZ, TBST_=TBST_, TBST1_=TBST1_, TC=TC, CI_=CI_, WT_=WT_, GBL_=GBL_, GBL1_=GBL1_, AACK_=AACK_, ARTRY_=ARTRY_, ARTRY1_=ARTRY1_, SHD_=SHD_, DBG_=DBG_, DBB_=DBB_, DBB1_=DBB1_, DP=DP, DPE_=DPE_, TA_=TA_, DRTRY_=DRTRY_}
Variables: {clk=DECLARATION(clk), BR_=DECLARATION(BR_), BG_=DECLARATION(BG_), ABB_=DECLARATION(ABB_), ABB1_=DECLARATION(ABB1_), TS_=DECLARATION(TS_), TS1_=DECLARATION(TS1_), AP=DECLARATION(AP), APE_=DECLARATION(APE_), TT=DECLARATION(TT), TT1=DECLARATION(TT1), TSIZ=DECLARATION(TSIZ), TBST_=DECLARATION(TBST_), TBST1_=DECLARATION(TBST1_), TC=DECLARATION(TC), CI_=DECLARATION(CI_), WT_=DECLARATION(WT_), GBL_=DECLARATION(GBL_), GBL1_=DECLARATION(GBL1_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), ARTRY1_=DECLARATION(ARTRY1_), SHD_=DECLARATION(SHD_), DBG_=DECLARATION(DBG_), DBB_=DECLARATION(DBB_), DBB1_=DECLARATION(DBB1_), DP=DECLARATION(DP), DPE_=DECLARATION(DPE_), TA_=DECLARATION(TA_), DRTRY_=DECLARATION(DRTRY_)}
Module 'AddressTenure' cannot be found
</pre>
<p>To reproduce the bug, uncomment the <strong>runTest_PPC60X_bus_src_cpu</strong> method in <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase</strong> and run it.</p> Verilog Translator - Bug #9213 (Rejected): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTes...https://forge.ispras.ru/issues/92132018-08-11T15:14:35ZSergey Smolovsmolov@ispras.ru
<pre>
Module name: arb2
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/arbiter.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/arbiter.v line 60:15 mismatched input 'reg' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 60:1 required (...)+ loop did not match anything at input 'reg'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 60:1 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR1_[]' has been found: DECLARATION(BR1_)
Declaration of 'BR2_[]' has been found: DECLARATION(BR2_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Declaration of 'DBG2_[]' has been found: DECLARATION(DBG2_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR1_[]' has been found: DECLARATION(BR1_)
Declaration of 'BR2_[]' has been found: DECLARATION(BR2_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Declaration of 'DBG2_[]' has been found: DECLARATION(DBG2_)
Starting the backend 'printer'...
module arb2(.clkclk /* DECL: clk */, .BR1_BR1_ /* DECL: BR1_ */, .BR2_BR2_ /* DECL: BR2_ */, .BG1_BG1_ /* DECL: BG1_ */, .BG2_BG2_ /* DECL: BG2_ */, .TS_TS_ /* DECL: TS_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .DBG1_DBG1_ /* DECL: DBG1_ */, .DBG2_DBG2_ /* DECL: DBG2_ */, clk /* DECL: clk */, BR1_ /* DECL: BR1_ */, BR2_ /* DECL: BR2_ */, BG1_ /* DECL: BG1_ */, BG2_ /* DECL: BG2_ */, TS_ /* DECL: TS_ */, AACK_ /* DECL: AACK_ */, ARTRY_ /* DECL: ARTRY_ */, DBG1_ /* DECL: DBG1_ */, DBG2_ /* DECL: DBG2_ */);
input clk;
input BR1_;
input BR2_;
output BG1_;
output BG2_;
input TS_;
input AACK_;
input ARTRY_;
output DBG1_;
output DBG2_;
wire bus_request;
/* DECL: null */
ArbiterStatus null
(
);
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(arb2)'...
Bindings: {clk=clk, BR1_=BR1_, BR2_=BR2_, BG1_=BG1_, BG2_=BG2_, TS_=TS_, AACK_=AACK_, ARTRY_=ARTRY_, DBG1_=DBG1_, DBG2_=DBG2_, bus_request=bus_request}
Variables: {clk=DECLARATION(clk), BR1_=DECLARATION(BR1_), BR2_=DECLARATION(BR2_), BG1_=DECLARATION(BG1_), BG2_=DECLARATION(BG2_), TS_=DECLARATION(TS_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), DBG1_=DECLARATION(DBG1_), DBG2_=DECLARATION(DBG2_), bus_request=DECLARATION(bus_request)}
Module 'ArbiterStatus' cannot be found
</pre>
<p>To reproduce the bug, uncomment the <strong>runTest_PPC60X_bus_src_arbiter</strong> method in <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase</strong> and run it.</p> Retrascope - Task #6511 (Rejected): keep expressions at case statementshttps://forge.ispras.ru/issues/65112016-01-19T08:40:47ZSergey Smolovsmolov@ispras.ru
<p>Keep not possible <code>NodeValue</code> values of switch expression in it's case statements, but expressions too.<br />Default case statements should be eliminated.</p> Retrascope - Task #6509 (Rejected): merge embedded switch nodes with conditions depending exactly...https://forge.ispras.ru/issues/65092016-01-17T15:54:28ZSergey Smolovsmolov@ispras.ru
<p>Backend that merges embedded switch statements. Supposing that they have f(x) and g(x) conditions respectively,<br />it merges them into one switch with the following condition:<br /><pre>
cond(f, C) ? fg : f
</pre><br />where <code>cond(f, C)</code> is an extression that is built from <code>f</code> condition and it's possible values of it's child <code>C</code> case statement (that is a parent for <code>g</code> switch statement), and <code>fg</code> is a concatenation. All the chidl case statements for <code>g</code> statements should modify their values to the bitvector datatype and should have "cond(f, C)" prefix.</p> Retrascope - Task #6412 (Rejected): engine combining HLDD & assertion modelhttps://forge.ispras.ru/issues/64122015-11-09T10:48:09ZSergey Smolovsmolov@ispras.ru
<p>Engine that combines HLDD and AssertionModel.</p> Retrascope - Bug #6362 (Rejected): src/test/verilog/adder/adder4_testbench.v: wrong CFG modelhttps://forge.ispras.ru/issues/63622015-10-21T14:56:38ZSergey Smolovsmolov@ispras.ru
<p>The Verilog parser generates incorrect CFG model for adder4_testbench.v file.<br />Please look at GraphML representation of CFG model which was generated with disabled backends. This graph does not contain BasicBock node for "a = a + 1" assignment.<br />Note that this bug can be reproduced at revision 1639, when the last your change was made.</p> Retrascope - Task #5609 (Rejected): make process-local variables be efsm-model-globalhttps://forge.ispras.ru/issues/56092015-02-11T08:57:16ZSergey Smolovsmolov@ispras.ru
<p>While EFSM models being extracted from CFG processes, they should have global variables only (in terms of EfsmModel).It means, that when different CFG processes have different local variables, these variables should be transformed into global variables of the final EfsmModel.</p> Retrascope - Task #5507 (Rejected): [engine][basis] implement PrinterEnginehttps://forge.ispras.ru/issues/55072014-12-16T14:34:33ZSergey Smolovsmolov@ispras.ru
<p>Implement PrinterEngine as basic class for all the engines that are from 'Printer' category - stores an input data into file.</p> C++TESK Testing ToolKit - Bug #4005 (Rejected): удалить пустой READMEhttps://forge.ispras.ru/issues/40052013-03-15T14:17:10ZSergey Smolovsmolov@ispras.ru
<p>Что делает пустой файл README в trunk основного проекта?</p> Fortress - Task #3914 (Rejected): function templateshttps://forge.ispras.ru/issues/39142013-02-05T10:34:46ZSergey Smolovsmolov@ispras.ru
<p>Реализовать поддержку шаблонов функций. В зависимости от типа аргументов должны генерироваться корректные функции.</p>