Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692019-11-13T12:01:33ZOpen-Source Projects
Redmine Verilog Translator - Bug #9915 (Closed): "Cycle inclusion has been detected in fine <filename>" e...https://forge.ispras.ru/issues/99152019-11-13T12:01:33ZSergey Smolovsmolov@ispras.ru
<p>The tool reports "Cycle inclusion has been detected in fine <filename>" error for the case when "a.v" and "b.v" modules include "c.v" module.</p>
<p>To reproduce the bug, checkout to <a class="changeset" title="hdl-benchmark submodule update Signed-off-by: chudnovmaxim <chudnov@ispras.ru>" href="https://forge.ispras.ru/projects/veritrans/repository/veritrans/revisions/5ca788cdbc460bf393ccdef4b9cd6451f71acdd0">5ca788cd</a> commit and run <strong>ru.ispras.verilog.parser.VerilogQuipTestCase</strong>. It should be fail-free, but it is not.</p>
<p>IMPORTANT: please run all the project tests before push and compare your results with Jenkins!</p> Retrascope - Task #9911 (Closed): merge "*/sample/*TestCase" Java test cases https://forge.ispras.ru/issues/99112019-11-12T08:52:05ZSergey Smolovsmolov@ispras.ru
<p>There are separate "*/sample/*TestCase" Java classes in the project. They contain duplicated code and should be merged the same way as benchmark-related test case collections at Verilog Translator project. See <strong>ru.ispras.verilog.parser.VerilogQuipTestCase</strong> for example.</p> Retrascope IDE - Task #9764 (New): migrate to Eclipse 2019https://forge.ispras.ru/issues/97642019-07-22T13:37:19ZSergey Smolovsmolov@ispras.ruVerilog Translator - Task #9311 (Closed): type casting of expression operandshttps://forge.ispras.ru/issues/93112018-10-05T15:09:31ZSergey Smolovsmolov@ispras.ru
<p>It is a common case for expressions in Verilog designs to have operands that become wrong via transforming to SMT\SMV format. Here are some examples.</p>
<p>1. In <em>vcegar-tests/mpeg/mpeg_1.v</em>:<br /><pre>
reg [15:0] NumBytes;
wire [3:0] timeStampBytes;
...
NumBytes = NumBytes - timeStampBytes;
</pre><br />Operands of "-" have different data types, so SMT solver reports an error.</p>
<p>2. In <em>verilog2smv-vis-tests/Vsa16/vsa16a.v</em>:<br /><pre>
output [15:0] ALUOutput;
reg [11:0] NPC;
wire [15:0] Imm = {{8{immFld[8]}},immFld[7:0]};
ALUOutput <= {4'd0,NPC} + {Imm,1'b0};
</pre><br />This expression produces the following error in nuXmv model checker:<br /><pre><code class="text syntaxhl" data-language="text">TYPE ERROR file vsa16a.smv: line 593 : illegal operand types of "+" : unsigned word[16] and unsigned word[17]
</code></pre><br />3. In <em>twoFifo1.v</em>:<br /><pre>
parameter LOGLENGTH = 2;
...
reg [LOGLENGTH-1:0] writehead;
...
for (i = 0; i <= LENGTH-1; i = i + 1) begin
if (((writehead < writetail) && (i >= writehead) &&
(i < writetail)) ||
((writehead > writetail) && ((i >= writehead) ||
(i < writetail)))) begin
if ((readempty == 0) &&
(readfifo[readhead] == writefifo[i])) begin
match <= 1;
storeaddr <= readhead;
end
end
</pre><br />The unrolled "for" loop produces the error in nuXmv model checker (probably the <em>i</em> counter value has 32-bit vector type):<br /><pre><code class="text syntaxhl" data-language="text">TYPE ERROR file twoFifo1.smv: line 762 : illegal operand types of "<" : unsigned word[32] and unsigned word[2]
</code></pre><br />4. In <em>verilog2smv-vis-tests/Ibuf/ibuf.v</em>:<br /><pre>
input [0:2] flush;
output [0:1] load0;
output [0:2] issue0;
output [0:2] issue1;
output [0:2] valid;
...
wire nv0 = ~flush[0] & (valid[0] & ~(issue0[0] | issue1[0]) | load0);
</pre><br />This expression produces the following error in nuXmv model checker:<br /><pre><code class="text syntaxhl" data-language="text">TYPE ERROR file ibuf.smv: line 164 : illegal operand types of "|" : unsigned word[1] and unsigned word[2]
</code></pre><br />5. In <em>verilog2smv-vis-tests/BufAl/bufferAlloc.v</em>:<br /><pre>
output nack;
reg [4:0] count;
reg alloc, free;
...
count = count + (alloc & ~nack) - (free & busy[free_addr]);
</pre><br />This expression produces the following error in nuXmv model checker:<br /><pre><code class="text syntaxhl" data-language="text">TYPE ERROR file bufferAlloc.smv: line 964 : illegal operand types of "+" : unsigned word[5] and unsigned word[1]
</code></pre></p> QEMU4V - Bug #9288 (Closed): /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’https://forge.ispras.ru/issues/92882018-09-28T08:44:54ZSergey Smolovsmolov@ispras.ru
<p>Compilation error:</p>
<pre>
/srv/****/workspace/QEMU4V/target/mips/translate.c: In function ‘gen_logic_imm’:
/srv/****/workspace/QEMU4V/target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’
else {
^~~~
/srv/****/workspace/QEMU4V/rules.mak:69: recipe for target 'target/mips/translate.o' failed
make[1]: *** [target/mips/translate.o] Error 1
Makefile:481: recipe for target 'subdir-mips-softmmu' failed
make: *** [subdir-mips-softmmu] Error 2
:make FAILED
</pre> Verilog Translator - Bug #9231 (Closed): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_...https://forge.ispras.ru/issues/92312018-08-17T07:50:34ZSergey Smolovsmolov@ispras.ru
<p>The test case produces the following exception:<br /><pre>
java.lang.NullPointerException
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_binary_operation(VerilogTreeBuilder.java:6931)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_operation(VerilogTreeBuilder.java:6225)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_expression(VerilogTreeBuilder.java:6060)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_binary_operation(VerilogTreeBuilder.java:6923)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_operation(VerilogTreeBuilder.java:6225)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_expression(VerilogTreeBuilder.java:6060)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_if_statement(VerilogTreeBuilder.java:4671)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4087)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:5171)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4117)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_case_statement_item(VerilogTreeBuilder.java:5513)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_case_statement(VerilogTreeBuilder.java:4835)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4097)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:5171)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4117)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_delayed_statement(VerilogTreeBuilder.java:4620)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4077)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_process(VerilogTreeBuilder.java:3202)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_item(VerilogTreeBuilder.java:946)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_module(VerilogTreeBuilder.java:674)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:516)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:466)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:250)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:255)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:270)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:274)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:168)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:72)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:58)
at ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2(VerilogTexas97TestCase.java:515)
</pre></p>
<p>The tool error log is:<br /><pre><code class="text syntaxhl" data-language="text">ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 155:23 no viable alternative at input ')'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 165:27 no viable alternative at input ')'
DEBUG: Expanding macro '3'b101' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 167:27 no viable alternative at input ')'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 167:42 no viable alternative at input ')'
DEBUG: Expanding macro '3'b011' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 176:23 no viable alternative at input ')'
DEBUG: Expanding macro '3'b011' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b100' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b100' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 192:23 no viable alternative at input ')'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 202:27 no viable alternative at input ')'
DEBUG: Expanding macro '3'b101' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 204:25 no viable alternative at input ')'
DEBUG: Expanding macro '3'b100' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b001' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b101' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b010' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b001' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b00' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b00' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b01' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b01' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b10' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b10' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b00' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b01' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b10' ...
DEBUG: End of the token source 'null'
ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 155:12 no viable alternative at input ')'
</code></pre></p> Verilog Translator - Bug #9230 (Closed): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_...https://forge.ispras.ru/issues/92302018-08-17T07:42:51ZSergey Smolovsmolov@ispras.ru
<p>The test case produces the following exception:<br /><pre>
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkFalse(InvariantChecks.java:68)
at ru.ispras.verilog.parser.VerilogTranslator.exit(VerilogTranslator.java:104)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:193)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:72)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:58)
at ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus(VerilogTexas97TestCase.java:483)
</pre></p>
<p>Here is the error log:<br /><pre><code class="text syntaxhl" data-language="text">ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 142:22 no viable alternative at input ')'
DEBUG: Expanding macro '3'b001' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 170:27 no viable alternative at input ')'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b100' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 184:20 no viable alternative at input ')'
DEBUG: Expanding macro '3'b011' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 197:37 no viable alternative at input ')'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 205:39 no viable alternative at input ')'
DEBUG: Expanding macro '3'b001' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 233:44 no viable alternative at input ')'
DEBUG: Expanding macro '3'b010' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 240:40 no viable alternative at input '&&'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 240:51 mismatched input ')' expecting COLON
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 243:20 no viable alternative at input ')'
DEBUG: Expanding macro '3'b001' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b100' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 275:4 mismatched input 'else' expecting KW_END
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 277:28 no viable alternative at input ')'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 277:43 no viable alternative at input ')'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 279:19 mismatched input '=' expecting LPAREN
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 280:19 mismatched input '=' expecting LPAREN
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 281:20 mismatched input '=' expecting LPAREN
DEBUG: Expanding macro '3'b000' ...
ERROR: line 282:15 mismatched input '=' expecting LPAREN
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 286:25 no viable alternative at input ')'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 287:23 mismatched input '=' expecting LPAREN
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 289:23 mismatched input '=' expecting LPAREN
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 290:19 mismatched input '=' expecting LPAREN
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 291:19 mismatched input '=' expecting LPAREN
DEBUG: Expanding macro '3'b011' ...
ERROR: line 292:15 mismatched input '=' expecting LPAREN
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/bus.v line 294:7 mismatched input 'end' expecting KW_ENDMODULE
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b001' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b100' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b100' ...
DEBUG: End of the token source 'null'
ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from line 0:0 mismatched tree node: <mismatched token: [@1039,6991:6993='end',<50>,294:7], resync=modulebus_cont(A,OPC,ACK,LOCK,READ,SEL_0,GNT_0,GNT_1,REQ_0,REQ_1,TOUT,clk);input[0:29]A;input[0:3]OPC;inputACK;inputLOCK;inputREAD;inputclk;inputREQ_0;inputREQ_1;outputGNT_0;outputGNT_1;outputSEL_0;outputTOUT;wire[2:0]ACK;wireGNT_0;wireGNT_1;wireSEL_0;wireTOUT;regGNT_reg_0;regGNT_reg_1;reg[0:7]TOUT_cnt;regr_TOUT;regselect_reg;regGNT_mux;reg[2:0]state;assignGNT_0=GNT_reg_0;assignGNT_1=GNT_reg_1;assignTOUT=r_TOUT;assignSEL_0=(A[0]==1)&&(A[1]==1)&&select_reg;initialbeginstate=3'b000;GNT_reg_0=0;GNT_reg_1=0;TOUT_cnt=8'b00000000;r_TOUT=0;select_reg=0;GNT_mux=0;endalways@(posedgeclk)begincase(state)BUS_IDLE:beginTOUT_cnt=8'b00000000;if((REQ_0==0)&&(REQ_1==0))state=3'b000;elseif(REQ_0==1&&REQ_1==1)beginGNT_reg_0=~GNT_mux;GNT_reg_1=GNT_mux;GNT_mux=~GNT_mux;state=3'b001;endelsebeginif(REQ_0==1)GNT_reg_0=1;elseGNT_reg_1=1;GNT_mux=(REQ_0==1)?1:0;state=3'b001;endendBUS_REQ:beginGNT_reg_0=0;GNT_reg_1=0;if(OPC==0)select_reg=0;elseselect_reg=1;state=3'b010;endBUS_ADDR:beginif((LOCK==1)&&(OPC==0))beginselect_reg=0;GNT_reg_0=0;GNT_reg_1=0;state=3'b010;endelseif((LOCK==0)&&(OPC==0))beginif(REQ_0==1||REQ_1==1)beginif(REQ_0==1&&REQ_1==1)beginGNT_reg_0=~GNT_mux;GNT_reg_1=GNT_mux;GNT_mux=~GNT_mux;endelsebeginif(REQ_0==1)GNT_reg_0=1;elseGNT_reg_1=1;GNT_mux=(REQ_0==1)?1:0;endstate=3'b001;endelsebeginGNT_reg_0=0;GNT_reg_1=0;TOUT_cnt=8'b00000000;state=3'b000;endendelseif((LOCK==0)&&(!(OPC==0)))beginselect_reg=0;if(ACK==)beginif(REQ_0==1||REQ_1==1)beginif(REQ_0==1&&REQ_1==1)beginGNT_reg_0=~GNT_mux;GNT_reg_1=GNT_mux;GNT_mux=~GNT_mux;endelsebeginif(REQ_0==1)GNT_reg_0=1;elseGNT_reg_1=1;GNT_mux=(REQ_0==1)?1:0;endstate=3'b001;endelsebeginGNT_reg_0=0;GNT_reg_1=0;TOUT_cnt=8'b00000000;state=3'b000;endendelseif(ACK==)beginGNT_reg_0=0;GNT_reg_1=0;TOUT_cnt=8'b00000000;state=3'b000;endelsebeginstate=3'b100;endendelsebeginif(ACK==)select_reg=1;elseselect_reg=0;GNT_reg_0=0;GNT_reg_1=0;state=3'b011;endendBUS_ADDRDATA:beginTOUT_cnt=TOUT_cnt+1;if(TOUT_cnt==255||ACK==)beginr_TOUT=1;TOUT_cnt=8'b00000000;GNT_reg_0=0;GNT_reg_1=0;state=3'b000;endelseif((LOCK==0)&&(ACK==)&&(OPC==0))beginif(REQ_0==1||REQ_1==1)beginif(REQ_0==1&&REQ_1==1)beginGNT_reg_0=~GNT_mux;GNT_reg_1=GNT_mux;GNT_mux=~GNT_mux;endelsebeginif(REQ_0==1)GNT_reg_0=1;elseGNT_reg_1=1;GNT_mux=(REQ_0==1)?1:0;endstate=3'b001;endelsebeginGNT_reg_0=0;GNT_reg_1=0;TOUT_cnt=8'b00000000;state=3'b000;endendelseif((LOCK==1)&&(ACK==)&&(OPC==0))beginGNT_reg_0=0;GNT_reg_1=0;select_reg=0;state=3'b010;endelseif(LOCK==0&&ACK==&&OPC!=0)beginselect_reg=0;if(ACK==)beginif(REQ_0==1||REQ_1==1)beginif(REQ_0==1&&REQ_1==1)beginGNT_reg_0=~GNT_mux;GNT_reg_1=GNT_mux;GNT_mux=~GNT_mux;endelsebeginif(REQ_0==1)GNT_reg_0=1;elseGNT_reg_1=1;GNT_mux=(REQ_0==1)?1:0;endstate=3'b001;endelsebeginGNT_reg_0=0;GNT_reg_1=0;TOUT_cnt=8'b00000000;state=3'b000;endendelsestate=3'b100;endelsebeginif(!((ACK==)||(ACK==)))beginGNT_reg_0=0;GNT_reg_1=0;select_reg=0;state=3'b000;endelsebeginif((ACK==)||(OPC==0))select_reg=0;elseselect_reg=1;GNT_reg_0=0;GNT_reg_1=0;state=3'b011;endendendBUS_DATA:beginTOUT_cnt=TOUT_cnt+1;if> expecting <UP>
</code></pre></p> Verilog Translator - Bug #9209 (Closed): java.util.EmptyStackException at ru.ispras.verilog.parse...https://forge.ispras.ru/issues/92092018-08-11T15:00:03ZSergey Smolovsmolov@ispras.ru
<pre>
java.util.EmptyStackException
at java.util.Stack.peek(Stack.java:102)
at ru.ispras.verilog.parser.util.TokenSourceStack.getLastParentToken(TokenSourceStack.java:70)
at ru.ispras.verilog.parser.util.TokenSourceStack.nextToken(TokenSourceStack.java:138)
at org.antlr.runtime.BufferedTokenStream.fetch(BufferedTokenStream.java:143)
at org.antlr.runtime.BufferedTokenStream.sync(BufferedTokenStream.java:137)
at org.antlr.runtime.CommonTokenStream.setup(CommonTokenStream.java:137)
at org.antlr.runtime.CommonTokenStream.LT(CommonTokenStream.java:94)
at ru.ispras.verilog.parser.grammar.VerilogParser.startRule(VerilogParser.java:435)
at ru.ispras.verilog.parser.VerilogFrontend.startParser(VerilogFrontend.java:230)
at ru.ispras.verilog.parser.VerilogFrontend.startParser(VerilogFrontend.java:240)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:265)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:275)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:162)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:64)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:50)
</pre>
<p>To reproduce the bug, run any of the following test cases:</p>
<p>ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Miim_vMiim<br />ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_BufAI_bufferAlloc<br />ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_BufAI_buf_bug</p> Verilog Translator - Bug #8786 (Closed): ru.ispras.verilog.parser.sample.FifoTestbenchTestCase failshttps://forge.ispras.ru/issues/87862018-03-27T14:38:56ZSergey Smolovsmolov@ispras.ru
<p>The same problem, that makes this test to be failed, appears while running Retrascope at Jenkins server with the following parameters:</p>
<pre>
/srv/jenkins/workspace/Retrascope/build/resources/test/fifo/fifo_testbench.v
--target cfg-iface
--include-path /srv/jenkins/workspace/Retrascope/build/resources/test/fifo
--module-name fifo_testbench
--engine cfg-cfginterface-extractor
</pre>
<p>Here comes an error like:</p>
<pre>
java.lang.IllegalArgumentException: Module 'fifo' cannot be found
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:109)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:334)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:176)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:56)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:163)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:51)
at ru.ispras.verilog.parser.sample.VerilogPrinterTestCase.runTest(VerilogPrinterTestCase.java:48)
</pre> Retrascope - Task #6490 (Closed): Gradle task & cmdline scripts for running the tool from terminalhttps://forge.ispras.ru/issues/64902015-12-29T11:37:37ZSergey Smolovsmolov@ispras.ruRetrascope - Task #6483 (Closed): keep related clock-like variables for top-level containers of E...https://forge.ispras.ru/issues/64832015-12-22T13:48:50ZSergey Smolovsmolov@ispras.ru
<p>For the purposes of SMV-based test generation it is necessary to store the related clock-like variable for every assertion-containing object that is built from top-level EFSM module.</p> Retrascope - Task #6367 (Closed): Fortress expressions printing in an SMV formathttps://forge.ispras.ru/issues/63672015-10-25T18:19:41ZSergey Smolovsmolov@ispras.ru
<p>We need utility methods for Fortress expressions printing in an SMV format.</p>
<p>The most wanted use case is:</p>
<p>we have a collection of Fortress expressions: <code>e[1]</code>, <code>e[2]</code>, ... , <code>e[n]</code>;<br />we want to produce and SMV file of the following structure (it is supposed to be so):</p>
<pre>
declarations(e[1])
...
declarations(e[n])
formula(e[1])
...
formula(e[n])
</pre>
<p>where i = 1, ... , n; <code>declarations(e[i])</code> is a list of variable declarations that are used in <code>e[i]</code> expression; <code>formula(e[i])</code> is an SMV equivalent for <code>e[i]</code> expression.</p> Retrascope - Bug #5719 (Closed): EFSM Test Generator hangs on b11https://forge.ispras.ru/issues/57192015-03-18T07:20:55ZSergey Smolovsmolov@ispras.ru
<p>The EFSM Test Generator that is run at <strong>EfsmTestGeneratorVhdlTestCase</strong> hangs on b11 VHDL design (or this testcase continues more than <strong>8 hours</strong> - it is very suspicious).</p>
<p>The log fragment is attached below.</p> Retrascope - Bug #5680 (Closed): [efsm][generator][test][fate] DirectedFateGenerator.generateSequ...https://forge.ispras.ru/issues/56802015-03-04T08:01:26ZSergey Smolovsmolov@ispras.ru
<p>The error appears upon b07 design processing.</p>
<p>The stack trace:</p>
<p>[stack]<br />java.lang.NullPointerException<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.DirectedFateGenerator.generateSequence(DirectedFateGenerator.java:226)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.DirectedFateGenerator.getNextSequenceIterator(DirectedFateGenerator.java:163)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGenerator.start(EfsmFateTestGenerator.java:315)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGenerator.start(EfsmFateTestGenerator.java:52)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:200)<br /> at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:106)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:200)<br /> at ru.ispras.retrascope.Retrascope$Run.start(Retrascope.java:116)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:333)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:355)<br /> at ru.ispras.retrascope.util.VhdlUtilTest.runRetrascope(VhdlUtilTest.java:148)<br /> at ru.ispras.retrascope.util.VhdlUtilTest.runVhdl(VhdlUtilTest.java:73)<br /> at ru.ispras.retrascope.util.HdlUtilTest.runVhdl(HdlUtilTest.java:94)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGeneratorVhdlTestCase.generate(EfsmFateTestGeneratorVhdlTestCase.java:32)<br />[/stack]</p>
<p>Full log is attached below.</p> С++TESK Development Environment - Task #3756 (New): Генерация C++ кода для модели сообщенийhttps://forge.ispras.ru/issues/37562012-12-05T15:32:06ZSergey Smolovsmolov@ispras.ru
<p>Небходимо разработать метод генерации C++ кода для модели сообщений.</p>
<p>На вход методу подается несколько объектов класса Adapter. В виде какой структуры данных эти "несколько" будут подаваться - на твое усмотрение. Например, можно взять ту же, что использовалась<br />в инструменте signalsGrouper для хранения набора накликанных "интерфейсов".<br />Т.к. все адаптеры между собой различны и полных совпадений между ними быть не должно, то из самых общих соображений могу предложить использовать java.util.Set.</p>
<p>Суть метода такова: проходим по всем адаптерам и извлекаем из них объекты MessageType и помещаем их в промежуточное хранилище (возможно, тот же Set). При этом необходимо проверять, что в хранилище ещё нет такого же типа сообщений (а при разработке адаптеров для разных интерфейсов вполне реально, что они будут использовать сообщения одного типа)- делать такую проверку лучше всего посредством разработки метода сравнения equals в классе MessageType.</p>
<p><strong>Шаблон для *.h-файла</strong></p>
<pre>
#pragma once
#include <hw/message.hpp>
namespace имя_пространства_имен {
</pre> Про извлечение название пространства имен смотри <a class="issue tracker-2 status-1 priority-4 priority-default" title="Task: namespace name for test system prototypes (New)" href="https://forge.ispras.ru/issues/3755">#3755</a>
<p>Для каждого типа сообщений далее генерируем следующий код:<br /><pre>
MESSAGE(имя_типа_сообщений)
{
public:
имя_типа_сообщений();
virtual ~имя_типа_сообщений();
SUPPORT_CLONE(имя_типа_сообщений);
</pre></p>
<p>Далее для всех полей сообщения данного типа генерируем вызов соответствующего макроса. Макросы бывают следующие:<br />1) Если размер поля больше 64 бит, то нужно использовать<br /> - CPPTESK_DECLARE_FIELD_ARRAY(имя_поля, размер_массива, размер_поля); - если маска не задана<br /> - CPPTESK_DECLARE_MASKED_FIELD_ARRAY(имя_поля, размер_массива, размер_поля, маска_поля); - если маска задана</p>
<p>В силу особенностей реализации параметр размер_поля делаем равным 64, а параметр размер_массива делаем таким, чтобы удовлетворялось следующее неравенство:</p>
<p>capacity <= размер_поля*размер_массива</p>
<p>где capacity - одноименное поле соответствующего экземпляра класса MessageField.</p>
<p>2) Если размер поля меньше, или равен 64 бит, то нужно использовать<br /> - CPPTESK_DECLARE_FIELD(имя_поля, размер_поля);<br /> - CPPTESK_DECLARE_MASKED_FIELD(имя_поля, размер_поля, маска_поля);<br /> - CPPTESK_DECLARE_BIT(имя_поля); - если размер поля равен 1</p>
<pre>
};
}
</pre>
<p>Заголовочный файл называем имя_пространства_имен_msg.h</p>
<p><strong>Шаблон для .cpp файла</strong></p>
<pre>
include <имя_пространства_имен_msg.h>
namespace имя_пространства_имен {
</pre>
<p>Для каждого из типов сообщений генерируем следующий код конструктора и деструктора</p>
<pre>
имя_типа_сообщений::имя_типа_сообщений(void)
{
</pre>
<p>Для всех полей сообщения, у которых incomparable равно false (см. <a class="issue tracker-2 status-5 priority-4 priority-default closed" title="Task: флаг incomparable в полях сообщений (Closed)" href="https://forge.ispras.ru/issues/3754">#3754</a>):<br /><pre>
ADD_FIELD(имя_типа_сообщений::имя_поля);
</pre></p>
<p>Для всех полей сообщения, у которых incomparable равно true (см. <a class="issue tracker-2 status-5 priority-4 priority-default closed" title="Task: флаг incomparable в полях сообщений (Closed)" href="https://forge.ispras.ru/issues/3754">#3754</a>):<br /><pre>
ADD_INCOMPARABLE_FIELD(имя_типа_сообщений::имя_поля);
</pre></p>
<p>Рандомизируем значения полей - только если оно соответствует входному интерфейсу!<br /><pre>
RANDOMIZE_MESSAGE(*this);
}
имя_типа_сообщений::~имя_типа_сообщений(void) {}
}
</pre></p>
<p>Рекомендация - данную задачу стоить решать посредством разработки нескольких относительно простых методов в соответствующих классах, а не одного сложного.</p>