Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692019-02-06T08:47:58ZOpen-Source Projects
Redmine Retrascope RISC-V Benchmark - Bug #9477 (New): an "import "DPI-C" function" construction causes V...https://forge.ispras.ru/issues/94772019-02-06T08:47:58ZSergey Smolovsmolov@ispras.ru
<p>The <strong>ru.ispras.verilog.parser.sample.RocketChipSimJtagVerilogPrinterTestCase</strong> test case runs Verilog Translator on <strong>SimJTAG.v</strong> module, that contains the following code:<br /><pre><code class="text syntaxhl" data-language="text">import "DPI-C" function int jtag_tick
(
output bit jtag_TCK,
output bit jtag_TMS,
output bit jtag_TDI,
output bit jtag_TRSTn,
input bit jtag_TDO
);
module SimJTAG #(
parameter TICK_DELAY = 50
)(
input clock,
input reset,
...
</code></pre></p>
<p>The "import function" construction causes the following error:<br /><pre>
ERROR: ..\retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\SimJTAG.v line 3:0 mismatched input 'import' expecting EOF
ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from line 0:0 mismatched tree node: <mismatched token: [@0,71:76='import',<35>,3:0], resync=import"DPI-C"functionintjtag_tick(outputbitjtag_TCK,outputbitjtag_TMS,outputbitjtag_TDI,outputbitjtag_TRSTn,inputbitjtag_TDO);moduleSimJTAG#(parameterTICK_DELAY=50)(inputclock,inputreset,inputenable,inputinit_done,outputjtag_TCK,outputjtag_TMS,outputjtag_TDI,outputjtag_TRSTn,inputjtag_TDO_data,inputjtag_TDO_driven,output[31:0]exit);reg[31:0]tickCounterReg;wire[31:0]tickCounterNxt;assigntickCounterNxt=(tickCounterReg==0)?TICK_DELAY:(tickCounterReg-1);bitr_reset;wire[31:0]random_bits=$random;wire#0.1__jtag_TDO=jtag_TDO_driven?jtag_TDO_data:random_bits[0];bit__jtag_TCK;bit__jtag_TMS;bit__jtag_TDI;bit__jtag_TRSTn;int__exit;reginit_done_sticky;assign#0.1jtag_TCK=__jtag_TCK;assign#0.1jtag_TMS=__jtag_TMS;assign#0.1jtag_TDI=__jtag_TDI;assign#0.1jtag_TRSTn=__jtag_TRSTn;assign#0.1exit=__exit;always@(posedgeclock)beginr_reset<=reset;if(reset||r_reset)begin__exit=0;tickCounterReg<=TICK_DELAY;init_done_sticky<=1'b0;__jtag_TCK=!__jtag_TCK;endelsebegininit_done_sticky<=init_done|init_done_sticky;if(enable&&init_done_sticky)begintickCounterReg<=tickCounterNxt;if(tickCounterReg==0)begin__exit=jtag_tick(__jtag_TCK,__jtag_TMS,__jtag_TDI,__jtag_TRSTn,__jtag_TDO);endendendendendmodule> expecting AST_ROOT
ERROR: Module 'SimJTAG' has not been found
</pre></p>
<p>The same error appears at the following test cases:<br />ru.ispras.verilog.parser.sample.RocketChipSimDtmVerilogPrinterTestCase</p> Retrascope RISC-V Benchmark - Bug #9475 (Closed): Picorv32Hx8kdemoVerilogPrinterTestCase: ERROR: ...https://forge.ispras.ru/issues/94752019-02-06T08:25:02ZSergey Smolovsmolov@ispras.ru
<p>When running the <strong>ru.ispras.verilog.parser.sample.Picorv32Hx8kdemoVerilogPrinterTestCase</strong>, the following error appears:<br /><pre>
ERROR: line 1:0 no viable alternative at input '('
ERROR: [Internal] null
java.lang.StackOverflowError
at org.antlr.runtime.BaseRecognizer.mismatchIsUnwantedToken(BaseRecognizer.java:127)
at org.antlr.runtime.BaseRecognizer.recoverFromMismatchedToken(BaseRecognizer.java:593)
at org.antlr.runtime.BaseRecognizer.match(BaseRecognizer.java:115)
at ru.ispras.verilog.parser.grammar.VerilogParser.begin_block_statement(VerilogParser.java:13992)
at ru.ispras.verilog.parser.grammar.VerilogParser.statement(VerilogParser.java:15145)
...
</pre></p>
<p>The same error appears for the following test cases: <br />ru.ispras.verilog.parser.sample.Picorv32IcebreakerVerilogPrinterTestCase<br />ru.ispras.verilog.parser.sample.Picorv32PicosocVerilogPrinterTestCase<br />ru.ispras.verilog.parser.sample.Picorv32SimpleuartVerilogPrinterTestCase<br />ru.ispras.verilog.parser.sample.Picorv32SpiflashVerilogPrinterTestCase<br />ru.ispras.verilog.parser.sample.Picorv32SpimemioVerilogPrinterTestCase</p> MicroTESK for MIPS - Bug #9377 (New): 'Failed to construct decoder' warnings in project's build loghttps://forge.ispras.ru/issues/93772018-11-08T11:34:41ZSergey Smolovsmolov@ispras.ru
<pre>
Warning: Failed to construct decoder for mfc0. Unrecognized field: rd.r
Warning: Failed to construct decoder for mfc0. Unrecognized field: rd.s
Warning: Failed to construct decoder for mfc0. Undecoded arguments: [rd]
Warning: Failed to construct decoder for mtc0. Unrecognized field: rd.r
Warning: Failed to construct decoder for mtc0. Unrecognized field: rd.s
Warning: Failed to construct decoder for mtc0. Undecoded arguments: [rd]
Warning: Failed to construct decoder for ext. Unrecognized field: (BVSUB size 00001)
Warning: Failed to construct decoder for ext. Undecoded arguments: [size]
Warning: Failed to construct decoder for ins. Unrecognized field: (BVSUB (BVADD pos size) 00001)
Warning: Failed to construct decoder for ins. Undecoded arguments: [size]
Warning: Failed to construct decoder for dins. Unrecognized field: (BVSUB (BVADD pos size) 00001)
Warning: Failed to construct decoder for dins. Undecoded arguments: [size]
Warning: Failed to construct decoder for dinsm. Unrecognized field: (BVEXTRACT 4 0 (BVSUB (BVADD (BVZEROEXT 1 pos) size) 100001))
Warning: Failed to construct decoder for dinsm. Undecoded arguments: [size]
Warning: Failed to construct decoder for dinsu. Unrecognized field: (BVEXTRACT 4 0 (BVSUB (BVADD pos (BVZEROEXT 1 size)) 100001))
Warning: Failed to construct decoder for dinsu. Unrecognized field: (BVEXTRACT 4 0 (BVSUB pos 100000))
Warning: Failed to construct decoder for dinsu. Undecoded arguments: [pos, size]
</pre> MicroTESK for MIPS - Bug #9376 (New): Warning: Group MIPS64FpuOp contains two items add_fmt and m...https://forge.ispras.ru/issues/93762018-11-08T11:33:31ZSergey Smolovsmolov@ispras.ru
<p>The warning above appears upon project building. To reproduce it, run './gradlew assemble' in Unix-like OS or 'gradlew.bat assemble' in Windows OS.</p> Retrascope - Bug #8681 (Closed): EngineRegistry fails to create toolchain when HashSet\HashMap ar...https://forge.ispras.ru/issues/86812018-01-19T13:30:09ZSergey Smolovsmolov@ispras.ru
<p>The result of EngineRegistry toolchain construction mechanism implicitly depends from order in sets\maps.<br />When HashSet\HashMap classes are used, it can return null, while with LinkedHashSet\LinkedHashMap it is ok.<br />To reproduce the bug, substitute set\map classes from linked to non-linked and run HlddAssertSmvPrinterTestCase on JDK 1.8.</p> Retrascope - Task #5526 (Rejected): Retrascope engines configurationhttps://forge.ispras.ru/issues/55262014-12-24T14:34:26ZSergey Smolovsmolov@ispras.ru
<p>Implement a registration of external engines by addition of their class names to special configuration file.<br />Use classloader to registering them into main class.</p> Retrascope - Bug #5404 (Closed): [verilog][parser][cfg] java.lang.IllegalArgumentException: Unsup...https://forge.ispras.ru/issues/54042014-11-02T12:15:20ZSergey Smolovsmolov@ispras.ru
<p>Running: verilog-parser<br />Options: {v=[D:\Sergey\projects\retrascope.svn\trunk\retrascope\src\test\verilog\ram\ram.v], args=D:\Sergey\projects\retrascope.svn\trunk\retrascope\src\test\verilog\ram\ram.v --target efsm --engine cgaa-efsm-transformer}<br />2014.11.02 14:02:28.860. INFO: Start observing module ram.<br />2014.11.02 14:02:28.860. INFO: add variable clk [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.861. INFO: add variable rst [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.862. INFO: add variable val_rd [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.862. INFO: add variable val_wr [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.863. INFO: add variable addr_in [(BIT_VECTOR 2)] (Data[type=(BIT_VECTOR 2), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.864. INFO: add variable data_in [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.864. INFO: add variable val_out [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.865. INFO: add variable data_out [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.866. INFO: add variable is_ready [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.866. INFO: add variable mem0 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.867. INFO: add variable mem1 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.868. INFO: add variable mem2 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.868. INFO: add variable mem3 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.869. INFO: add variable result [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.870. INFO: add variable state [(BIT_VECTOR 2)] (Data[type=(BIT_VECTOR 2), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.871. INFO: add variable RAM_IDLE [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.875. INFO: add variable RAM_READ [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.876. INFO: add variable RAM_WRITE [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.877. INFO: add variable RAM_RESULT [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />Storing: cfg</p>
<p>Running: cfg-cgaa-transformer<br />Options: {args=D:\Sergey\projects\retrascope.svn\trunk\retrascope\src\test\verilog\ram\ram.v --target efsm --engine cgaa-efsm-transformer, cfg=<cfg>}<br />Storing: cgaa</p>
<p>Running: cgaa-efsm-transformer<br />Options: {cgaa=<cgaa>, args=D:\Sergey\projects\retrascope.svn\trunk\retrascope\src\test\verilog\ram\ram.v --target efsm --engine cgaa-efsm-transformer}<br />2014.11.02 14:02:28.888. ERROR: The exception has been encountered: java.lang.IllegalArgumentException: Unsupported data type: UNKNOWN<br /> at ru.ispras.fortress.solver.engine.z3.SMTStrings.textForData(SMTStrings.java:147)<br /> at ru.ispras.fortress.solver.engine.z3.SMTTextBuilder.onValue(SMTTextBuilder.java:303)<br /> at ru.ispras.fortress.solver.engine.z3.SMTTextBuilder.onValue(SMTTextBuilder.java:282)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitValue(ExprTreeWalker.java:209)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:152)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:192)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:160)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:192)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:160)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:192)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:160)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:127)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:100)<br /> at ru.ispras.fortress.solver.engine.z3.Z3TextSolver.solve(Z3TextSolver.java:120)<br /> at ru.ispras.fortress.expression.ExprUtils.isSAT(ExprUtils.java:350)<br /> at ru.ispras.fortress.expression.ExprUtils.areCompatible(ExprUtils.java:335)<br /> at ru.ispras.retrascope.engine.cgaa.transformer.efsm.CgaaStateExprVisitor.isSAT(CgaaStateExprVisitor.java:203)<br /> at ru.ispras.retrascope.engine.cgaa.transformer.efsm.CgaaStateExprVisitor.checkConditionsIfNot(CgaaStateExprVisitor.java:192)<br /> at ru.ispras.retrascope.engine.cgaa.transformer.efsm.CgaaStateExprVisitor.onBasicBlockBegin(CgaaStateExprVisitor.java:183)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitBasicBlock(CfgWalker.java:255)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:133)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitCase(CfgWalker.java:247)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:139)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitSwitch(CfgWalker.java:229)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:145)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitCase(CfgWalker.java:247)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:139)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitSwitch(CfgWalker.java:229)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:145)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitSource(CfgWalker.java:213)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:151)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitCfg(CfgWalker.java:204)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitProcess(CfgWalker.java:195)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitModule(CfgWalker.java:179)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitCfgModel(CfgWalker.java:166)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.start(CfgWalker.java:86)<br /> at ru.ispras.retrascope.engine.cfg.CfgEngine.start(CfgEngine.java:126)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:191)<br /> at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:106)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:191)<br /> at ru.ispras.retrascope.Retrascope$Run.start(Retrascope.java:117)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:320)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:341)<br /> at ru.ispras.retrascope.util.VerilogUtilTest.runRetrascope(VerilogUtilTest.java:120)<br /> at ru.ispras.retrascope.util.VerilogUtilTest.runVerilog(VerilogUtilTest.java:69)<br /> at ru.ispras.retrascope.util.HdlUtilTest.runVerilog(HdlUtilTest.java:137)<br /> at ru.ispras.retrascope.util.HdlUtilTest.runHdl(HdlUtilTest.java:51)</p> Java SoftFloat - Bug #5385 (Closed): Странная структура директорий проектаhttps://forge.ispras.ru/issues/53852014-10-24T07:55:28ZSergey Smolovsmolov@ispras.ru
<p>В репозитории проекта замечена папка jsoftfloat, находящаяся на том же уровне вложенности, что и традиционные branches, tags, trunk.<br />Это запланированное явление, или результат ошибки?</p> Retrascope - Task #5258 (Closed): [basis] Обработка циклических зависимостей разных Enginehttps://forge.ispras.ru/issues/52582014-09-09T05:58:43ZSergey Smolovsmolov@ispras.ru
<p>В Retrascope стали появляться Engine, имеющие циклические зависимости по Entity.<br />Это означает, что можно найти пару Engine, таких, что output type одного является input type для другого и обратно.</p>
<p>Запуск инструмента, в котором зарегистрирована хотя бы одна пара таких Engine, приводит к ошибке:</p>
<p><code>java.lang.IllegalArgumentException: Addition of engine 'xml-test-parser' causes a cycle dependency</code></p>
<p>Необходимо корректно разрешать такие зависимости при построении последовательности вызовов Engine.<br />Возможный вариант такой: строить кратчайший путь между двумя вершинами в графе зависимостей Engine (проходить циклы не более чем один раз).</p> Retrascope - Task #5249 (Closed): [basis] Настройка Retrascope для работы с SMT-решателямиhttps://forge.ispras.ru/issues/52492014-09-04T10:32:33ZSergey Smolovsmolov@ispras.ru
<p>Для корректного взаимодействия с SMT-решателями через библиотеку Fortress необходимо в инструменте Retrascope определять путь к исполняемому файлу (Environment.setSolverPath(String path)).</p>
<p>Такую настройку нужно однократно проделывать при каждом запуске Retrascope.</p> Retrascope - Task #5247 (Closed): [basis] Набор идентификаторов Engine как опция командной строки...https://forge.ispras.ru/issues/52472014-09-03T05:37:09ZSergey Smolovsmolov@ispras.ru
<p>Реализовать опцию командной строки для исполняемого модуля Retrascope.<br />Опция содержит набор идентификаторов Engine. <br />На основе указанного набора значений исполняемый модуль должен построить последовательность вызовов Engine и выполнить их в указанном порядке, либо сообщить, что такой последовательности нет.<br />Необходимо сообщать о некорректных идентификаторах Engine.</p> Retrascope - Bug #5096 (Closed): [basis] FileCreator: "Can't create file" errorhttps://forge.ispras.ru/issues/50962014-07-17T13:17:22ZSergey Smolovsmolov@ispras.ru
<p>Если файл уже был когда-то создан, то попытка пересоздать его с помощью метода newFile класса FileCreator приводит к ошибке "Can't create file".</p> Retrascope IDE - Bug #4991 (Closed): Не передается путь к HDL-описаниюhttps://forge.ispras.ru/issues/49912014-06-16T10:43:45ZSergey Smolovsmolov@ispras.ru
<p>Если во вкладке Input Files в меню Retrascope Tool Launcher выбрать *.vhd-файл, то инструменту Retrascope в качестве аргумента передается только имя файла без указания пути, что приводит к ошибке "File not found" VHDL-парсера.</p> Fortress - Task #4702 (Closed): [expression] Реализовать операцию BVBIThttps://forge.ispras.ru/issues/47022014-03-01T09:38:03ZSergey Smolovsmolov@ispras.ru
<p>Необходимо реализовать операцию BVBIT. <br />Аргументы операции: битовый вектор bv, целое неотрицательное число n.<br />Операция возвращает значение bv[n], т.е. n-ный бит вектора.<br />Если n >= bv.size, то бросаем Exception.</p> С++TESK Development Environment - Task #2224 (Closed): Добавить пункт со сведениями о плагинеhttps://forge.ispras.ru/issues/22242012-01-17T10:24:56ZSergey Smolovsmolov@ispras.ru
<p>Добавить в меню "Help"->"About Eclipse SDK" пункт со сведениями о плагине. Можно сделать по аналогии с плагинами для CTesK, JavaTesK.</p>