Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692021-12-02T12:12:23ZOpen-Source Projects
Redmine Java SoftFloat - Bug #11042 (New): Javadoc warningshttps://forge.ispras.ru/issues/110422021-12-02T12:12:23ZSergey Smolovsmolov@ispras.ru
<p>Warnings upon project build:</p>
<pre>
> Task :javadoc
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/jni/Cfloat.java:17: warning - invalid usage of tag &
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/jni/Conversion.java:41: warning - Tag @see: reference not found: #f32_to_i32(int)
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:622: warning - @param argument "zExpPtr" is not a parameter name.
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:623: warning - @param argument "zSigPtr" is not a parameter name.
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:4899: warning - invalid usage of tag <
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:4899: warning - invalid usage of tag >
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:4926: warning - invalid usage of tag <
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:4926: warning - invalid usage of tag >
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:4975: warning - invalid usage of tag <
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:4975: warning - invalid usage of tag >
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:5005: warning - invalid usage of tag <
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:5005: warning - invalid usage of tag >
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:6348: warning - invalid usage of tag <
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:6348: warning - invalid usage of tag >
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:6375: warning - invalid usage of tag <
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:6375: warning - invalid usage of tag >
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:6424: warning - invalid usage of tag <
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:6424: warning - invalid usage of tag >
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:6454: warning - invalid usage of tag <
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloat.java:6454: warning - invalid usage of tag >
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/JSoftFloatUtils.java:122: warning - @param argument "zPtr" is not a parameter name.
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/Utils.java:37: warning - invalid usage of tag <
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/Utils.java:37: warning - invalid usage of tag >
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/Utils.java:51: warning - invalid usage of tag <
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/Utils.java:51: warning - invalid usage of tag >
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/jni/Cfloat.java:17: warning - invalid usage of tag &
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/jni/Cfloat.java:17: warning - invalid usage of tag &
/home/ssedai/projects/jsoftfloat/src/main/java/ru/ispras/softfloat/jni/Cfloat.java:17: warning - invalid usage of tag &
28 warnings
</pre> Verilog Translator - Bug #10513 (New): macOS related line endings at Verilog moduleshttps://forge.ispras.ru/issues/105132020-10-04T06:54:18ZSergey Smolovsmolov@ispras.ru
<p>Verilog Translator does not support macOS related line endings ('\r') at Verilog modules. Is it ok for the tool?</p> Verilog Translator - Bug #10512 (New): ADDA162H90A_atop.v line 120:47 mismatched input ':' expect...https://forge.ispras.ru/issues/105122020-10-02T08:46:35ZSergey Smolovsmolov@ispras.ru
<pre>
RROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\faraday\rtl\DSP\hdl\CODEC\FXADDA162H90A\ADDA162H90A_atop.v line 120:47 mismatched input ':' expecting RPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\faraday\rtl\DSP\hdl\CODEC\FXADDA162H90A\ADDA162H90A_atop.v line 157:47 mismatched input ':' expecting RPAREN
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 117:36 mismatched tree node: <mismatched token: [@2436,3042:3042=':',<19>,120:47], resync=$width(posedgedac_phase_check,400.00:500.00:900.00,0,> expecting <UP>
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 117:36 mismatched tree node: AST_ATTRIBUTES expecting <UP>
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 117:36 mismatched tree node: <unexpected: [@2444,3089:3089=')',<276>,120:94], resync=n_flag_dac_phase_overlape> expecting <UP>
</pre> Verilog Translator - Bug #10510 (New): ERROR: [Internal] Bit vector sizes do not match: 32 != 2.https://forge.ispras.ru/issues/105102020-10-01T15:35:04ZSergey Smolovsmolov@ispras.ru
<pre>
java.lang.IllegalArgumentException: Bit vector sizes do not match: 32 != 2.
at ru.ispras.fortress.data.types.bitvector.BitVectorMath.checkEqualSize(BitVectorMath.java:1255)
at ru.ispras.fortress.data.types.bitvector.BitVectorMath.transform(BitVectorMath.java:1231)
at ru.ispras.fortress.data.types.bitvector.BitVectorMath.add(BitVectorMath.java:869)
at ru.ispras.fortress.data.types.bitvector.BitVectorMath.sub(BitVectorMath.java:888)
at ru.ispras.verilog.parser.interpreter.VerilogOperations$10.calculate(VerilogOperations.java:222)
at ru.ispras.fortress.calculator.OperationGroup.calculate(OperationGroup.java:141)
at ru.ispras.fortress.transformer.Reducer$OperationRule.apply(Reducer.java:147)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:173)
at ru.ispras.fortress.transformer.NodeTransformer.updateNode(NodeTransformer.java:183)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:231)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Reducer.reduce(Reducer.java:183)
at ru.ispras.verilog.parser.interpreter.VerilogCalculator.evaluate(VerilogCalculator.java:67)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.evaluate(VerilogElaborator.java:1161)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.defineParameter(VerilogElaborator.java:1073)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:526)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariablesAndBindings(VerilogElaborator.java:910)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariablesAndBindings(VerilogElaborator.java:883)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:330)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:231)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:212)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogIwlsTestSuite.runTest_risc_defgh(VerilogIwlsTestSuite.java:1692)
</pre> Verilog Translator - Bug #10509 (New): ERROR: [Internal] 0 must be > 0https://forge.ispras.ru/issues/105092020-10-01T15:15:47ZSergey Smolovsmolov@ispras.ru
<pre>
ERROR: [Internal] 0 must be > 0
java.lang.IllegalArgumentException: 0 must be > 0
at ru.ispras.fortress.util.InvariantChecks.checkGreaterThanZero(InvariantChecks.java:159)
at ru.ispras.fortress.data.types.bitvector.BitVector.newEmpty(BitVector.java:381)
at ru.ispras.verilog.parser.model.basis.VerilogLiteral.<init>(VerilogLiteral.java:188)
at ru.ispras.verilog.parser.model.basis.VerilogLiteral.parseString(VerilogLiteral.java:55)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_string(VerilogTreeBuilder.java:7916)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_primary(VerilogTreeBuilder.java:6628)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_operation(VerilogTreeBuilder.java:6502)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_expression(VerilogTreeBuilder.java:6356)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_task_statement(VerilogTreeBuilder.java:4716)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4393)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:5465)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4473)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_process(VerilogTreeBuilder.java:3514)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_item(VerilogTreeBuilder.java:1214)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_module(VerilogTreeBuilder.java:918)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_unit(VerilogTreeBuilder.java:765)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:713)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:663)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:455)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:460)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:486)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:490)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:206)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogIwlsTestSuite.runTest_usbf_top(VerilogIwlsTestSuite.java:4417)
</pre> Verilog Translator - Bug #10508 (New): ERROR: [Internal] Java heap spacehttps://forge.ispras.ru/issues/105082020-10-01T11:33:03ZSergey Smolovsmolov@ispras.ru
<p>The following test cases fall with "ERROR: [Internal] Java heap space":</p>
<p><strong>ru.ispras.verilog.parser.VerilogIwlsTestSuite#runTest_iscas_s35932<br />ru.ispras.verilog.parser.VerilogIwlsTestSuite#runTest_iscas_s38417<br />ru.ispras.verilog.parser.VerilogIwlsTestSuite#runTest_iscas_s15850</strong></p> Verilog Translator - Bug #10505 (New): ERROR: [Internal] 11 must be within range [0, 1)https://forge.ispras.ru/issues/105052020-09-30T10:51:18ZSergey Smolovsmolov@ispras.ru
<pre>
java.lang.IndexOutOfBoundsException: 11 must be within range [0, 1)
at ru.ispras.fortress.util.InvariantChecks.checkBounds(InvariantChecks.java:190)
at ru.ispras.fortress.data.types.bitvector.BitVector.field(BitVector.java:309)
at ru.ispras.verilog.parser.interpreter.VerilogOperations$34.calculate(VerilogOperations.java:745)
at ru.ispras.fortress.calculator.OperationGroup.calculate(OperationGroup.java:141)
at ru.ispras.fortress.transformer.Reducer$OperationRule.apply(Reducer.java:147)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:173)
at ru.ispras.fortress.transformer.NodeTransformer.updateNode(NodeTransformer.java:183)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:231)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Reducer.reduce(Reducer.java:183)
at ru.ispras.fortress.transformer.Reducer.reduce(Reducer.java:248)
at ru.ispras.verilog.parser.interpreter.VerilogCalculator.reduce(VerilogCalculator.java:50)
at ru.ispras.verilog.parser.transformer.VerilogTransformerOperation.transform(VerilogTransformerOperation.java:66)
at ru.ispras.verilog.parser.transformer.VerilogTransformerComposite.transform(VerilogTransformerComposite.java:57)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:214)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:226)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:245)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.onAssignStatementBegin(VerilogTransformer.java:84)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(VerilogNodeVisitor.java:285)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:770)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:81)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.run(VerilogTransformer.java:55)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiate(VerilogInstantiator.java:198)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateProcess(VerilogInstantiator.java:144)
at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:212)
at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:199)
at ru.ispras.verilog.parser.backends.design.typecast.VerilogTypeCaster.start(VerilogTypeCaster.java:43)
at ru.ispras.verilog.parser.VerilogDesignBackends.start(VerilogDesignBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:219)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogIwlsTestSuite.runTest_opencores_pci_target_unit(VerilogIwlsTestSuite.java:3941)
</pre> Verilog Translator - Bug #10502 (New): subbytes.v line 76:13 no viable alternative at input '['https://forge.ispras.ru/issues/105022020-09-28T08:20:09ZSergey Smolovsmolov@ispras.ru
<p>When processing the hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v module, the following errors appear:<br /><pre>
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 76:13 no viable alternative at input '['
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 77:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 78:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 79:21 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 80:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 81:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 82:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 83:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 84:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 85:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 86:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 87:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 88:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 89:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 90:19 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 91:18 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 95:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 96:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 97:21 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 98:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 99:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 100:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 101:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 102:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 103:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 104:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 105:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 106:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 107:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 108:19 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 109:18 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 113:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 114:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 115:21 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 116:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 117:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 118:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 119:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 120:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 121:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 122:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 123:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 124:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 125:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 126:19 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 127:18 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 1:0 extraneous input '\' expecting KW_END
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 1:0 extraneous input '\' expecting KW_END
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 1:0 mismatched input '\' expecting KW_END
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 245:17 mismatched input '=' expecting COLON
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 245:33 missing COLON at ';'
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 246:14 mismatched input '=' expecting COLON
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 246:25 missing COLON at ';'
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 247:2 extraneous input 'end' expecting KW_ENDCASE
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 73:0 mismatched tree node: <unexpected: [@6101,3705:3705='[',<214>,76:13], resync=data_reg_128> expecting <UP>
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 76:40 mismatched tree node: AST_STRENGTH expecting <UP>
</pre></p>
<p>The problem is connected with the following macro in Verilog:<br /><pre><code class="verilog syntaxhl" data-language="verilog"><span class="cp">`define</span> <span class="n">assign_array_to_128</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">127</span><span class="o">:</span><span class="mi">120</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">0</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">119</span><span class="o">:</span><span class="mi">112</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">1</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">111</span><span class="o">:</span><span class="mi">104</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">2</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">103</span><span class="o">:</span><span class="mi">96</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">3</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">95</span><span class="o">:</span><span class="mi">88</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">4</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">87</span><span class="o">:</span><span class="mi">80</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">5</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">79</span><span class="o">:</span><span class="mi">72</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">6</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">71</span><span class="o">:</span><span class="mi">64</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">7</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">63</span><span class="o">:</span><span class="mi">56</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">8</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">55</span><span class="o">:</span><span class="mi">48</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">9</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">47</span><span class="o">:</span><span class="mi">40</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">10</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">39</span><span class="o">:</span><span class="mi">32</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">11</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">31</span><span class="o">:</span><span class="mi">24</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">12</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">23</span><span class="o">:</span><span class="mi">16</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">13</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">15</span><span class="o">:</span><span class="mi">8</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">14</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">7</span><span class="o">:</span><span class="mi">0</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">15</span><span class="p">];</span>
</code></pre></p> Verilog Translator - Bug #10215 (New): ERROR: Starting points limit has been exhausted: 2255https://forge.ispras.ru/issues/102152020-04-06T09:39:48ZSergey Smolovsmolov@ispras.ru
<pre>
ERROR: Starting points limit has been exhausted: 2255
ERROR: [Internal] null
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkFalse(InvariantChecks.java:68)
at ru.ispras.verilog.parser.VerilogTranslator.exit(VerilogTranslator.java:126)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:223)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:212)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogQuipTestSuite.runTest_nut_000(VerilogQuipTestSuite.java:301)
</pre> MicroTESK - Bug #10069 (New): cpu.nml Error: Internal error: context [/Isa] 1:8 attribute file is...https://forge.ispras.ru/issues/100692020-01-24T12:11:55ZSergey Smolovsmolov@ispras.ru
<p>Upon building, the following error appears in Gradle log:<br /><pre>
> Task :translateCpu
Translating: src/main/arch/demo/cpu/model/cpu.nml
Model name: cpu
Included: src/main/arch/demo/cpu/model/cpu.nml
Error: Internal error: context [/Isa] 1:8 attribute file isn't defined
</pre></p> Verilog Translator - Bug #9993 (New): if two modules are passed to the tool and one includes anot...https://forge.ispras.ru/issues/99932019-12-18T12:43:15ZSergey Smolovsmolov@ispras.ru
<p>Suppose there are two files with Verilog modules: <em>a.v</em> and <em>b.v</em> (<em>a.v</em> contains "a" module, b.v contains "b" module). Module "a" includes module "b".</p>
<p>When the following args are used for the tool:<br /><pre>
a.v b.v --include-path /path/to/b/file --module-name a
</pre><br />the tool hangs. These arguments seem to be strange, because "b" module appears two times in the command line.<br />More adequate diagnostics should be shown here, and, of course, no freezes.</p> Verilog Translator - Bug #9902 (New): java.lang.IllegalArgumentException: Descriptor for '<var na...https://forge.ispras.ru/issues/99022019-11-01T16:20:57ZSergey Smolovsmolov@ispras.ru
<p>When running the tool on the <a href="https://github.com/ispras/hdl-benchmarks/blob/master/hdl/iwls05/faraday/rtl/DMA/hdl/dma_chsel.v" class="external">dma_chsel.v</a> and <a href="https://github.com/ispras/hdl-benchmarks/blob/master/hdl/iwls05/faraday/rtl/DMA/hdl/dma_rrarb.v" class="external">dma_rrarb.v</a> modules the following error log appears:<br /><pre>
ru.ispras.verilog.parser.VerilogIwlsTestCase > runTest_dma_chsel STANDARD_ERROR
java.lang.IllegalArgumentException: Descriptor for 'dma_chsel.arb_chcsr_reg' has not been found: {dma_chsel.HCLK=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.HRSTn=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.dma_req=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.dma_ack=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.dma_tc=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.csr=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.sync=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.de_err_notify=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c0csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c0abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c0llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c1csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c1abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c1llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c2csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c2abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c2llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c3csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c3abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c3llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c4csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c4abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c4llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c5csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c5abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c5llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c6csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c6abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c6llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c7csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c7abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c7llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.arb_ch_sel=(BIT_VECTOR 3):(SHIFT 0)}
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:109)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute$1.apply(VerilogTransformerVariableSubstitute.java:121)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:169)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:229)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:213)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute.shiftRanges(VerilogTransformerVariableSubstitute.java:95)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute.transform(VerilogTransformerVariableSubstitute.java:142)
at ru.ispras.verilog.parser.transformer.VerilogTransformerComposite.transform(VerilogTransformerComposite.java:57)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:177)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:189)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.onDeclarationBegin(VerilogTransformer.java:67)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$13.onBegin(VerilogNodeVisitor.java:385)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:81)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.run(VerilogTransformer.java:52)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiate(VerilogInstantiator.java:145)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateDescriptor(VerilogInstantiator.java:124)
at ru.ispras.verilog.parser.elaborator.VerilogDesign$Builder.build(VerilogDesign.java:102)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:246)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:187)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:111)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:71)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:45)
at ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_dma_chsel(VerilogIwlsTestCase.java:51)
</pre></p>
<p>To reproduce the bug, run <strong>ru.ispras.verilog.parser.VerilogIwlsTestCase#runTest_dma_chsel</strong> test from <em>Retrascope Test Suite</em> project.</p> Retrascope RISC-V Benchmark - Bug #9477 (New): an "import "DPI-C" function" construction causes V...https://forge.ispras.ru/issues/94772019-02-06T08:47:58ZSergey Smolovsmolov@ispras.ru
<p>The <strong>ru.ispras.verilog.parser.sample.RocketChipSimJtagVerilogPrinterTestCase</strong> test case runs Verilog Translator on <strong>SimJTAG.v</strong> module, that contains the following code:<br /><pre><code class="text syntaxhl" data-language="text">import "DPI-C" function int jtag_tick
(
output bit jtag_TCK,
output bit jtag_TMS,
output bit jtag_TDI,
output bit jtag_TRSTn,
input bit jtag_TDO
);
module SimJTAG #(
parameter TICK_DELAY = 50
)(
input clock,
input reset,
...
</code></pre></p>
<p>The "import function" construction causes the following error:<br /><pre>
ERROR: ..\retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\SimJTAG.v line 3:0 mismatched input 'import' expecting EOF
ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from line 0:0 mismatched tree node: <mismatched token: [@0,71:76='import',<35>,3:0], resync=import"DPI-C"functionintjtag_tick(outputbitjtag_TCK,outputbitjtag_TMS,outputbitjtag_TDI,outputbitjtag_TRSTn,inputbitjtag_TDO);moduleSimJTAG#(parameterTICK_DELAY=50)(inputclock,inputreset,inputenable,inputinit_done,outputjtag_TCK,outputjtag_TMS,outputjtag_TDI,outputjtag_TRSTn,inputjtag_TDO_data,inputjtag_TDO_driven,output[31:0]exit);reg[31:0]tickCounterReg;wire[31:0]tickCounterNxt;assigntickCounterNxt=(tickCounterReg==0)?TICK_DELAY:(tickCounterReg-1);bitr_reset;wire[31:0]random_bits=$random;wire#0.1__jtag_TDO=jtag_TDO_driven?jtag_TDO_data:random_bits[0];bit__jtag_TCK;bit__jtag_TMS;bit__jtag_TDI;bit__jtag_TRSTn;int__exit;reginit_done_sticky;assign#0.1jtag_TCK=__jtag_TCK;assign#0.1jtag_TMS=__jtag_TMS;assign#0.1jtag_TDI=__jtag_TDI;assign#0.1jtag_TRSTn=__jtag_TRSTn;assign#0.1exit=__exit;always@(posedgeclock)beginr_reset<=reset;if(reset||r_reset)begin__exit=0;tickCounterReg<=TICK_DELAY;init_done_sticky<=1'b0;__jtag_TCK=!__jtag_TCK;endelsebegininit_done_sticky<=init_done|init_done_sticky;if(enable&&init_done_sticky)begintickCounterReg<=tickCounterNxt;if(tickCounterReg==0)begin__exit=jtag_tick(__jtag_TCK,__jtag_TMS,__jtag_TDI,__jtag_TRSTn,__jtag_TDO);endendendendendmodule> expecting AST_ROOT
ERROR: Module 'SimJTAG' has not been found
</pre></p>
<p>The same error appears at the following test cases:<br />ru.ispras.verilog.parser.sample.RocketChipSimDtmVerilogPrinterTestCase</p> MicroTESK for MIPS - Bug #9377 (New): 'Failed to construct decoder' warnings in project's build loghttps://forge.ispras.ru/issues/93772018-11-08T11:34:41ZSergey Smolovsmolov@ispras.ru
<pre>
Warning: Failed to construct decoder for mfc0. Unrecognized field: rd.r
Warning: Failed to construct decoder for mfc0. Unrecognized field: rd.s
Warning: Failed to construct decoder for mfc0. Undecoded arguments: [rd]
Warning: Failed to construct decoder for mtc0. Unrecognized field: rd.r
Warning: Failed to construct decoder for mtc0. Unrecognized field: rd.s
Warning: Failed to construct decoder for mtc0. Undecoded arguments: [rd]
Warning: Failed to construct decoder for ext. Unrecognized field: (BVSUB size 00001)
Warning: Failed to construct decoder for ext. Undecoded arguments: [size]
Warning: Failed to construct decoder for ins. Unrecognized field: (BVSUB (BVADD pos size) 00001)
Warning: Failed to construct decoder for ins. Undecoded arguments: [size]
Warning: Failed to construct decoder for dins. Unrecognized field: (BVSUB (BVADD pos size) 00001)
Warning: Failed to construct decoder for dins. Undecoded arguments: [size]
Warning: Failed to construct decoder for dinsm. Unrecognized field: (BVEXTRACT 4 0 (BVSUB (BVADD (BVZEROEXT 1 pos) size) 100001))
Warning: Failed to construct decoder for dinsm. Undecoded arguments: [size]
Warning: Failed to construct decoder for dinsu. Unrecognized field: (BVEXTRACT 4 0 (BVSUB (BVADD pos (BVZEROEXT 1 size)) 100001))
Warning: Failed to construct decoder for dinsu. Unrecognized field: (BVEXTRACT 4 0 (BVSUB pos 100000))
Warning: Failed to construct decoder for dinsu. Undecoded arguments: [pos, size]
</pre> MicroTESK for MIPS - Bug #9376 (New): Warning: Group MIPS64FpuOp contains two items add_fmt and m...https://forge.ispras.ru/issues/93762018-11-08T11:33:31ZSergey Smolovsmolov@ispras.ru
<p>The warning above appears upon project building. To reproduce it, run './gradlew assemble' in Unix-like OS or 'gradlew.bat assemble' in Windows OS.</p>