Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692020-02-13T14:42:42ZOpen-Source Projects
Redmine MicroTESK - Bug #10121 (Open): technical output printing at 'compile.sh' script running with '--h...https://forge.ispras.ru/issues/101212020-02-13T14:42:42ZSergey Smolovsmolov@ispras.ru
<pre>
$ ./bin/compile.sh --help
Buildfile: /home/ssedai/Downloads/microtesk-2.5.1-beta-200127/bin/build.xml
clean:
[delete] Deleting directory /home/ssedai/Downloads/microtesk-2.5.1-beta-200127/gen
BUILD SUCCESSFUL
Total time: 0 seconds
usage: [options] Files to be processed
-ad,--arch-dirs <arg> Home directories for tested architectures [works with -g],
default=""
-ae,--asserts-enabled Enables assertion checks during simulation [works with -g],
default=false
-af,--align-format <arg> Alignment directive format [works with -g], default=".align %d"
-aff,--align-format2 <arg> Alignment directive format [works with -g], default=".align %d,
0x%02x"
-baf,--byte-align-format <arg> Byte alignment directive format [works with -g], default=".balign
%d"
-baff,--byte-align-format2 <arg> Byte alignment directive format [works with -g], default=".balign
%d, 0x%02x"
-bel,--branch-exec-limit <arg> Maximum execution count for an instruction [works with -g],
default=100
-bfbe,--binary-file-big-endian Use big endian for binary files, default=false
-bfe,--binary-file-extension <arg> Binary file extension [works with -g], default="bin"
-btn,--base-template-name <arg> Name of test template base class [works with -gt], default=""
-btp,--base-template-path <arg> Path to test template base class file [works with -gt],
default=""
-cd,--comments-debug Enables generation of detailed comments, depends on
--comments-enabled [works with -g], default=false
-ce,--comments-enabled Enables generation of comments [works with -g], default=false
-cfe,--code-file-extension <arg> Output file extension [works with -g], default="asm"
-cfp,--code-file-prefix <arg> Output file prefix [works with -g], default="test"
-cl,--coverage-log Enables coverage trace generation [works with -g], default=false
-ct,--comment-token <arg> Single-line comment text [works with -g], default="//"
-cte,--comment-token-end <arg> Text that ends a multiline comment [works with -g], default="*/"
-cts,--comment-token-start <arg> Text that starts a multiline comment [works with -g],
default="/*"
-d,--disassemble Disassembles binary files, default=false
-dfe,--data-file-extension <arg> Data file extension [works with -g], default="asm"
-dfp,--data-file-prefix <arg> Data file prefix [works with -g], default="data"
-dp,--debug-print Enables printing detailed debug messages [works with -g],
default=false
-dsk,--data-section-keyword <arg> Data section directive [works with -g], default=".data"
-dtd,--default-test-data Enables generation of default test data [works with -g],
default=false
-ed,--extension-dir <arg> Directory that stores user-defined Java code [works with -t],
default=""
-efp,--except-file-prefix <arg> Exception handler file prefix [works with -g],
default="test_except"
-fde,--fetch-decode-enabled Enables allocation, fetching and decoding of instructions [works
with -g], default=false
-g,--generate Generates test programs, default=false
-gb,--generate-binary Enables generating binary files (limited functionality for
debugging) [works with -g], default=false
-gf,--global-format <arg> Global directive format [works with -g], default=".globl %s"
-gt,--generate-template Generates test templates, default=false
-h,--help Shows help message, default=false
-i,--include <arg> Directory that stores include files [works with -t], default=""
-ii,--ignored-instructions <arg> Instructions to be ignored [works with -gt], default=""
-in,--instance-number <arg> Number of processing element instances [works with -g], default=1
-it,--indent-token <arg> Indentation text [works with -g], default="
"
-jtpm,--jruby-thread-pool-max <arg>JRuby: maximum number of threads to allow in pool [works with
-g], default=2147483647
-mn,--model-name <arg> Name of the constructed microprocessor model [works with -t],
default=""
-ns,--no-simulation Disables simulation of generated code [works with -g],
default=false
-od,--output-dir <arg> Directory to place generated files, default="./output"
-of,--origin-format <arg> Origin directive format [works with -g], default=".org 0x%x"
-off,--option-format <arg> Option directive format [works with -g], default=".option %s"
-paf,--power2-align-format <arg> Power of 2 alignment directive format [works with -g],
default=".p2align %d"
-paff,--power2-align-format2 <arg> Power of 2 alignment directive format [works with -g],
default=".p2align %d, 0x%02x"
-pll,--program-length-limit <arg> Maximum program length [works with -g], default=1000
-rd,--reserve-dependencies Enables automated reservation of registers that have dependencies
[works with -g], default=false
-re,--reserve-explicit Enables marking all explicitly specified registers as used [works
with -g], default=false
-ri,--rev-id <arg> Identifier of revision to be used, default=""
-rl,--rate-limit <arg> Minimum generation rate [works with -g], default=0
-rs,--random-seed <arg> Seed for randomizer [works with -g], default=0
-s,--solver <arg> Constraint solver engine to be used, default="cvc4"
-sc,--self-checks Enables inserting self-checks into test programs [works with -g],
default=false
-sd,--solver-debug Enables debug mode for SMT solvers [works with -g], default=false
-se,--symbolic-execute Performs symbolic execution, default=false
-st,--separator-token <arg> Text used to create separators [works with -g], default="="
-t,--translate Translates formal specifications, default=false
-tl,--tracer-log Enables generation of Tracer logs for simulation [works with -g],
default=false
-tll,--trace-length-limit <arg> Maximum execution trace length [works with -g], default=1000
-ts,--time-statistics Enables printing time statistics [works with -g], default=false
-tsk,--text-section-keyword <arg> Text section directive [works with -g], default=".text"
-tt,--transform-trace Transforms traces into templates, default=false
-v,--verbose Enables printing diagnostic messages, default=false
-wf,--weak-format <arg> Weak directive format [works with -g], default=".weak %s"
Buildfile: /home/ssedai/Downloads/microtesk-2.5.1-beta-200127/bin/build.xml
build:
[mkdir] Created dir: /home/ssedai/Downloads/microtesk-2.5.1-beta-200127/gen/bin
BUILD FAILED
/home/ssedai/Downloads/microtesk-2.5.1-beta-200127/bin/build.xml:47: srcdir "/home/ssedai/Downloads/microtesk-2.5.1-beta-200127/gen/src/java" does not exist!
</pre> MicroTESK - Bug #10102 (Closed): incorrect ld scripts for x86 test programshttps://forge.ispras.ru/issues/101022020-02-06T10:22:06ZSergey Smolovsmolov@ispras.ru
<p>For x86 test programs emulation on QEMU4V, the following approach can be used. Test program should be compiled as <em>bootable drive</em> and run on QEMU4V ("-hda" option). The following linker script should be generated:<br /><pre>
SECTIONS
{
/* The BIOS loads the code from the disk to this location.
* We must tell that to the linker so that it can properly
* calculate the addresses of symbols we might jump to.
*/
. = 0x7c00;
.text :
{
__start = .;
*(.text)
/* Place the magic boot bytes at the end of the first 512 sector of the disk. */
. = 0x1FE;
SHORT(0xAA55)
}
}
</pre></p>
<p>Now ld scripts look as follows:<br /><pre>
ENTRY(_start)
SECTIONS
{
. = 0x7C00;
.text : { *(".text")}
. = 0x8000;
.data : { *(".data")}
.bss : { *(".bss COMMON")}
. = ALIGN(8);
. = . + 0x10000;
stack_top = .;
}
</pre></p> MicroTESK - Bug #10094 (Closed): strange common code at LinkerScript.stghttps://forge.ispras.ru/issues/100942020-02-04T14:06:08ZSergey Smolovsmolov@ispras.ru
<p>The StringTemplate description for ld scripts looks as follows (<a class="external" href="https://forge.ispras.ru/projects/microtesk/repository/microtesk/revisions/master/entry/src/main/resources/core/stg/LinkerScript.stg">https://forge.ispras.ru/projects/microtesk/repository/microtesk/revisions/master/entry/src/main/resources/core/stg/LinkerScript.stg</a>):<br /><pre>
linker_script(
time,
section_ids,
section_vas,
section_flags
) ::= <<
<linker_script_header(time)>
ENTRY(_start)
SECTIONS
{
<section_ids, section_vas, section_flags : {id, va, fl | <section(id, va, fl)>}; separator="\n">
. = ALIGN(8);
. = . + 0x10000;
stack_top = .;
}
>>
section(id, va, common) ::= <<
<if(va)>. = <va>;<\n><endif><id> : { *("<id><if(common)> COMMON<endif>")}
>>
</pre></p>
<p>The following part is common for all linker scripts that are generated by the MicroTESK:<br /><pre>
. = ALIGN(8);
. = . + 0x10000;
stack_top = .;
</pre></p>
<p>It seems suspicious that this code is repeated for all ISAs.</p> MicroTESK - Bug #10069 (New): cpu.nml Error: Internal error: context [/Isa] 1:8 attribute file is...https://forge.ispras.ru/issues/100692020-01-24T12:11:55ZSergey Smolovsmolov@ispras.ru
<p>Upon building, the following error appears in Gradle log:<br /><pre>
> Task :translateCpu
Translating: src/main/arch/demo/cpu/model/cpu.nml
Model name: cpu
Included: src/main/arch/demo/cpu/model/cpu.nml
Error: Internal error: context [/Isa] 1:8 attribute file isn't defined
</pre></p> Retrascope RISC-V Benchmark - Bug #9477 (New): an "import "DPI-C" function" construction causes V...https://forge.ispras.ru/issues/94772019-02-06T08:47:58ZSergey Smolovsmolov@ispras.ru
<p>The <strong>ru.ispras.verilog.parser.sample.RocketChipSimJtagVerilogPrinterTestCase</strong> test case runs Verilog Translator on <strong>SimJTAG.v</strong> module, that contains the following code:<br /><pre><code class="text syntaxhl" data-language="text">import "DPI-C" function int jtag_tick
(
output bit jtag_TCK,
output bit jtag_TMS,
output bit jtag_TDI,
output bit jtag_TRSTn,
input bit jtag_TDO
);
module SimJTAG #(
parameter TICK_DELAY = 50
)(
input clock,
input reset,
...
</code></pre></p>
<p>The "import function" construction causes the following error:<br /><pre>
ERROR: ..\retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\SimJTAG.v line 3:0 mismatched input 'import' expecting EOF
ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from line 0:0 mismatched tree node: <mismatched token: [@0,71:76='import',<35>,3:0], resync=import"DPI-C"functionintjtag_tick(outputbitjtag_TCK,outputbitjtag_TMS,outputbitjtag_TDI,outputbitjtag_TRSTn,inputbitjtag_TDO);moduleSimJTAG#(parameterTICK_DELAY=50)(inputclock,inputreset,inputenable,inputinit_done,outputjtag_TCK,outputjtag_TMS,outputjtag_TDI,outputjtag_TRSTn,inputjtag_TDO_data,inputjtag_TDO_driven,output[31:0]exit);reg[31:0]tickCounterReg;wire[31:0]tickCounterNxt;assigntickCounterNxt=(tickCounterReg==0)?TICK_DELAY:(tickCounterReg-1);bitr_reset;wire[31:0]random_bits=$random;wire#0.1__jtag_TDO=jtag_TDO_driven?jtag_TDO_data:random_bits[0];bit__jtag_TCK;bit__jtag_TMS;bit__jtag_TDI;bit__jtag_TRSTn;int__exit;reginit_done_sticky;assign#0.1jtag_TCK=__jtag_TCK;assign#0.1jtag_TMS=__jtag_TMS;assign#0.1jtag_TDI=__jtag_TDI;assign#0.1jtag_TRSTn=__jtag_TRSTn;assign#0.1exit=__exit;always@(posedgeclock)beginr_reset<=reset;if(reset||r_reset)begin__exit=0;tickCounterReg<=TICK_DELAY;init_done_sticky<=1'b0;__jtag_TCK=!__jtag_TCK;endelsebegininit_done_sticky<=init_done|init_done_sticky;if(enable&&init_done_sticky)begintickCounterReg<=tickCounterNxt;if(tickCounterReg==0)begin__exit=jtag_tick(__jtag_TCK,__jtag_TMS,__jtag_TDI,__jtag_TRSTn,__jtag_TDO);endendendendendmodule> expecting AST_ROOT
ERROR: Module 'SimJTAG' has not been found
</pre></p>
<p>The same error appears at the following test cases:<br />ru.ispras.verilog.parser.sample.RocketChipSimDtmVerilogPrinterTestCase</p> Retrascope RISC-V Benchmark - Bug #9475 (Closed): Picorv32Hx8kdemoVerilogPrinterTestCase: ERROR: ...https://forge.ispras.ru/issues/94752019-02-06T08:25:02ZSergey Smolovsmolov@ispras.ru
<p>When running the <strong>ru.ispras.verilog.parser.sample.Picorv32Hx8kdemoVerilogPrinterTestCase</strong>, the following error appears:<br /><pre>
ERROR: line 1:0 no viable alternative at input '('
ERROR: [Internal] null
java.lang.StackOverflowError
at org.antlr.runtime.BaseRecognizer.mismatchIsUnwantedToken(BaseRecognizer.java:127)
at org.antlr.runtime.BaseRecognizer.recoverFromMismatchedToken(BaseRecognizer.java:593)
at org.antlr.runtime.BaseRecognizer.match(BaseRecognizer.java:115)
at ru.ispras.verilog.parser.grammar.VerilogParser.begin_block_statement(VerilogParser.java:13992)
at ru.ispras.verilog.parser.grammar.VerilogParser.statement(VerilogParser.java:15145)
...
</pre></p>
<p>The same error appears for the following test cases: <br />ru.ispras.verilog.parser.sample.Picorv32IcebreakerVerilogPrinterTestCase<br />ru.ispras.verilog.parser.sample.Picorv32PicosocVerilogPrinterTestCase<br />ru.ispras.verilog.parser.sample.Picorv32SimpleuartVerilogPrinterTestCase<br />ru.ispras.verilog.parser.sample.Picorv32SpiflashVerilogPrinterTestCase<br />ru.ispras.verilog.parser.sample.Picorv32SpimemioVerilogPrinterTestCase</p> MicroTESK - Bug #9436 (Closed): ru.ispras.microtesk.mmu.translator.GeneralTestCase: java.lang.Ill...https://forge.ispras.ru/issues/94362019-01-17T14:45:54ZSergey Smolovsmolov@ispras.ru
<pre>
:test
Translating: ./src/test/mmu/general.mmu
Model name: general
Included: ./src/test/mmu/general.mmu
Included: address.mmu
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:95)
at ru.ispras.microtesk.mmu.translator.MmuTreeWalkerBase.assignContext(MmuTreeWalkerBase.java:199)
at ru.ispras.microtesk.mmu.translator.MmuTranslator.start(MmuTranslator.java:121)
at ru.ispras.microtesk.translator.Translator.translate(Translator.java:201)
at ru.ispras.microtesk.translator.TranslatorTest.translate(TranslatorTest.java:79)
at ru.ispras.microtesk.mmu.translator.GeneralTestCase.test(GeneralTestCase.java:26)
</pre>
<p>The exception is thrown, but the test passes</p> MicroTESK for MIPS - Bug #9377 (New): 'Failed to construct decoder' warnings in project's build loghttps://forge.ispras.ru/issues/93772018-11-08T11:34:41ZSergey Smolovsmolov@ispras.ru
<pre>
Warning: Failed to construct decoder for mfc0. Unrecognized field: rd.r
Warning: Failed to construct decoder for mfc0. Unrecognized field: rd.s
Warning: Failed to construct decoder for mfc0. Undecoded arguments: [rd]
Warning: Failed to construct decoder for mtc0. Unrecognized field: rd.r
Warning: Failed to construct decoder for mtc0. Unrecognized field: rd.s
Warning: Failed to construct decoder for mtc0. Undecoded arguments: [rd]
Warning: Failed to construct decoder for ext. Unrecognized field: (BVSUB size 00001)
Warning: Failed to construct decoder for ext. Undecoded arguments: [size]
Warning: Failed to construct decoder for ins. Unrecognized field: (BVSUB (BVADD pos size) 00001)
Warning: Failed to construct decoder for ins. Undecoded arguments: [size]
Warning: Failed to construct decoder for dins. Unrecognized field: (BVSUB (BVADD pos size) 00001)
Warning: Failed to construct decoder for dins. Undecoded arguments: [size]
Warning: Failed to construct decoder for dinsm. Unrecognized field: (BVEXTRACT 4 0 (BVSUB (BVADD (BVZEROEXT 1 pos) size) 100001))
Warning: Failed to construct decoder for dinsm. Undecoded arguments: [size]
Warning: Failed to construct decoder for dinsu. Unrecognized field: (BVEXTRACT 4 0 (BVSUB (BVADD pos (BVZEROEXT 1 size)) 100001))
Warning: Failed to construct decoder for dinsu. Unrecognized field: (BVEXTRACT 4 0 (BVSUB pos 100000))
Warning: Failed to construct decoder for dinsu. Undecoded arguments: [pos, size]
</pre> MicroTESK for MIPS - Bug #9376 (New): Warning: Group MIPS64FpuOp contains two items add_fmt and m...https://forge.ispras.ru/issues/93762018-11-08T11:33:31ZSergey Smolovsmolov@ispras.ru
<p>The warning above appears upon project building. To reproduce it, run './gradlew assemble' in Unix-like OS or 'gradlew.bat assemble' in Windows OS.</p> MicroTESK - Bug #9063 (Closed): microtesk/src/main/java/core/ru/ispras/microtesk/utils/PropertyMa...https://forge.ispras.ru/issues/90632018-07-05T07:28:46ZSergey Smolovsmolov@ispras.ru
<p>The following warning appears at the compilation process:<br /><pre><code class="text syntaxhl" data-language="text">Note: /home/ssedai/projects/microtesk/src/main/java/core/ru/ispras/microtesk/utils/PropertyMap.java uses unchecked or unsafe operations.
Note: Recompile with -Xlint:unchecked for details.
</code></pre></p> Retrascope - Bug #8681 (Closed): EngineRegistry fails to create toolchain when HashSet\HashMap ar...https://forge.ispras.ru/issues/86812018-01-19T13:30:09ZSergey Smolovsmolov@ispras.ru
<p>The result of EngineRegistry toolchain construction mechanism implicitly depends from order in sets\maps.<br />When HashSet\HashMap classes are used, it can return null, while with LinkedHashSet\LinkedHashMap it is ok.<br />To reproduce the bug, substitute set\map classes from linked to non-linked and run HlddAssertSmvPrinterTestCase on JDK 1.8.</p> Retrascope - Bug #5404 (Closed): [verilog][parser][cfg] java.lang.IllegalArgumentException: Unsup...https://forge.ispras.ru/issues/54042014-11-02T12:15:20ZSergey Smolovsmolov@ispras.ru
<p>Running: verilog-parser<br />Options: {v=[D:\Sergey\projects\retrascope.svn\trunk\retrascope\src\test\verilog\ram\ram.v], args=D:\Sergey\projects\retrascope.svn\trunk\retrascope\src\test\verilog\ram\ram.v --target efsm --engine cgaa-efsm-transformer}<br />2014.11.02 14:02:28.860. INFO: Start observing module ram.<br />2014.11.02 14:02:28.860. INFO: add variable clk [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.861. INFO: add variable rst [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.862. INFO: add variable val_rd [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.862. INFO: add variable val_wr [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.863. INFO: add variable addr_in [(BIT_VECTOR 2)] (Data[type=(BIT_VECTOR 2), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.864. INFO: add variable data_in [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.864. INFO: add variable val_out [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.865. INFO: add variable data_out [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.866. INFO: add variable is_ready [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.866. INFO: add variable mem0 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.867. INFO: add variable mem1 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.868. INFO: add variable mem2 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.868. INFO: add variable mem3 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.869. INFO: add variable result [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.870. INFO: add variable state [(BIT_VECTOR 2)] (Data[type=(BIT_VECTOR 2), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.871. INFO: add variable RAM_IDLE [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.875. INFO: add variable RAM_READ [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.876. INFO: add variable RAM_WRITE [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.877. INFO: add variable RAM_RESULT [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />Storing: cfg</p>
<p>Running: cfg-cgaa-transformer<br />Options: {args=D:\Sergey\projects\retrascope.svn\trunk\retrascope\src\test\verilog\ram\ram.v --target efsm --engine cgaa-efsm-transformer, cfg=<cfg>}<br />Storing: cgaa</p>
<p>Running: cgaa-efsm-transformer<br />Options: {cgaa=<cgaa>, args=D:\Sergey\projects\retrascope.svn\trunk\retrascope\src\test\verilog\ram\ram.v --target efsm --engine cgaa-efsm-transformer}<br />2014.11.02 14:02:28.888. ERROR: The exception has been encountered: java.lang.IllegalArgumentException: Unsupported data type: UNKNOWN<br /> at ru.ispras.fortress.solver.engine.z3.SMTStrings.textForData(SMTStrings.java:147)<br /> at ru.ispras.fortress.solver.engine.z3.SMTTextBuilder.onValue(SMTTextBuilder.java:303)<br /> at ru.ispras.fortress.solver.engine.z3.SMTTextBuilder.onValue(SMTTextBuilder.java:282)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitValue(ExprTreeWalker.java:209)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:152)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:192)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:160)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:192)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:160)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:192)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:160)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:127)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:100)<br /> at ru.ispras.fortress.solver.engine.z3.Z3TextSolver.solve(Z3TextSolver.java:120)<br /> at ru.ispras.fortress.expression.ExprUtils.isSAT(ExprUtils.java:350)<br /> at ru.ispras.fortress.expression.ExprUtils.areCompatible(ExprUtils.java:335)<br /> at ru.ispras.retrascope.engine.cgaa.transformer.efsm.CgaaStateExprVisitor.isSAT(CgaaStateExprVisitor.java:203)<br /> at ru.ispras.retrascope.engine.cgaa.transformer.efsm.CgaaStateExprVisitor.checkConditionsIfNot(CgaaStateExprVisitor.java:192)<br /> at ru.ispras.retrascope.engine.cgaa.transformer.efsm.CgaaStateExprVisitor.onBasicBlockBegin(CgaaStateExprVisitor.java:183)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitBasicBlock(CfgWalker.java:255)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:133)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitCase(CfgWalker.java:247)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:139)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitSwitch(CfgWalker.java:229)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:145)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitCase(CfgWalker.java:247)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:139)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitSwitch(CfgWalker.java:229)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:145)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitSource(CfgWalker.java:213)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:151)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitCfg(CfgWalker.java:204)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitProcess(CfgWalker.java:195)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitModule(CfgWalker.java:179)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitCfgModel(CfgWalker.java:166)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.start(CfgWalker.java:86)<br /> at ru.ispras.retrascope.engine.cfg.CfgEngine.start(CfgEngine.java:126)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:191)<br /> at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:106)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:191)<br /> at ru.ispras.retrascope.Retrascope$Run.start(Retrascope.java:117)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:320)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:341)<br /> at ru.ispras.retrascope.util.VerilogUtilTest.runRetrascope(VerilogUtilTest.java:120)<br /> at ru.ispras.retrascope.util.VerilogUtilTest.runVerilog(VerilogUtilTest.java:69)<br /> at ru.ispras.retrascope.util.HdlUtilTest.runVerilog(HdlUtilTest.java:137)<br /> at ru.ispras.retrascope.util.HdlUtilTest.runHdl(HdlUtilTest.java:51)</p> Java SoftFloat - Bug #5385 (Closed): Странная структура директорий проектаhttps://forge.ispras.ru/issues/53852014-10-24T07:55:28ZSergey Smolovsmolov@ispras.ru
<p>В репозитории проекта замечена папка jsoftfloat, находящаяся на том же уровне вложенности, что и традиционные branches, tags, trunk.<br />Это запланированное явление, или результат ошибки?</p> Retrascope - Bug #5096 (Closed): [basis] FileCreator: "Can't create file" errorhttps://forge.ispras.ru/issues/50962014-07-17T13:17:22ZSergey Smolovsmolov@ispras.ru
<p>Если файл уже был когда-то создан, то попытка пересоздать его с помощью метода newFile класса FileCreator приводит к ошибке "Can't create file".</p> Retrascope IDE - Bug #4991 (Closed): Не передается путь к HDL-описаниюhttps://forge.ispras.ru/issues/49912014-06-16T10:43:45ZSergey Smolovsmolov@ispras.ru
<p>Если во вкладке Input Files в меню Retrascope Tool Launcher выбрать *.vhd-файл, то инструменту Retrascope в качестве аргумента передается только имя файла без указания пути, что приводит к ошибке "File not found" VHDL-парсера.</p>