Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692020-02-06T10:22:06ZOpen-Source Projects
Redmine MicroTESK - Bug #10102 (Closed): incorrect ld scripts for x86 test programshttps://forge.ispras.ru/issues/101022020-02-06T10:22:06ZSergey Smolovsmolov@ispras.ru
<p>For x86 test programs emulation on QEMU4V, the following approach can be used. Test program should be compiled as <em>bootable drive</em> and run on QEMU4V ("-hda" option). The following linker script should be generated:<br /><pre>
SECTIONS
{
/* The BIOS loads the code from the disk to this location.
* We must tell that to the linker so that it can properly
* calculate the addresses of symbols we might jump to.
*/
. = 0x7c00;
.text :
{
__start = .;
*(.text)
/* Place the magic boot bytes at the end of the first 512 sector of the disk. */
. = 0x1FE;
SHORT(0xAA55)
}
}
</pre></p>
<p>Now ld scripts look as follows:<br /><pre>
ENTRY(_start)
SECTIONS
{
. = 0x7C00;
.text : { *(".text")}
. = 0x8000;
.data : { *(".data")}
.bss : { *(".bss COMMON")}
. = ALIGN(8);
. = . + 0x10000;
stack_top = .;
}
</pre></p> Verilog Translator - Bug #9993 (New): if two modules are passed to the tool and one includes anot...https://forge.ispras.ru/issues/99932019-12-18T12:43:15ZSergey Smolovsmolov@ispras.ru
<p>Suppose there are two files with Verilog modules: <em>a.v</em> and <em>b.v</em> (<em>a.v</em> contains "a" module, b.v contains "b" module). Module "a" includes module "b".</p>
<p>When the following args are used for the tool:<br /><pre>
a.v b.v --include-path /path/to/b/file --module-name a
</pre><br />the tool hangs. These arguments seem to be strange, because "b" module appears two times in the command line.<br />More adequate diagnostics should be shown here, and, of course, no freezes.</p> Verilog Translator - Bug #9915 (Closed): "Cycle inclusion has been detected in fine <filename>" e...https://forge.ispras.ru/issues/99152019-11-13T12:01:33ZSergey Smolovsmolov@ispras.ru
<p>The tool reports "Cycle inclusion has been detected in fine <filename>" error for the case when "a.v" and "b.v" modules include "c.v" module.</p>
<p>To reproduce the bug, checkout to <a class="changeset" title="hdl-benchmark submodule update Signed-off-by: chudnovmaxim <chudnov@ispras.ru>" href="https://forge.ispras.ru/projects/veritrans/repository/veritrans/revisions/5ca788cdbc460bf393ccdef4b9cd6451f71acdd0">5ca788cd</a> commit and run <strong>ru.ispras.verilog.parser.VerilogQuipTestCase</strong>. It should be fail-free, but it is not.</p>
<p>IMPORTANT: please run all the project tests before push and compare your results with Jenkins!</p> Retrascope - Task #9911 (Closed): merge "*/sample/*TestCase" Java test cases https://forge.ispras.ru/issues/99112019-11-12T08:52:05ZSergey Smolovsmolov@ispras.ru
<p>There are separate "*/sample/*TestCase" Java classes in the project. They contain duplicated code and should be merged the same way as benchmark-related test case collections at Verilog Translator project. See <strong>ru.ispras.verilog.parser.VerilogQuipTestCase</strong> for example.</p> Verilog Translator - Bug #9902 (New): java.lang.IllegalArgumentException: Descriptor for '<var na...https://forge.ispras.ru/issues/99022019-11-01T16:20:57ZSergey Smolovsmolov@ispras.ru
<p>When running the tool on the <a href="https://github.com/ispras/hdl-benchmarks/blob/master/hdl/iwls05/faraday/rtl/DMA/hdl/dma_chsel.v" class="external">dma_chsel.v</a> and <a href="https://github.com/ispras/hdl-benchmarks/blob/master/hdl/iwls05/faraday/rtl/DMA/hdl/dma_rrarb.v" class="external">dma_rrarb.v</a> modules the following error log appears:<br /><pre>
ru.ispras.verilog.parser.VerilogIwlsTestCase > runTest_dma_chsel STANDARD_ERROR
java.lang.IllegalArgumentException: Descriptor for 'dma_chsel.arb_chcsr_reg' has not been found: {dma_chsel.HCLK=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.HRSTn=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.dma_req=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.dma_ack=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.dma_tc=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.csr=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.sync=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.de_err_notify=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c0csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c0abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c0llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c1csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c1abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c1llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c2csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c2abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c2llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c3csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c3abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c3llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c4csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c4abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c4llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c5csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c5abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c5llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c6csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c6abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c6llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c7csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c7abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c7llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.arb_ch_sel=(BIT_VECTOR 3):(SHIFT 0)}
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:109)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute$1.apply(VerilogTransformerVariableSubstitute.java:121)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:169)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:229)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:213)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute.shiftRanges(VerilogTransformerVariableSubstitute.java:95)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute.transform(VerilogTransformerVariableSubstitute.java:142)
at ru.ispras.verilog.parser.transformer.VerilogTransformerComposite.transform(VerilogTransformerComposite.java:57)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:177)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:189)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.onDeclarationBegin(VerilogTransformer.java:67)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$13.onBegin(VerilogNodeVisitor.java:385)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:81)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.run(VerilogTransformer.java:52)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiate(VerilogInstantiator.java:145)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateDescriptor(VerilogInstantiator.java:124)
at ru.ispras.verilog.parser.elaborator.VerilogDesign$Builder.build(VerilogDesign.java:102)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:246)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:187)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:111)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:71)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:45)
at ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_dma_chsel(VerilogIwlsTestCase.java:51)
</pre></p>
<p>To reproduce the bug, run <strong>ru.ispras.verilog.parser.VerilogIwlsTestCase#runTest_dma_chsel</strong> test from <em>Retrascope Test Suite</em> project.</p> Verilog Translator - Bug #9798 (Closed): ru.ispras.verilog.parser.sample.Bug9798TestCase: incorre...https://forge.ispras.ru/issues/97982019-08-27T08:47:02ZSergey Smolovsmolov@ispras.ru
<p>For the following module:<br /><pre>
module bv_non_zero_idx(in, clk, out);
input [2:1] in;
input clk;
output [1:0] out;
reg [1:0] data;
assign out = data;
always @(posedge clk)
begin
if (in[2:2] == 1'b1)
begin
data <= 2'b11;
end
if (in[1:1] == 1'b0)
begin
data <= 2'b01;
end
end
endmodule
</pre></p>
<p>the VerilogPrinter engine produces the following output:<br /><pre>
module bv_non_zero_idx(in /* DECL: in */, clk /* DECL: clk */, out /* DECL: out */, in /* DECL: in */, clk /* DECL: clk */, out /* DECL: out */);
input [00000000000000000000000000000010 /* 00000000000000000000000000000010 */:00000000000000000000000000000001 /* 00000000000000000000000000000001 */] in;
input clk;
output [00000000000000000000000000000001 /* 00000000000000000000000000000001 */:00000000000000000000000000000000 /* 00000000000000000000000000000000 */] out;
reg [00000000000000000000000000000001 /* 00000000000000000000000000000001 */:00000000000000000000000000000000 /* 00000000000000000000000000000000 */] data;
assign out /* DECL: out */ = data /* data */;
always
@(posedge clk /* clk */)
begin: block.0
if((in[00000000000000000000000000000010:00000000000000000000000000000010] == 1) /* (EQ (BVEXTRACT 00000000000000000000000000000010 00000000000000000000000000000010 in) 1) */)
/* ASSERT: (in[00000000000000000000000000000010:00000000000000000000000000000010] == 1) /* (EQ (BVEXTRACT 00000000000000000000000000000010 00000000000000000000000000000010 in) 1) */ */
begin: block.1
data /* DECL: data */ <= 11 /* 11 */;
end
else
/* ASSERT: ! (in[00000000000000000000000000000010:00000000000000000000000000000010] == 1) /* (NOT (EQ (BVEXTRACT 00000000000000000000000000000010 00000000000000000000000000000010 in) 1)) */ */
begin: block.2
end
end
if((in[00000000000000000000000000000001:00000000000000000000000000000001] == 0) /* (EQ (BVEXTRACT 00000000000000000000000000000001 00000000000000000000000000000001 in) 0) */)
/* ASSERT: (in[00000000000000000000000000000001:00000000000000000000000000000001] == 0) /* (EQ (BVEXTRACT 00000000000000000000000000000001 00000000000000000000000000000001 in) 0) */ */
begin: block.3
data /* DECL: data */ <= 01 /* 01 */;
end
else
/* ASSERT: ! (in[00000000000000000000000000000001:00000000000000000000000000000001] == 0) /* (NOT (EQ (BVEXTRACT 00000000000000000000000000000001 00000000000000000000000000000001 in) 0)) */ */
begin: block.4
end
end
end
endmodule
WARN: Can't cast (BVEXTRACT 2 2 in) to (BIT_VECTOR 1) type; no changes.
@(posedge clk)
begin: block.0
if((in[2:2] == 1))
begin: block.1
bv_non_zero_idx.data <= 11;
end
else
begin: block.2
end
end
if((in[1:1] == 0))
begin: block.3
bv_non_zero_idx.data <= 01;
end
else
begin: block.4
end
end
end
assign out = bv_non_zero_idx.data;
</pre></p>
<p>Here params for BVEXTRACT operation of <strong>in</strong> variable are incorrect: an offset should be taken into account</p> Verilog Translator - Bug #9296 (Closed): vcegar-tests/cache_coherence/two_processor_bin_2.v:46: i...https://forge.ispras.ru/issues/92962018-10-04T10:47:05ZSergey Smolovsmolov@ispras.ru
<p>The 46th line of <em>two_processor_bin_2.v</em> file:<br /><pre><code class="text syntaxhl" data-language="text">assign ND_inB = (master_outA ) ? ND_inA : (ndB && !bus_ackB);
</code></pre><br />produces the error via model checking:<br /><pre>
illegal types of "then" and "else" expressions : unsigned word[1] and boolean
</pre><br />The <em>ND_inA</em> variable has 1-bit vector dataType ("then"), but the "ndB && !bus_ackB" expression ("else") is represented by the VeriTrans as follows: (AND (EQ bus_ackB 0) (NOT (EQ ndB 0))).<br />So it has Boolean data type since all operations are logic, not bitvector-oriented.</p> QEMU4V - Bug #9288 (Closed): /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’https://forge.ispras.ru/issues/92882018-09-28T08:44:54ZSergey Smolovsmolov@ispras.ru
<p>Compilation error:</p>
<pre>
/srv/****/workspace/QEMU4V/target/mips/translate.c: In function ‘gen_logic_imm’:
/srv/****/workspace/QEMU4V/target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’
else {
^~~~
/srv/****/workspace/QEMU4V/rules.mak:69: recipe for target 'target/mips/translate.o' failed
make[1]: *** [target/mips/translate.o] Error 1
Makefile:481: recipe for target 'subdir-mips-softmmu' failed
make: *** [subdir-mips-softmmu] Error 2
:make FAILED
</pre> Verilog Translator - Bug #9282 (Closed): ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: ...https://forge.ispras.ru/issues/92822018-09-15T08:58:10ZSergey Smolovsmolov@ispras.ru
<p>In the <strong>ru.ispras.verilog.parser.sample.DataMemTestCase</strong> log the following record appears:<br /><pre>
DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr)
</pre><br />It comes from the following fragment of the Verilog '_data_mem.v_' module:<br /><pre><code class="text syntaxhl" data-language="text">wire [`DATA_MEM_ADDR_WIDTH-1 : 0] ram_addr = mem_access_addr[`DATA_MEM_ADDR_WIDTH-1 : 0];
</code></pre><br />The Fortress node that is created from the right hand side expression of this assignment is incorrect, because the first param of BVEXTRACT operation should be greater or equal to the second one.</p> Verilog Translator - Task #9251 (Closed): calculate type of index for bit-vector arrayshttps://forge.ispras.ru/issues/92512018-08-29T13:16:51ZSergey Smolovsmolov@ispras.ru
<p>Now the index type for bit vector array variables is set to 32-bit.<br />It should be calculated more precisely.</p> Verilog Translator - Bug #9250 (Closed): ru.ispras.verilog.parser.sample.IfStageTestCase: src/tes...https://forge.ispras.ru/issues/92502018-08-29T07:53:19ZSergey Smolovsmolov@ispras.ru
<p>The test produces the following error log:<br /><pre>
...
ERROR: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc'
ERROR: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc'
ERROR: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc'
java.lang.StackOverflowError
at ru.ispras.verilog.parser.grammar.VerilogParser.number(VerilogParser.java)
at ru.ispras.verilog.parser.grammar.VerilogParser.primary(VerilogParser.java:26555)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_0(VerilogParser.java:23694)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_1(VerilogParser.java:23770)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_2(VerilogParser.java:23865)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_3(VerilogParser.java:23997)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_4(VerilogParser.java:24167)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_5(VerilogParser.java:24333)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_6(VerilogParser.java:24503)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_7(VerilogParser.java:24673)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_8(VerilogParser.java:24843)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_9(VerilogParser.java:25013)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_10(VerilogParser.java:25183)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_11(VerilogParser.java:25353)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_12(VerilogParser.java:25523)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_13(VerilogParser.java:25693)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_14(VerilogParser.java:25868)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression(VerilogParser.java:26037)
at ru.ispras.verilog.parser.grammar.VerilogParser.discrete_assignment_statement(VerilogParser.java:12931)
...
</pre></p> Retrascope - Task #6367 (Closed): Fortress expressions printing in an SMV formathttps://forge.ispras.ru/issues/63672015-10-25T18:19:41ZSergey Smolovsmolov@ispras.ru
<p>We need utility methods for Fortress expressions printing in an SMV format.</p>
<p>The most wanted use case is:</p>
<p>we have a collection of Fortress expressions: <code>e[1]</code>, <code>e[2]</code>, ... , <code>e[n]</code>;<br />we want to produce and SMV file of the following structure (it is supposed to be so):</p>
<pre>
declarations(e[1])
...
declarations(e[n])
formula(e[1])
...
formula(e[n])
</pre>
<p>where i = 1, ... , n; <code>declarations(e[i])</code> is a list of variable declarations that are used in <code>e[i]</code> expression; <code>formula(e[i])</code> is an SMV equivalent for <code>e[i]</code> expression.</p> Retrascope - Bug #5719 (Closed): EFSM Test Generator hangs on b11https://forge.ispras.ru/issues/57192015-03-18T07:20:55ZSergey Smolovsmolov@ispras.ru
<p>The EFSM Test Generator that is run at <strong>EfsmTestGeneratorVhdlTestCase</strong> hangs on b11 VHDL design (or this testcase continues more than <strong>8 hours</strong> - it is very suspicious).</p>
<p>The log fragment is attached below.</p> Retrascope - Bug #5680 (Closed): [efsm][generator][test][fate] DirectedFateGenerator.generateSequ...https://forge.ispras.ru/issues/56802015-03-04T08:01:26ZSergey Smolovsmolov@ispras.ru
<p>The error appears upon b07 design processing.</p>
<p>The stack trace:</p>
<p>[stack]<br />java.lang.NullPointerException<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.DirectedFateGenerator.generateSequence(DirectedFateGenerator.java:226)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.DirectedFateGenerator.getNextSequenceIterator(DirectedFateGenerator.java:163)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGenerator.start(EfsmFateTestGenerator.java:315)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGenerator.start(EfsmFateTestGenerator.java:52)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:200)<br /> at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:106)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:200)<br /> at ru.ispras.retrascope.Retrascope$Run.start(Retrascope.java:116)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:333)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:355)<br /> at ru.ispras.retrascope.util.VhdlUtilTest.runRetrascope(VhdlUtilTest.java:148)<br /> at ru.ispras.retrascope.util.VhdlUtilTest.runVhdl(VhdlUtilTest.java:73)<br /> at ru.ispras.retrascope.util.HdlUtilTest.runVhdl(HdlUtilTest.java:94)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGeneratorVhdlTestCase.generate(EfsmFateTestGeneratorVhdlTestCase.java:32)<br />[/stack]</p>
<p>Full log is attached below.</p> С++TESK Development Environment - Task #3756 (New): Генерация C++ кода для модели сообщенийhttps://forge.ispras.ru/issues/37562012-12-05T15:32:06ZSergey Smolovsmolov@ispras.ru
<p>Небходимо разработать метод генерации C++ кода для модели сообщений.</p>
<p>На вход методу подается несколько объектов класса Adapter. В виде какой структуры данных эти "несколько" будут подаваться - на твое усмотрение. Например, можно взять ту же, что использовалась<br />в инструменте signalsGrouper для хранения набора накликанных "интерфейсов".<br />Т.к. все адаптеры между собой различны и полных совпадений между ними быть не должно, то из самых общих соображений могу предложить использовать java.util.Set.</p>
<p>Суть метода такова: проходим по всем адаптерам и извлекаем из них объекты MessageType и помещаем их в промежуточное хранилище (возможно, тот же Set). При этом необходимо проверять, что в хранилище ещё нет такого же типа сообщений (а при разработке адаптеров для разных интерфейсов вполне реально, что они будут использовать сообщения одного типа)- делать такую проверку лучше всего посредством разработки метода сравнения equals в классе MessageType.</p>
<p><strong>Шаблон для *.h-файла</strong></p>
<pre>
#pragma once
#include <hw/message.hpp>
namespace имя_пространства_имен {
</pre> Про извлечение название пространства имен смотри <a class="issue tracker-2 status-1 priority-4 priority-default" title="Task: namespace name for test system prototypes (New)" href="https://forge.ispras.ru/issues/3755">#3755</a>
<p>Для каждого типа сообщений далее генерируем следующий код:<br /><pre>
MESSAGE(имя_типа_сообщений)
{
public:
имя_типа_сообщений();
virtual ~имя_типа_сообщений();
SUPPORT_CLONE(имя_типа_сообщений);
</pre></p>
<p>Далее для всех полей сообщения данного типа генерируем вызов соответствующего макроса. Макросы бывают следующие:<br />1) Если размер поля больше 64 бит, то нужно использовать<br /> - CPPTESK_DECLARE_FIELD_ARRAY(имя_поля, размер_массива, размер_поля); - если маска не задана<br /> - CPPTESK_DECLARE_MASKED_FIELD_ARRAY(имя_поля, размер_массива, размер_поля, маска_поля); - если маска задана</p>
<p>В силу особенностей реализации параметр размер_поля делаем равным 64, а параметр размер_массива делаем таким, чтобы удовлетворялось следующее неравенство:</p>
<p>capacity <= размер_поля*размер_массива</p>
<p>где capacity - одноименное поле соответствующего экземпляра класса MessageField.</p>
<p>2) Если размер поля меньше, или равен 64 бит, то нужно использовать<br /> - CPPTESK_DECLARE_FIELD(имя_поля, размер_поля);<br /> - CPPTESK_DECLARE_MASKED_FIELD(имя_поля, размер_поля, маска_поля);<br /> - CPPTESK_DECLARE_BIT(имя_поля); - если размер поля равен 1</p>
<pre>
};
}
</pre>
<p>Заголовочный файл называем имя_пространства_имен_msg.h</p>
<p><strong>Шаблон для .cpp файла</strong></p>
<pre>
include <имя_пространства_имен_msg.h>
namespace имя_пространства_имен {
</pre>
<p>Для каждого из типов сообщений генерируем следующий код конструктора и деструктора</p>
<pre>
имя_типа_сообщений::имя_типа_сообщений(void)
{
</pre>
<p>Для всех полей сообщения, у которых incomparable равно false (см. <a class="issue tracker-2 status-5 priority-4 priority-default closed" title="Task: флаг incomparable в полях сообщений (Closed)" href="https://forge.ispras.ru/issues/3754">#3754</a>):<br /><pre>
ADD_FIELD(имя_типа_сообщений::имя_поля);
</pre></p>
<p>Для всех полей сообщения, у которых incomparable равно true (см. <a class="issue tracker-2 status-5 priority-4 priority-default closed" title="Task: флаг incomparable в полях сообщений (Closed)" href="https://forge.ispras.ru/issues/3754">#3754</a>):<br /><pre>
ADD_INCOMPARABLE_FIELD(имя_типа_сообщений::имя_поля);
</pre></p>
<p>Рандомизируем значения полей - только если оно соответствует входному интерфейсу!<br /><pre>
RANDOMIZE_MESSAGE(*this);
}
имя_типа_сообщений::~имя_типа_сообщений(void) {}
}
</pre></p>
<p>Рекомендация - данную задачу стоить решать посредством разработки нескольких относительно простых методов в соответствующих классах, а не одного сложного.</p>