Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692020-02-06T10:22:06ZOpen-Source Projects
Redmine MicroTESK - Bug #10102 (Closed): incorrect ld scripts for x86 test programshttps://forge.ispras.ru/issues/101022020-02-06T10:22:06ZSergey Smolovsmolov@ispras.ru
<p>For x86 test programs emulation on QEMU4V, the following approach can be used. Test program should be compiled as <em>bootable drive</em> and run on QEMU4V ("-hda" option). The following linker script should be generated:<br /><pre>
SECTIONS
{
/* The BIOS loads the code from the disk to this location.
* We must tell that to the linker so that it can properly
* calculate the addresses of symbols we might jump to.
*/
. = 0x7c00;
.text :
{
__start = .;
*(.text)
/* Place the magic boot bytes at the end of the first 512 sector of the disk. */
. = 0x1FE;
SHORT(0xAA55)
}
}
</pre></p>
<p>Now ld scripts look as follows:<br /><pre>
ENTRY(_start)
SECTIONS
{
. = 0x7C00;
.text : { *(".text")}
. = 0x8000;
.data : { *(".data")}
.bss : { *(".bss COMMON")}
. = ALIGN(8);
. = . + 0x10000;
stack_top = .;
}
</pre></p> Verilog Translator - Bug #9993 (New): if two modules are passed to the tool and one includes anot...https://forge.ispras.ru/issues/99932019-12-18T12:43:15ZSergey Smolovsmolov@ispras.ru
<p>Suppose there are two files with Verilog modules: <em>a.v</em> and <em>b.v</em> (<em>a.v</em> contains "a" module, b.v contains "b" module). Module "a" includes module "b".</p>
<p>When the following args are used for the tool:<br /><pre>
a.v b.v --include-path /path/to/b/file --module-name a
</pre><br />the tool hangs. These arguments seem to be strange, because "b" module appears two times in the command line.<br />More adequate diagnostics should be shown here, and, of course, no freezes.</p> Verilog Translator - Bug #9902 (New): java.lang.IllegalArgumentException: Descriptor for '<var na...https://forge.ispras.ru/issues/99022019-11-01T16:20:57ZSergey Smolovsmolov@ispras.ru
<p>When running the tool on the <a href="https://github.com/ispras/hdl-benchmarks/blob/master/hdl/iwls05/faraday/rtl/DMA/hdl/dma_chsel.v" class="external">dma_chsel.v</a> and <a href="https://github.com/ispras/hdl-benchmarks/blob/master/hdl/iwls05/faraday/rtl/DMA/hdl/dma_rrarb.v" class="external">dma_rrarb.v</a> modules the following error log appears:<br /><pre>
ru.ispras.verilog.parser.VerilogIwlsTestCase > runTest_dma_chsel STANDARD_ERROR
java.lang.IllegalArgumentException: Descriptor for 'dma_chsel.arb_chcsr_reg' has not been found: {dma_chsel.HCLK=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.HRSTn=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.dma_req=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.dma_ack=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.dma_tc=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.csr=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.sync=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.de_err_notify=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c0csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c0abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c0llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c1csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c1abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c1llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c2csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c2abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c2llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c3csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c3abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c3llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c4csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c4abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c4llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c5csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c5abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c5llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c6csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c6abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c6llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c7csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c7abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c7llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.arb_ch_sel=(BIT_VECTOR 3):(SHIFT 0)}
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:109)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute$1.apply(VerilogTransformerVariableSubstitute.java:121)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:169)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:229)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:213)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute.shiftRanges(VerilogTransformerVariableSubstitute.java:95)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute.transform(VerilogTransformerVariableSubstitute.java:142)
at ru.ispras.verilog.parser.transformer.VerilogTransformerComposite.transform(VerilogTransformerComposite.java:57)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:177)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:189)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.onDeclarationBegin(VerilogTransformer.java:67)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$13.onBegin(VerilogNodeVisitor.java:385)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:81)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.run(VerilogTransformer.java:52)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiate(VerilogInstantiator.java:145)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateDescriptor(VerilogInstantiator.java:124)
at ru.ispras.verilog.parser.elaborator.VerilogDesign$Builder.build(VerilogDesign.java:102)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:246)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:187)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:111)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:71)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:45)
at ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_dma_chsel(VerilogIwlsTestCase.java:51)
</pre></p>
<p>To reproduce the bug, run <strong>ru.ispras.verilog.parser.VerilogIwlsTestCase#runTest_dma_chsel</strong> test from <em>Retrascope Test Suite</em> project.</p> Verilog Translator - Bug #9798 (Closed): ru.ispras.verilog.parser.sample.Bug9798TestCase: incorre...https://forge.ispras.ru/issues/97982019-08-27T08:47:02ZSergey Smolovsmolov@ispras.ru
<p>For the following module:<br /><pre>
module bv_non_zero_idx(in, clk, out);
input [2:1] in;
input clk;
output [1:0] out;
reg [1:0] data;
assign out = data;
always @(posedge clk)
begin
if (in[2:2] == 1'b1)
begin
data <= 2'b11;
end
if (in[1:1] == 1'b0)
begin
data <= 2'b01;
end
end
endmodule
</pre></p>
<p>the VerilogPrinter engine produces the following output:<br /><pre>
module bv_non_zero_idx(in /* DECL: in */, clk /* DECL: clk */, out /* DECL: out */, in /* DECL: in */, clk /* DECL: clk */, out /* DECL: out */);
input [00000000000000000000000000000010 /* 00000000000000000000000000000010 */:00000000000000000000000000000001 /* 00000000000000000000000000000001 */] in;
input clk;
output [00000000000000000000000000000001 /* 00000000000000000000000000000001 */:00000000000000000000000000000000 /* 00000000000000000000000000000000 */] out;
reg [00000000000000000000000000000001 /* 00000000000000000000000000000001 */:00000000000000000000000000000000 /* 00000000000000000000000000000000 */] data;
assign out /* DECL: out */ = data /* data */;
always
@(posedge clk /* clk */)
begin: block.0
if((in[00000000000000000000000000000010:00000000000000000000000000000010] == 1) /* (EQ (BVEXTRACT 00000000000000000000000000000010 00000000000000000000000000000010 in) 1) */)
/* ASSERT: (in[00000000000000000000000000000010:00000000000000000000000000000010] == 1) /* (EQ (BVEXTRACT 00000000000000000000000000000010 00000000000000000000000000000010 in) 1) */ */
begin: block.1
data /* DECL: data */ <= 11 /* 11 */;
end
else
/* ASSERT: ! (in[00000000000000000000000000000010:00000000000000000000000000000010] == 1) /* (NOT (EQ (BVEXTRACT 00000000000000000000000000000010 00000000000000000000000000000010 in) 1)) */ */
begin: block.2
end
end
if((in[00000000000000000000000000000001:00000000000000000000000000000001] == 0) /* (EQ (BVEXTRACT 00000000000000000000000000000001 00000000000000000000000000000001 in) 0) */)
/* ASSERT: (in[00000000000000000000000000000001:00000000000000000000000000000001] == 0) /* (EQ (BVEXTRACT 00000000000000000000000000000001 00000000000000000000000000000001 in) 0) */ */
begin: block.3
data /* DECL: data */ <= 01 /* 01 */;
end
else
/* ASSERT: ! (in[00000000000000000000000000000001:00000000000000000000000000000001] == 0) /* (NOT (EQ (BVEXTRACT 00000000000000000000000000000001 00000000000000000000000000000001 in) 0)) */ */
begin: block.4
end
end
end
endmodule
WARN: Can't cast (BVEXTRACT 2 2 in) to (BIT_VECTOR 1) type; no changes.
@(posedge clk)
begin: block.0
if((in[2:2] == 1))
begin: block.1
bv_non_zero_idx.data <= 11;
end
else
begin: block.2
end
end
if((in[1:1] == 0))
begin: block.3
bv_non_zero_idx.data <= 01;
end
else
begin: block.4
end
end
end
assign out = bv_non_zero_idx.data;
</pre></p>
<p>Here params for BVEXTRACT operation of <strong>in</strong> variable are incorrect: an offset should be taken into account</p> Verilog Translator - Bug #9296 (Closed): vcegar-tests/cache_coherence/two_processor_bin_2.v:46: i...https://forge.ispras.ru/issues/92962018-10-04T10:47:05ZSergey Smolovsmolov@ispras.ru
<p>The 46th line of <em>two_processor_bin_2.v</em> file:<br /><pre><code class="text syntaxhl" data-language="text">assign ND_inB = (master_outA ) ? ND_inA : (ndB && !bus_ackB);
</code></pre><br />produces the error via model checking:<br /><pre>
illegal types of "then" and "else" expressions : unsigned word[1] and boolean
</pre><br />The <em>ND_inA</em> variable has 1-bit vector dataType ("then"), but the "ndB && !bus_ackB" expression ("else") is represented by the VeriTrans as follows: (AND (EQ bus_ackB 0) (NOT (EQ ndB 0))).<br />So it has Boolean data type since all operations are logic, not bitvector-oriented.</p> Verilog Translator - Bug #9282 (Closed): ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: ...https://forge.ispras.ru/issues/92822018-09-15T08:58:10ZSergey Smolovsmolov@ispras.ru
<p>In the <strong>ru.ispras.verilog.parser.sample.DataMemTestCase</strong> log the following record appears:<br /><pre>
DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr)
</pre><br />It comes from the following fragment of the Verilog '_data_mem.v_' module:<br /><pre><code class="text syntaxhl" data-language="text">wire [`DATA_MEM_ADDR_WIDTH-1 : 0] ram_addr = mem_access_addr[`DATA_MEM_ADDR_WIDTH-1 : 0];
</code></pre><br />The Fortress node that is created from the right hand side expression of this assignment is incorrect, because the first param of BVEXTRACT operation should be greater or equal to the second one.</p> Verilog Translator - Bug #9250 (Closed): ru.ispras.verilog.parser.sample.IfStageTestCase: src/tes...https://forge.ispras.ru/issues/92502018-08-29T07:53:19ZSergey Smolovsmolov@ispras.ru
<p>The test produces the following error log:<br /><pre>
...
ERROR: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc'
ERROR: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc'
ERROR: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc'
java.lang.StackOverflowError
at ru.ispras.verilog.parser.grammar.VerilogParser.number(VerilogParser.java)
at ru.ispras.verilog.parser.grammar.VerilogParser.primary(VerilogParser.java:26555)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_0(VerilogParser.java:23694)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_1(VerilogParser.java:23770)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_2(VerilogParser.java:23865)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_3(VerilogParser.java:23997)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_4(VerilogParser.java:24167)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_5(VerilogParser.java:24333)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_6(VerilogParser.java:24503)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_7(VerilogParser.java:24673)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_8(VerilogParser.java:24843)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_9(VerilogParser.java:25013)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_10(VerilogParser.java:25183)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_11(VerilogParser.java:25353)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_12(VerilogParser.java:25523)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_13(VerilogParser.java:25693)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression_14(VerilogParser.java:25868)
at ru.ispras.verilog.parser.grammar.VerilogParser.expression(VerilogParser.java:26037)
at ru.ispras.verilog.parser.grammar.VerilogParser.discrete_assignment_statement(VerilogParser.java:12931)
...
</pre></p> Verilog Translator - Bug #9239 (Closed): ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: j...https://forge.ispras.ru/issues/92392018-08-20T10:55:53ZSergey Smolovsmolov@ispras.ru
<p>The tool's error log includes the following:<br /><pre>
ERROR: ../src/test/verilog/rest-tests/mips16/IF_stage.v line 31:24 extraneous input ''b0' expecting SEMI
DEBUG: Expanding macro '8' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '8' ...
DEBUG: End of the token source 'null'
ERROR: ../src/test/verilog/rest-tests/mips16/IF_stage.v line 39:25 extraneous input ''d1' expecting SEMI
</pre></p> Verilog Translator - Bug #9224 (Closed): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_...https://forge.ispras.ru/issues/92242018-08-16T08:08:58ZSergey Smolovsmolov@ispras.ru
<p>The test case produces the following error:<br /><pre>
ERROR: Function declaration '$random' has not been found
1 error(s), 0 warning(s)
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkFalse(InvariantChecks.java:68)
at ru.ispras.verilog.parser.VerilogTranslator.exit(VerilogTranslator.java:104)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkFunctionCall(VerilogStaticChecker.java:573)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.access$000(VerilogStaticChecker.java:63)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker$ExprTreeVisitor.onOperationBegin(VerilogStaticChecker.java:88)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:139)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:391)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:403)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:420)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:446)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.onAssignBegin(VerilogStaticChecker.java:114)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$2.onBegin(VerilogNodeVisitor.java:253)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:87)
at ru.ispras.verilog.parser.VerilogSyntaxBackend.start(VerilogSyntaxBackend.java:80)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:170)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:72)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:58)
at ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PCI_BUS_Verilog_MV_files_PCInorm(VerilogTexas97TestCase.java:476)
</pre></p>
<p>To reproduce the bug, run <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PCI_BUS_Verilog_MV_files_PCInorm</strong> test case.</p> Verilog Translator - Bug #9222 (Closed): ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.r...https://forge.ispras.ru/issues/92222018-08-15T09:05:31ZSergey Smolovsmolov@ispras.ru
<pre>
java.lang.IllegalStateException: Parameter is not a value: LOGLENGTH
at ru.ispras.fortress.expression.NodeOperation.getParams(NodeOperation.java:289)
at ru.ispras.fortress.expression.NodeOperation.getDataType(NodeOperation.java:197)
at ru.ispras.fortress.expression.Node.isType(Node.java:177)
at ru.ispras.fortress.expression.ExprUtils.isType(ExprUtils.java:84)
at ru.ispras.verilog.parser.processor.VerilogExprTransformer$3.apply(VerilogExprTransformer.java:216)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:169)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:229)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
at ru.ispras.verilog.parser.processor.VerilogExprTransformer.transform(VerilogExprTransformer.java:62)
at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:180)
at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:191)
at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:210)
at ru.ispras.verilog.parser.elaborator.VerilogTransformer.onAssignBegin(VerilogTransformer.java:77)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$2.onBegin(VerilogNodeVisitor.java:253)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:81)
at ru.ispras.verilog.parser.elaborator.VerilogTransformer.run(VerilogTransformer.java:54)
at ru.ispras.verilog.parser.elaborator.VerilogCallCollector.transform(VerilogCallCollector.java:55)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.addProcess(VerilogElaborator.java:460)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:324)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:194)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:170)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:72)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:58)
at ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Sampleq_twoFifo1(VerilogVisVerilog2SmvTestCase.java:121)
</pre>
<p>This bug comes from the fact, that 'LOGLENGTH' parameter was not substituted by it's value '2'in the resulting representation of the 'twoFifo1.v' Verilog module. The module includes the following code:<br /><pre><code class="text syntaxhl" data-language="text">/*
*
* Taken from VIS Benchmarks <ftp://vlsi.colorado.edu/pub/vis/vis-verilog-models-1.3.tar.gz>
* Modified by Ahmed Irfan <irfan@fbk.eu>
*
*/
module sampleq (reset, inaddr, validin, readin, clkin, bus_gnt_raw,
outaddr, validout, outisaread, readheadentry);
...
parameter LOGLENGTH = 2; //no. of bits required to encode
// head/tail pointers
reg [LOGLENGTH-1:0] readtail; // points to the next incoming read address
reg [LOGLENGTH-1:0] readhead; // points to the next outgoing read address
wire readfull, writefull, readempty, writeempty;
...
// read queue is full
assign readfull = (((readtail +1)&{LOGLENGTH{1'b1}}) == readhead);
...
endmodule // sampleq
</code></pre></p> Verilog Translator - Bug #9215 (Rejected): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTes...https://forge.ispras.ru/issues/92152018-08-11T15:24:15ZSergey Smolovsmolov@ispras.ru
<pre>
Module name: mem
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 47:19 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 50:19 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 147:5 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 148:12 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 171:5 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 179:5 mismatched input 'reg' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 47:8 required (...)+ loop did not match anything at input 'wire'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 47:8 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Starting the backend 'printer'...
module mem(.clkclk /* DECL: clk */, .TS_TS_ /* DECL: TS_ */, .TTTT /* DECL: TT */, .GBL_GBL_ /* DECL: GBL_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .DBB_DBB_ /* DECL: DBB_ */, .TA_TA_ /* DECL: TA_ */, .DRTRY_DRTRY_ /* DECL: DRTRY_ */, .BG1_BG1_ /* DECL: BG1_ */, .BG2_BG2_ /* DECL: BG2_ */, .DBG1_DBG1_ /* DECL: DBG1_ */, clk /* DECL: clk */, TS_ /* DECL: TS_ */, TT /* DECL: TT */, GBL_ /* DECL: GBL_ */, AACK_ /* DECL: AACK_ */, ARTRY_ /* DECL: ARTRY_ */, DBB_ /* DECL: DBB_ */, TA_ /* DECL: TA_ */, DRTRY_ /* DECL: DRTRY_ */, BG1_ /* DECL: BG1_ */, BG2_ /* DECL: BG2_ */, DBG1_ /* DECL: DBG1_ */);
input clk;
input TS_;
input [00000000000000000000000000000000:00000000000000000000000000000100] TT;
input GBL_;
output AACK_;
input ARTRY_;
input DBB_;
output TA_;
output DRTRY_;
input BG1_;
input BG2_;
input DBG1_;
/* DECL: null */
AddrStatus null
(
);
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(mem)'...
Bindings: {clk=clk, TS_=TS_, TT=TT, GBL_=GBL_, AACK_=AACK_, ARTRY_=ARTRY_, DBB_=DBB_, TA_=TA_, DRTRY_=DRTRY_, BG1_=BG1_, BG2_=BG2_, DBG1_=DBG1_}
Variables: {clk=DECLARATION(clk), TS_=DECLARATION(TS_), TT=DECLARATION(TT), GBL_=DECLARATION(GBL_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), DBB_=DECLARATION(DBB_), TA_=DECLARATION(TA_), DRTRY_=DECLARATION(DRTRY_), BG1_=DECLARATION(BG1_), BG2_=DECLARATION(BG2_), DBG1_=DECLARATION(DBG1_)}
Module 'AddrStatus' cannot be found
</pre>
<p>To reproduce the bug, uncomment the <strong>runTest_PPC60X_bus_src_mem</strong> method in <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase</strong> and run it.</p> Verilog Translator - Bug #9214 (Rejected): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTes...https://forge.ispras.ru/issues/92142018-08-11T15:16:52ZSergey Smolovsmolov@ispras.ru
<pre>
Module name: cpu
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 155:17 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 157:14 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 159:16 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 161:14 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 228:37 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 229:44 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 230:36 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 233:26 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 234:33 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 235:27 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 236:34 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 321:33 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 322:33 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 323:32 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 324:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 325:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 326:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 327:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 328:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 329:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 330:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 331:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 332:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 333:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 334:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 338:39 extraneous input '&&' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 339:28 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 341:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 342:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 346:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 347:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 348:36 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 349:43 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 350:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 351:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 352:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 353:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 354:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 356:40 mismatched input '&&' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 356:46 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 359:36 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 360:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 361:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 362:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 363:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 364:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 365:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 387:47 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 388:43 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 389:46 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 390:19 extraneous input ')' expecting SEMI
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 403:51 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 404:58 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 407:44 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 408:51 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 409:45 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 410:52 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 436:14 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 643:74 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 644:46 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 645:39 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 646:45 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 647:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 648:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 649:44 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 650:42 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 651:39 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 652:48 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 653:56 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 654:41 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 655:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 656:47 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 885:6 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 906:29 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 907:32 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 908:29 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 909:29 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 909:57 mismatched input ')' expecting COLON
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 939:16 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 941:16 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 943:16 mismatched input 'wire' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 155:3 required (...)+ loop did not match anything at input 'reg'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 155:3 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR_[]' has been found: DECLARATION(BR_)
Declaration of 'BG_[]' has been found: DECLARATION(BG_)
Declaration of 'ABB_[]' has been found: DECLARATION(ABB_)
Declaration of 'ABB1_[]' has been found: DECLARATION(ABB1_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TS1_[]' has been found: DECLARATION(TS1_)
Declaration of 'AP[]' has been found: DECLARATION(AP)
Declaration of 'APE_[]' has been found: DECLARATION(APE_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'TT1[]' has been found: DECLARATION(TT1)
Declaration of 'TSIZ[]' has been found: DECLARATION(TSIZ)
Declaration of 'TBST_[]' has been found: DECLARATION(TBST_)
Declaration of 'TBST1_[]' has been found: DECLARATION(TBST1_)
Declaration of 'TC[]' has been found: DECLARATION(TC)
Declaration of 'CI_[]' has been found: DECLARATION(CI_)
Declaration of 'WT_[]' has been found: DECLARATION(WT_)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'GBL1_[]' has been found: DECLARATION(GBL1_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'ARTRY1_[]' has been found: DECLARATION(ARTRY1_)
Declaration of 'SHD_[]' has been found: DECLARATION(SHD_)
Declaration of 'DBG_[]' has been found: DECLARATION(DBG_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'DBB1_[]' has been found: DECLARATION(DBB1_)
Declaration of 'DP[]' has been found: DECLARATION(DP)
Declaration of 'DPE_[]' has been found: DECLARATION(DPE_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR_[]' has been found: DECLARATION(BR_)
Declaration of 'BG_[]' has been found: DECLARATION(BG_)
Declaration of 'ABB_[]' has been found: DECLARATION(ABB_)
Declaration of 'ABB1_[]' has been found: DECLARATION(ABB1_)
Declaration of 'TS1_[]' has been found: DECLARATION(TS1_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'AP[]' has been found: DECLARATION(AP)
Declaration of 'APE_[]' has been found: DECLARATION(APE_)
Declaration of 'TT1[]' has been found: DECLARATION(TT1)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'TSIZ[]' has been found: DECLARATION(TSIZ)
Declaration of 'TBST1_[]' has been found: DECLARATION(TBST1_)
Declaration of 'TBST_[]' has been found: DECLARATION(TBST_)
Declaration of 'TC[]' has been found: DECLARATION(TC)
Declaration of 'CI_[]' has been found: DECLARATION(CI_)
Declaration of 'WT_[]' has been found: DECLARATION(WT_)
Declaration of 'GBL1_[]' has been found: DECLARATION(GBL1_)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY1_[]' has been found: DECLARATION(ARTRY1_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'SHD_[]' has been found: DECLARATION(SHD_)
Declaration of 'DBG_[]' has been found: DECLARATION(DBG_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'DBB1_[]' has been found: DECLARATION(DBB1_)
Declaration of 'DP[]' has been found: DECLARATION(DP)
Declaration of 'DPE_[]' has been found: DECLARATION(DPE_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Starting the backend 'printer'...
module cpu(.clkclk /* DECL: clk */, .BR_BR_ /* DECL: BR_ */, .BG_BG_ /* DECL: BG_ */, .ABB_ABB_ /* DECL: ABB_ */, .ABB1_ABB1_ /* DECL: ABB1_ */, .TS_TS_ /* DECL: TS_ */, .TS1_TS1_ /* DECL: TS1_ */, .APAP /* DECL: AP */, .APE_APE_ /* DECL: APE_ */, .TTTT /* DECL: TT */, .TT1TT1 /* DECL: TT1 */, .TSIZTSIZ /* DECL: TSIZ */, .TBST_TBST_ /* DECL: TBST_ */, .TBST1_TBST1_ /* DECL: TBST1_ */, .TCTC /* DECL: TC */, .CI_CI_ /* DECL: CI_ */, .WT_WT_ /* DECL: WT_ */, .GBL_GBL_ /* DECL: GBL_ */, .GBL1_GBL1_ /* DECL: GBL1_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .ARTRY1_ARTRY1_ /* DECL: ARTRY1_ */, .SHD_SHD_ /* DECL: SHD_ */, .DBG_DBG_ /* DECL: DBG_ */, .DBB_DBB_ /* DECL: DBB_ */, .DBB1_DBB1_ /* DECL: DBB1_ */, .DPDP /* DECL: DP */, .DPE_DPE_ /* DECL: DPE_ */, .TA_TA_ /* DECL: TA_ */, .DRTRY_DRTRY_ /* DECL: DRTRY_ */, clk /* DECL: clk */, BR_ /* DECL: BR_ */, BG_ /* DECL: BG_ */, ABB_ /* DECL: ABB_ */, ABB1_ /* DECL: ABB1_ */, TS1_ /* DECL: TS1_ */, TS_ /* DECL: TS_ */, AP /* DECL: AP */, APE_ /* DECL: APE_ */, TT1 /* DECL: TT1 */, TT /* DECL: TT */, TSIZ /* DECL: TSIZ */, TBST1_ /* DECL: TBST1_ */, TBST_ /* DECL: TBST_ */, TC /* DECL: TC */, CI_ /* DECL: CI_ */, WT_ /* DECL: WT_ */, GBL1_ /* DECL: GBL1_ */, GBL_ /* DECL: GBL_ */, AACK_ /* DECL: AACK_ */, ARTRY1_ /* DECL: ARTRY1_ */, ARTRY_ /* DECL: ARTRY_ */, SHD_ /* DECL: SHD_ */, DBG_ /* DECL: DBG_ */, DBB_ /* DECL: DBB_ */, DBB1_ /* DECL: DBB1_ */, DP /* DECL: DP */, DPE_ /* DECL: DPE_ */, TA_ /* DECL: TA_ */, DRTRY_ /* DECL: DRTRY_ */);
input clk;
output BR_;
input BG_;
input ABB_;
output ABB1_;
output TS1_;
input TS_;
output [00000000000000000000000000000000:00000000000000000000000000000011] AP;
output APE_;
output [00000000000000000000000000000100:00000000000000000000000000000000] TT1;
input [00000000000000000000000000000100:00000000000000000000000000000000] TT;
output [00000000000000000000000000000010:00000000000000000000000000000000] TSIZ;
output TBST1_;
input TBST_;
output [00000000000000000000000000000000:00000000000000000000000000000010] TC;
output CI_;
output WT_;
output GBL1_;
input GBL_;
input AACK_;
output ARTRY1_;
input ARTRY_;
output SHD_;
input DBG_;
input DBB_;
output DBB1_;
output [00000000000000000000000000000000:00000000000000000000000000000111] DP;
output DPE_;
input TA_;
input DRTRY_;
/* DECL: null */
AddressTenure null
(
);
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(cpu)'...
Bindings: {clk=clk, BR_=BR_, BG_=BG_, ABB_=ABB_, ABB1_=ABB1_, TS_=TS_, TS1_=TS1_, AP=AP, APE_=APE_, TT=TT, TT1=TT1, TSIZ=TSIZ, TBST_=TBST_, TBST1_=TBST1_, TC=TC, CI_=CI_, WT_=WT_, GBL_=GBL_, GBL1_=GBL1_, AACK_=AACK_, ARTRY_=ARTRY_, ARTRY1_=ARTRY1_, SHD_=SHD_, DBG_=DBG_, DBB_=DBB_, DBB1_=DBB1_, DP=DP, DPE_=DPE_, TA_=TA_, DRTRY_=DRTRY_}
Variables: {clk=DECLARATION(clk), BR_=DECLARATION(BR_), BG_=DECLARATION(BG_), ABB_=DECLARATION(ABB_), ABB1_=DECLARATION(ABB1_), TS_=DECLARATION(TS_), TS1_=DECLARATION(TS1_), AP=DECLARATION(AP), APE_=DECLARATION(APE_), TT=DECLARATION(TT), TT1=DECLARATION(TT1), TSIZ=DECLARATION(TSIZ), TBST_=DECLARATION(TBST_), TBST1_=DECLARATION(TBST1_), TC=DECLARATION(TC), CI_=DECLARATION(CI_), WT_=DECLARATION(WT_), GBL_=DECLARATION(GBL_), GBL1_=DECLARATION(GBL1_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), ARTRY1_=DECLARATION(ARTRY1_), SHD_=DECLARATION(SHD_), DBG_=DECLARATION(DBG_), DBB_=DECLARATION(DBB_), DBB1_=DECLARATION(DBB1_), DP=DECLARATION(DP), DPE_=DECLARATION(DPE_), TA_=DECLARATION(TA_), DRTRY_=DECLARATION(DRTRY_)}
Module 'AddressTenure' cannot be found
</pre>
<p>To reproduce the bug, uncomment the <strong>runTest_PPC60X_bus_src_cpu</strong> method in <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase</strong> and run it.</p> Verilog Translator - Bug #9213 (Rejected): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTes...https://forge.ispras.ru/issues/92132018-08-11T15:14:35ZSergey Smolovsmolov@ispras.ru
<pre>
Module name: arb2
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/arbiter.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/arbiter.v line 60:15 mismatched input 'reg' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 60:1 required (...)+ loop did not match anything at input 'reg'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 60:1 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR1_[]' has been found: DECLARATION(BR1_)
Declaration of 'BR2_[]' has been found: DECLARATION(BR2_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Declaration of 'DBG2_[]' has been found: DECLARATION(DBG2_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR1_[]' has been found: DECLARATION(BR1_)
Declaration of 'BR2_[]' has been found: DECLARATION(BR2_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Declaration of 'DBG2_[]' has been found: DECLARATION(DBG2_)
Starting the backend 'printer'...
module arb2(.clkclk /* DECL: clk */, .BR1_BR1_ /* DECL: BR1_ */, .BR2_BR2_ /* DECL: BR2_ */, .BG1_BG1_ /* DECL: BG1_ */, .BG2_BG2_ /* DECL: BG2_ */, .TS_TS_ /* DECL: TS_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .DBG1_DBG1_ /* DECL: DBG1_ */, .DBG2_DBG2_ /* DECL: DBG2_ */, clk /* DECL: clk */, BR1_ /* DECL: BR1_ */, BR2_ /* DECL: BR2_ */, BG1_ /* DECL: BG1_ */, BG2_ /* DECL: BG2_ */, TS_ /* DECL: TS_ */, AACK_ /* DECL: AACK_ */, ARTRY_ /* DECL: ARTRY_ */, DBG1_ /* DECL: DBG1_ */, DBG2_ /* DECL: DBG2_ */);
input clk;
input BR1_;
input BR2_;
output BG1_;
output BG2_;
input TS_;
input AACK_;
input ARTRY_;
output DBG1_;
output DBG2_;
wire bus_request;
/* DECL: null */
ArbiterStatus null
(
);
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(arb2)'...
Bindings: {clk=clk, BR1_=BR1_, BR2_=BR2_, BG1_=BG1_, BG2_=BG2_, TS_=TS_, AACK_=AACK_, ARTRY_=ARTRY_, DBG1_=DBG1_, DBG2_=DBG2_, bus_request=bus_request}
Variables: {clk=DECLARATION(clk), BR1_=DECLARATION(BR1_), BR2_=DECLARATION(BR2_), BG1_=DECLARATION(BG1_), BG2_=DECLARATION(BG2_), TS_=DECLARATION(TS_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), DBG1_=DECLARATION(DBG1_), DBG2_=DECLARATION(DBG2_), bus_request=DECLARATION(bus_request)}
Module 'ArbiterStatus' cannot be found
</pre>
<p>To reproduce the bug, uncomment the <strong>runTest_PPC60X_bus_src_arbiter</strong> method in <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase</strong> and run it.</p> Verilog Translator - Bug #9212 (Closed): ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.r...https://forge.ispras.ru/issues/92122018-08-11T15:08:03ZSergey Smolovsmolov@ispras.ru
<p>Here is the test output:<br /><pre>
Module name: lunc
Including file '/home/ssedai/projects/veritrans/src/test/verilog/verilog2smv-vis-tests/Vlunc/vlunc.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/verilog2smv-vis-tests/Vlunc/vlunc.v line 115:31 missing COLON at '('
/home/ssedai/projects/veritrans/src/test/verilog/verilog2smv-vis-tests/Vlunc/vlunc.v line 115:36 mismatched input ':' expecting SEMI
/home/ssedai/projects/veritrans/src/test/verilog/verilog2smv-vis-tests/Vlunc/vlunc.v line 116:9 mismatched input '?' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/verilog2smv-vis-tests/Vlunc/vlunc.v line 116:23 mismatched input ':' expecting SEMI
/home/ssedai/projects/veritrans/src/test/verilog/verilog2smv-vis-tests/Vlunc/vlunc.v line 117:9 mismatched input '?' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/verilog2smv-vis-tests/Vlunc/vlunc.v line 117:14 mismatched input ':' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/verilog2smv-vis-tests/Vlunc/vlunc.v line 118:9 mismatched input '?' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/verilog2smv-vis-tests/Vlunc/vlunc.v line 118:26 mismatched input ':' expecting SEMI
/home/ssedai/projects/veritrans/src/test/verilog/verilog2smv-vis-tests/Vlunc/vlunc.v line 123:12 missing RPAREN at '('
/home/ssedai/projects/veritrans/src/test/verilog/verilog2smv-vis-tests/Vlunc/vlunc.v line 125:1 mismatched input 'else' expecting KW_END
/home/ssedai/projects/veritrans/src/test/verilog/verilog2smv-vis-tests/Vlunc/vlunc.v line 126:13 mismatched input '<=' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 99:52 mismatched tree node: <mismatched token: [@516,2641:2643='end',<50>,127:4], resync=moduletransform(in,Lcmd,Ucmd,Ncmd,Ccmd,out);input[7:0]in;inputLcmd;inputUcmd;inputNcmd;inputCcmd;output[7:0]out;assignout=Lcmd?toLower(in):Ucmd?toUpper(in):Ncmd?in:Ccmd?changeCase(in):8'hxx;function[7:0]toLower;input[7:0]in;begin:_toLowerif(isUpper(in))toLower<=in+8'h20;elsetoLower<=in;endendfunctionfunction[7:0]toUpper;input[7:0]in;begin:_toUpperif> expecting <UP>
Starting the backend 'static-checker'...
Declaration of 'regIn[]' has been found: DECLARATION(regIn)
Declaration of 'dataOut[]' has been found: DECLARATION(dataOut)
Instance: c
Module: control
Port connection: null
Port connection: set clock
Port connection: null
Port connection: set reset
Port connection: null
Port connection: set in
Port connection: null
Port connection: set Lcmd
Port connection: null
Port connection: set Ucmd
Port connection: null
Port connection: set Ncmd
Port connection: null
Port connection: set Ccmd
Declaration of 'clock[]' has been found: DECLARATION(clock)
Declaration of 'reset[]' has been found: DECLARATION(reset)
Declaration of 'regIn[]' has been found: DECLARATION(regIn)
Declaration of 'Lcmd[]' has been found: DECLARATION(Lcmd)
Declaration of 'Ucmd[]' has been found: DECLARATION(Ucmd)
Declaration of 'Ncmd[]' has been found: DECLARATION(Ncmd)
Declaration of 'Ccmd[]' has been found: DECLARATION(Ccmd)
Instance: t
Declaration of 'regIn[]' has been found: DECLARATION(regIn)
Declaration of 'Lcmd[]' has been found: DECLARATION(Lcmd)
Declaration of 'Ucmd[]' has been found: DECLARATION(Ucmd)
Declaration of 'Ncmd[]' has been found: DECLARATION(Ncmd)
Declaration of 'Ccmd[]' has been found: DECLARATION(Ccmd)
Declaration of 'transformed[]' has been found: DECLARATION(transformed)
Declaration of 'clock[]' has been found: DECLARATION(clock)
Declaration of 'reset[]' has been found: DECLARATION(reset)
Declaration of 'dataOut[]' has been found: DECLARATION(dataOut)
Declaration of 'regIn[]' has been found: DECLARATION(regIn)
Declaration of 'dataOut[]' has been found: DECLARATION(dataOut)
Declaration of 'transformed[]' has been found: DECLARATION(transformed)
Declaration of 'regIn[]' has been found: DECLARATION(regIn)
Declaration of 'dataIn[]' has been found: DECLARATION(dataIn)
Declaration of 'clock[]' has been found: DECLARATION(clock)
Declaration of 'reset[]' has been found: DECLARATION(reset)
Declaration of 'dataIn[]' has been found: DECLARATION(dataIn)
Declaration of 'dataOut[]' has been found: DECLARATION(dataOut)
Declaration of 'clock[]' has been found: DECLARATION(clock)
Declaration of 'reset[]' has been found: DECLARATION(reset)
Declaration of 'dataIn[]' has been found: DECLARATION(dataIn)
Declaration of 'dataOut[]' has been found: DECLARATION(dataOut)
Declaration of 'Lcmd[]' has been found: DECLARATION(Lcmd)
Declaration of 'Ucmd[]' has been found: DECLARATION(Ucmd)
Declaration of 'Ncmd[]' has been found: DECLARATION(Ncmd)
Declaration of 'Ccmd[]' has been found: DECLARATION(Ccmd)
Declaration of 'prev[]' has been found: DECLARATION(prev)
Declaration of 'clock[]' has been found: DECLARATION(clock)
Declaration of 'reset[]' has been found: DECLARATION(reset)
Declaration of 'prev[]' has been found: DECLARATION(prev)
Declaration of 'prev[]' has been found: DECLARATION(prev)
Declaration of 'in[]' has been found: DECLARATION(in)
Declaration of 'load[]' has been found: DECLARATION(load)
Declaration of 'prev[]' has been found: DECLARATION(prev)
Declaration of 'clock[]' has been found: DECLARATION(clock)
Declaration of 'reset[]' has been found: DECLARATION(reset)
Declaration of 'Ncmd[]' has been found: DECLARATION(Ncmd)
Declaration of 'Lcmd[]' has been found: DECLARATION(Lcmd)
Declaration of 'Ucmd[]' has been found: DECLARATION(Ucmd)
Declaration of 'Ccmd[]' has been found: DECLARATION(Ccmd)
Declaration of 'load[]' has been found: DECLARATION(load)
Declaration of 'in[]' has been found: DECLARATION(in)
Declaration of 'Lcmd[]' has been found: DECLARATION(Lcmd)
Declaration of 'Ucmd[]' has been found: DECLARATION(Ucmd)
Declaration of 'Ncmd[]' has been found: DECLARATION(Ncmd)
Declaration of 'Ccmd[]' has been found: DECLARATION(Ccmd)
Declaration of 'Lcmd[]' has been found: DECLARATION(Lcmd)
Declaration of 'Ucmd[]' has been found: DECLARATION(Ucmd)
Declaration of 'Ncmd[]' has been found: DECLARATION(Ncmd)
Declaration of 'Ccmd[]' has been found: DECLARATION(Ccmd)
Declaration of 'Lcmd[]' has been found: DECLARATION(Lcmd)
Declaration of 'Ucmd[]' has been found: DECLARATION(Ucmd)
Declaration of 'Ncmd[]' has been found: DECLARATION(Ncmd)
Declaration of 'Ccmd[]' has been found: DECLARATION(Ccmd)
Declaration of 'Lcmd[]' has been found: DECLARATION(Lcmd)
Declaration of 'Ucmd[]' has been found: DECLARATION(Ucmd)
Declaration of 'Ncmd[]' has been found: DECLARATION(Ncmd)
Declaration of 'Ccmd[]' has been found: DECLARATION(Ccmd)
Declaration of 'Lcmd[]' has been found: DECLARATION(Lcmd)
Declaration of 'Ucmd[]' has been found: DECLARATION(Ucmd)
Declaration of 'Ncmd[]' has been found: DECLARATION(Ncmd)
Declaration of 'Ccmd[]' has been found: DECLARATION(Ccmd)
Declaration of 'clock[]' has been found: DECLARATION(clock)
Declaration of 'reset[]' has been found: DECLARATION(reset)
Declaration of 'in[]' has been found: DECLARATION(in)
Declaration of 'Lcmd[]' has been found: DECLARATION(Lcmd)
Declaration of 'Ucmd[]' has been found: DECLARATION(Ucmd)
Declaration of 'Ncmd[]' has been found: DECLARATION(Ncmd)
Declaration of 'Ccmd[]' has been found: DECLARATION(Ccmd)
Declaration of 'clock[]' has been found: DECLARATION(clock)
Declaration of 'reset[]' has been found: DECLARATION(reset)
Declaration of 'in[]' has been found: DECLARATION(in)
Declaration of 'Lcmd[]' has been found: DECLARATION(Lcmd)
Declaration of 'Ucmd[]' has been found: DECLARATION(Ucmd)
Declaration of 'Ncmd[]' has been found: DECLARATION(Ncmd)
Declaration of 'Ccmd[]' has been found: DECLARATION(Ccmd)
Starting the backend 'printer'...
module lunc(clock /* DECL: clock */, reset /* DECL: reset */, dataIn /* DECL: dataIn */, dataOut /* DECL: dataOut */, clock /* DECL: clock */, reset /* DECL: reset */, dataIn /* DECL: dataIn */, dataOut /* DECL: dataOut */);
input clock;
inout reset;
input [00000000000000000000000000000111:00000000000000000000000000000000] dataIn;
output [00000000000000000000000000000111:00000000000000000000000000000000] dataOut;
reg [00000000000000000000000000000111:00000000000000000000000000000000] dataOut;
reg [00000000000000000000000000000111:00000000000000000000000000000000] regIn;
wire [00000000000000000000000000000111:00000000000000000000000000000000] transformed;
wire Lcmd;
wire Ucmd;
wire Ncmd;
wire Ccmd;
initial
begin
regIn /* DECL: regIn */ = 00000000000000000000000000000000;
dataOut /* DECL: dataOut */ = 00000000000000000000000000000000;
end
/* DECL: control */
control c
(
.clock(clock)
.reset(reset)
.in(regIn)
.Lcmd(Lcmd)
.Ucmd(Ucmd)
.Ncmd(Ncmd)
.Ccmd(Ccmd)
);
/* DECL: null */
transform t
(
regIn
Lcmd
Ucmd
Ncmd
Ccmd
transformed
);
always
@(posedge clock)
begin
if(reset)
/* ASSERT: reset */
begin
dataOut /* DECL: dataOut */ <= 00000000000000000000000000000000;
regIn /* DECL: regIn */ <= 00000000000000000000000000000000;
end
else
/* ASSERT: ! reset */
begin
dataOut /* DECL: dataOut */ <= transformed;
regIn /* DECL: regIn */ <= dataIn;
end
end
end
endmodule
module control(clock /* DECL: clock */, reset /* DECL: reset */, in /* DECL: in */, Lcmd /* DECL: Lcmd */, Ucmd /* DECL: Ucmd */, Ncmd /* DECL: Ncmd */, Ccmd /* DECL: Ccmd */, clock /* DECL: clock */, reset /* DECL: reset */, in /* DECL: in */, Lcmd /* DECL: Lcmd */, Ucmd /* DECL: Ucmd */, Ncmd /* DECL: Ncmd */, Ccmd /* DECL: Ccmd */);
input clock;
input reset;
input [00000000000000000000000000000111:00000000000000000000000000000000] in;
output reg Lcmd;
output reg Ucmd;
output reg Ncmd;
output reg Ccmd;
reg Lcmd;
reg Ucmd;
reg Ncmd;
reg Ccmd;
wire load;
reg [00000000000000000000000000000111:00000000000000000000000000000000] prev;
initial
begin
Lcmd /* DECL: Lcmd */ = 00000000000000000000000000000000;
Ucmd /* DECL: Ucmd */ = 00000000000000000000000000000000;
Ncmd /* DECL: Ncmd */ = 00000000000000000000000000000001;
Ccmd /* DECL: Ccmd */ = 00000000000000000000000000000000;
prev /* DECL: prev */ = 00000000000000000000000000000000;
end
always
@(posedge clock)
if(reset)
/* ASSERT: reset */
prev /* DECL: prev */ <= 00000000000000000000000000000000;
else
/* ASSERT: ! reset */
prev /* DECL: prev */ <= in;
end
assign load /* DECL: load */ = (prev == 00011011);
always
@(posedge clock)
if(reset)
/* ASSERT: reset */
begin
Ncmd /* DECL: Ncmd */ <= 00000000000000000000000000000001;
Lcmd /* DECL: Lcmd */ <= 00000000000000000000000000000000;
Ucmd /* DECL: Ucmd */ <= 00000000000000000000000000000000;
Ccmd /* DECL: Ccmd */ <= 00000000000000000000000000000000;
end
else
/* ASSERT: ! reset */
if(load)
/* ASSERT: load */
begin
case(in)
01001100:
/* ASSERT: (in === 01001100) */
begin
Lcmd /* DECL: Lcmd */ <= 00000000000000000000000000000001;
Ucmd /* DECL: Ucmd */ <= 00000000000000000000000000000000;
Ncmd /* DECL: Ncmd */ <= 00000000000000000000000000000000;
Ccmd /* DECL: Ccmd */ <= 00000000000000000000000000000000;
end
01010101:
/* ASSERT: (in === 01010101) */
begin
Lcmd /* DECL: Lcmd */ <= 00000000000000000000000000000000;
Ucmd /* DECL: Ucmd */ <= 00000000000000000000000000000001;
Ncmd /* DECL: Ncmd */ <= 00000000000000000000000000000000;
Ccmd /* DECL: Ccmd */ <= 00000000000000000000000000000000;
end
01001110:
/* ASSERT: (in === 01001110) */
begin
Lcmd /* DECL: Lcmd */ <= 00000000000000000000000000000000;
Ucmd /* DECL: Ucmd */ <= 00000000000000000000000000000000;
Ncmd /* DECL: Ncmd */ <= 00000000000000000000000000000001;
Ccmd /* DECL: Ccmd */ <= 00000000000000000000000000000000;
end
01000011:
/* ASSERT: (in === 01000011) */
begin
Lcmd /* DECL: Lcmd */ <= 00000000000000000000000000000000;
Ucmd /* DECL: Ucmd */ <= 00000000000000000000000000000000;
Ncmd /* DECL: Ncmd */ <= 00000000000000000000000000000000;
Ccmd /* DECL: Ccmd */ <= 00000000000000000000000000000001;
end
default:
/* ASSERT: ! ((((in === 01001100) || (in === 01010101)) || (in === 01001110)) || (in === 01000011)) */
begin
Lcmd /* DECL: Lcmd */ <= 0;
Ucmd /* DECL: Ucmd */ <= 0;
Ncmd /* DECL: Ncmd */ <= 0;
Ccmd /* DECL: Ccmd */ <= 0;
end
end
end
else
/* ASSERT: ! load */
begin
end
end
end
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(lunc)'...
Bindings: {clock=clock, reset=reset, dataIn=dataIn, dataOut=dataOut, regIn=regIn, transformed=transformed, Lcmd=Lcmd, Ucmd=Ucmd, Ncmd=Ncmd, Ccmd=Ccmd}
Variables: {clock=DECLARATION(clock), reset=DECLARATION(reset), dataIn=DECLARATION(dataIn), dataOut=DECLARATION(dataOut), regIn=DECLARATION(regIn), transformed=DECLARATION(transformed), Lcmd=DECLARATION(Lcmd), Ucmd=DECLARATION(Ucmd), Ncmd=DECLARATION(Ncmd), Ccmd=DECLARATION(Ccmd)}
Module 'transform' cannot be found
</pre><br />To reproduce the bug, uncomment the <strong>runTest_Vlunc_vlunc</strong> method in <strong>ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase</strong></p> Verilog Translator - Bug #9211 (Closed): java.lang.IllegalArgumentException at ru.ispras.verilog....https://forge.ispras.ru/issues/92112018-08-11T15:04:26ZSergey Smolovsmolov@ispras.ru
<pre>
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:95)
at ru.ispras.verilog.parser.model.basis.VerilogPathItem.<init>(VerilogPathItem.java:41)
at ru.ispras.verilog.parser.model.VerilogModule.addDeclaration(VerilogModule.java:193)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_module(VerilogTreeBuilder.java:674)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:509)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:459)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:251)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:256)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:271)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:275)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:162)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:64)
at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:50)
</pre>
<p>To reproduce the bug, run any of the following test cases:<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_Mux<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_Add4<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_Mux<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_ThreeBitReg<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_OneBitReg<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_DataMem<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_DataMem<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_Clock<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_ZTest<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_Clock<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_ZTest<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_SignExt<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_InstMem<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_SignExt<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_Add4<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_Register<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_RegFile<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_RegFile<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_OneBitReg<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_PDLX_misc_FiveBitReg<br /> ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_DLX_SDLX_misc_Register</p>