Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692020-01-30T19:03:30ZOpen-Source Projects
Redmine Retrascope - Bug #10082 (New): WARNING: Illegal reflective access by org.python.core.PySystemStatehttps://forge.ispras.ru/issues/100822020-01-30T19:03:30ZSergey Smolovsmolov@ispras.ru
<pre>
WARNING: An illegal reflective access operation has occurred
WARNING: Illegal reflective access by org.python.core.PySystemState (file:/home/ssedai/projects/retrascope/build/distributions/retrascope-1.1.3-beta-SNAPSHOT/lib/jython-standalone-2.7.1.jar) to method java.io.Console.encoding()
WARNING: Please consider reporting this to the maintainers of org.python.core.PySystemState
WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations
WARNING: All illegal access operations will be denied in a future release
</pre> MicroTESK - Bug #10069 (New): cpu.nml Error: Internal error: context [/Isa] 1:8 attribute file is...https://forge.ispras.ru/issues/100692020-01-24T12:11:55ZSergey Smolovsmolov@ispras.ru
<p>Upon building, the following error appears in Gradle log:<br /><pre>
> Task :translateCpu
Translating: src/main/arch/demo/cpu/model/cpu.nml
Model name: cpu
Included: src/main/arch/demo/cpu/model/cpu.nml
Error: Internal error: context [/Isa] 1:8 attribute file isn't defined
</pre></p> MicroTESK for PowerPC - Bug #10031 (New): WARNING: An illegal reflective access operation has occ...https://forge.ispras.ru/issues/100312020-01-13T11:54:41ZSergey Smolovsmolov@ispras.ru
<p>The following warnings appear in test log:<br /><pre><code class="text syntaxhl" data-language="text">WARNING: An illegal reflective access operation has occurred
WARNING: Illegal reflective access by org.jruby.util.io.ChannelDescriptor (file:/home/ssedai/projects/microtesk-powerpc/build/target/lib/jars/jruby-complete-1.7.25.jar) to method sun.nio.ch.SelChImpl.getFD()
WARNING: Please consider reporting this to the maintainers of org.jruby.util.io.ChannelDescriptor
WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations
WARNING: All illegal access operations will be denied in a future release
</code></pre></p>
<p>OpenJDK 11 is used.</p> Verilog Translator - Bug #9993 (New): if two modules are passed to the tool and one includes anot...https://forge.ispras.ru/issues/99932019-12-18T12:43:15ZSergey Smolovsmolov@ispras.ru
<p>Suppose there are two files with Verilog modules: <em>a.v</em> and <em>b.v</em> (<em>a.v</em> contains "a" module, b.v contains "b" module). Module "a" includes module "b".</p>
<p>When the following args are used for the tool:<br /><pre>
a.v b.v --include-path /path/to/b/file --module-name a
</pre><br />the tool hangs. These arguments seem to be strange, because "b" module appears two times in the command line.<br />More adequate diagnostics should be shown here, and, of course, no freezes.</p> Verilog Translator - Bug #9902 (New): java.lang.IllegalArgumentException: Descriptor for '<var na...https://forge.ispras.ru/issues/99022019-11-01T16:20:57ZSergey Smolovsmolov@ispras.ru
<p>When running the tool on the <a href="https://github.com/ispras/hdl-benchmarks/blob/master/hdl/iwls05/faraday/rtl/DMA/hdl/dma_chsel.v" class="external">dma_chsel.v</a> and <a href="https://github.com/ispras/hdl-benchmarks/blob/master/hdl/iwls05/faraday/rtl/DMA/hdl/dma_rrarb.v" class="external">dma_rrarb.v</a> modules the following error log appears:<br /><pre>
ru.ispras.verilog.parser.VerilogIwlsTestCase > runTest_dma_chsel STANDARD_ERROR
java.lang.IllegalArgumentException: Descriptor for 'dma_chsel.arb_chcsr_reg' has not been found: {dma_chsel.HCLK=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.HRSTn=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.dma_req=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.dma_ack=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.dma_tc=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.csr=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.sync=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.de_err_notify=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c0csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c0abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c0llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c1csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c1abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c1llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c2csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c2abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c2llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c3csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c3abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c3llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c4csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c4abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c4llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c5csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c5abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c5llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c6csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c6abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c6llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c7csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c7abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c7llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.arb_ch_sel=(BIT_VECTOR 3):(SHIFT 0)}
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:109)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute$1.apply(VerilogTransformerVariableSubstitute.java:121)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:169)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:229)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:213)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute.shiftRanges(VerilogTransformerVariableSubstitute.java:95)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute.transform(VerilogTransformerVariableSubstitute.java:142)
at ru.ispras.verilog.parser.transformer.VerilogTransformerComposite.transform(VerilogTransformerComposite.java:57)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:177)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:189)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.onDeclarationBegin(VerilogTransformer.java:67)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$13.onBegin(VerilogNodeVisitor.java:385)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:81)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.run(VerilogTransformer.java:52)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiate(VerilogInstantiator.java:145)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateDescriptor(VerilogInstantiator.java:124)
at ru.ispras.verilog.parser.elaborator.VerilogDesign$Builder.build(VerilogDesign.java:102)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:246)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:187)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:111)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:71)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:45)
at ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_dma_chsel(VerilogIwlsTestCase.java:51)
</pre></p>
<p>To reproduce the bug, run <strong>ru.ispras.verilog.parser.VerilogIwlsTestCase#runTest_dma_chsel</strong> test from <em>Retrascope Test Suite</em> project.</p> Retrascope Test Suite - Bug #9901 (New): initializationError in some tests after Jenkins updatehttps://forge.ispras.ru/issues/99012019-11-01T08:32:54ZSergey Smolovsmolov@ispras.ru
<p>JDK 11 is used by Jenkins now. It could be the cause of several JUnit test cases falling. Here is an example log:<br /><pre>
java.lang.Exception: The inner class ru.ispras.retrascope.engine.hldd.printer.smv.formula.sample.vcegar.VcegarPjIcram1SmvFormulaPrinterTestCase$TestCase is not static.
at org.junit.runners.BlockJUnit4ClassRunner.validateNoNonStaticInnerClass(BlockJUnit4ClassRunner.java:113)
at org.junit.runners.BlockJUnit4ClassRunner.collectInitializationErrors(BlockJUnit4ClassRunner.java:102)
at org.junit.runners.ParentRunner.validate(ParentRunner.java:355)
at org.junit.runners.ParentRunner.<init>(ParentRunner.java:76)
at org.junit.runners.BlockJUnit4ClassRunner.<init>(BlockJUnit4ClassRunner.java:57)
at org.junit.internal.builders.JUnit4Builder.runnerForClass(JUnit4Builder.java:10)
at org.junit.runners.model.RunnerBuilder.safeRunnerForClass(RunnerBuilder.java:59)
at org.junit.internal.builders.AllDefaultPossibilitiesBuilder.runnerForClass(AllDefaultPossibilitiesBuilder.java:26)
at org.junit.runners.model.RunnerBuilder.safeRunnerForClass(RunnerBuilder.java:59)
at org.junit.internal.requests.ClassRequest.getRunner(ClassRequest.java:26)
at org.gradle.api.internal.tasks.testing.junit.JUnitTestClassExecutor.runTestClass(JUnitTestClassExecutor.java:78)
at org.gradle.api.internal.tasks.testing.junit.JUnitTestClassExecutor.execute(JUnitTestClassExecutor.java:58)
at org.gradle.api.internal.tasks.testing.junit.JUnitTestClassExecutor.execute(JUnitTestClassExecutor.java:38)
at org.gradle.api.internal.tasks.testing.junit.AbstractJUnitTestClassProcessor.processTestClass(AbstractJUnitTestClassProcessor.java:66)
at org.gradle.api.internal.tasks.testing.SuiteTestClassProcessor.processTestClass(SuiteTestClassProcessor.java:51)
at jdk.internal.reflect.GeneratedMethodAccessor2.invoke(Unknown Source)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:566)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:35)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:24)
at org.gradle.internal.dispatch.ContextClassLoaderDispatch.dispatch(ContextClassLoaderDispatch.java:32)
at org.gradle.internal.dispatch.ProxyDispatchAdapter$DispatchingInvocationHandler.invoke(ProxyDispatchAdapter.java:93)
at com.sun.proxy.$Proxy5.processTestClass(Unknown Source)
at org.gradle.api.internal.tasks.testing.worker.TestWorker.processTestClass(TestWorker.java:117)
at jdk.internal.reflect.GeneratedMethodAccessor1.invoke(Unknown Source)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:566)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:35)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:24)
at org.gradle.internal.remote.internal.hub.MessageHubBackedObjectConnection$DispatchWrapper.dispatch(MessageHubBackedObjectConnection.java:155)
at org.gradle.internal.remote.internal.hub.MessageHubBackedObjectConnection$DispatchWrapper.dispatch(MessageHubBackedObjectConnection.java:137)
at org.gradle.internal.remote.internal.hub.MessageHub$Handler.run(MessageHub.java:404)
at org.gradle.internal.concurrent.ExecutorPolicy$CatchAndRecordFailures.onExecute(ExecutorPolicy.java:63)
at org.gradle.internal.concurrent.ManagedExecutorImpl$1.run(ManagedExecutorImpl.java:46)
at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
at org.gradle.internal.concurrent.ThreadFactoryImpl$ManagedThreadRunnable.run(ThreadFactoryImpl.java:55)
at java.base/java.lang.Thread.run(Thread.java:834)
</pre></p> Retrascope IDE - Bug #9816 (New): Retrascope IDE does not appear in "Installed Software" menuhttps://forge.ispras.ru/issues/98162019-09-09T09:08:34ZSergey Smolovsmolov@ispras.ru
<p>The plugin does not appear in Help->About Eclipse IDE->Installed Software menu</p> Retrascope RISC-V Benchmark - Bug #9478 (New): ERROR: retrascope-riscv\src\main\verilog\rocket-ch...https://forge.ispras.ru/issues/94782019-02-06T10:20:27ZSergey Smolovsmolov@ispras.ru
<p>The <strong>ru.ispras.verilog.parser.sample.RocketChipTestDriverVerilogPrinterTestCase</strong> test case falls with the following error:<br /><pre>
ERROR: L:\work\retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:6 mismatched input 'unsigned' expecting LPAREN
ERROR: L:\work\retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 31:4 missing KW_BEGIN at 'void'
ERROR: [Internal] null
</pre><br />The related Verilog code is as follows:<br /><pre><code class="text syntaxhl" data-language="text">int unsigned rand_value;
</code></pre></p> Retrascope RISC-V Benchmark - Bug #9477 (New): an "import "DPI-C" function" construction causes V...https://forge.ispras.ru/issues/94772019-02-06T08:47:58ZSergey Smolovsmolov@ispras.ru
<p>The <strong>ru.ispras.verilog.parser.sample.RocketChipSimJtagVerilogPrinterTestCase</strong> test case runs Verilog Translator on <strong>SimJTAG.v</strong> module, that contains the following code:<br /><pre><code class="text syntaxhl" data-language="text">import "DPI-C" function int jtag_tick
(
output bit jtag_TCK,
output bit jtag_TMS,
output bit jtag_TDI,
output bit jtag_TRSTn,
input bit jtag_TDO
);
module SimJTAG #(
parameter TICK_DELAY = 50
)(
input clock,
input reset,
...
</code></pre></p>
<p>The "import function" construction causes the following error:<br /><pre>
ERROR: ..\retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\SimJTAG.v line 3:0 mismatched input 'import' expecting EOF
ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from line 0:0 mismatched tree node: <mismatched token: [@0,71:76='import',<35>,3:0], resync=import"DPI-C"functionintjtag_tick(outputbitjtag_TCK,outputbitjtag_TMS,outputbitjtag_TDI,outputbitjtag_TRSTn,inputbitjtag_TDO);moduleSimJTAG#(parameterTICK_DELAY=50)(inputclock,inputreset,inputenable,inputinit_done,outputjtag_TCK,outputjtag_TMS,outputjtag_TDI,outputjtag_TRSTn,inputjtag_TDO_data,inputjtag_TDO_driven,output[31:0]exit);reg[31:0]tickCounterReg;wire[31:0]tickCounterNxt;assigntickCounterNxt=(tickCounterReg==0)?TICK_DELAY:(tickCounterReg-1);bitr_reset;wire[31:0]random_bits=$random;wire#0.1__jtag_TDO=jtag_TDO_driven?jtag_TDO_data:random_bits[0];bit__jtag_TCK;bit__jtag_TMS;bit__jtag_TDI;bit__jtag_TRSTn;int__exit;reginit_done_sticky;assign#0.1jtag_TCK=__jtag_TCK;assign#0.1jtag_TMS=__jtag_TMS;assign#0.1jtag_TDI=__jtag_TDI;assign#0.1jtag_TRSTn=__jtag_TRSTn;assign#0.1exit=__exit;always@(posedgeclock)beginr_reset<=reset;if(reset||r_reset)begin__exit=0;tickCounterReg<=TICK_DELAY;init_done_sticky<=1'b0;__jtag_TCK=!__jtag_TCK;endelsebegininit_done_sticky<=init_done|init_done_sticky;if(enable&&init_done_sticky)begintickCounterReg<=tickCounterNxt;if(tickCounterReg==0)begin__exit=jtag_tick(__jtag_TCK,__jtag_TMS,__jtag_TDI,__jtag_TRSTn,__jtag_TDO);endendendendendmodule> expecting AST_ROOT
ERROR: Module 'SimJTAG' has not been found
</pre></p>
<p>The same error appears at the following test cases:<br />ru.ispras.verilog.parser.sample.RocketChipSimDtmVerilogPrinterTestCase</p> MicroTESK for MIPS - Bug #9377 (New): 'Failed to construct decoder' warnings in project's build loghttps://forge.ispras.ru/issues/93772018-11-08T11:34:41ZSergey Smolovsmolov@ispras.ru
<pre>
Warning: Failed to construct decoder for mfc0. Unrecognized field: rd.r
Warning: Failed to construct decoder for mfc0. Unrecognized field: rd.s
Warning: Failed to construct decoder for mfc0. Undecoded arguments: [rd]
Warning: Failed to construct decoder for mtc0. Unrecognized field: rd.r
Warning: Failed to construct decoder for mtc0. Unrecognized field: rd.s
Warning: Failed to construct decoder for mtc0. Undecoded arguments: [rd]
Warning: Failed to construct decoder for ext. Unrecognized field: (BVSUB size 00001)
Warning: Failed to construct decoder for ext. Undecoded arguments: [size]
Warning: Failed to construct decoder for ins. Unrecognized field: (BVSUB (BVADD pos size) 00001)
Warning: Failed to construct decoder for ins. Undecoded arguments: [size]
Warning: Failed to construct decoder for dins. Unrecognized field: (BVSUB (BVADD pos size) 00001)
Warning: Failed to construct decoder for dins. Undecoded arguments: [size]
Warning: Failed to construct decoder for dinsm. Unrecognized field: (BVEXTRACT 4 0 (BVSUB (BVADD (BVZEROEXT 1 pos) size) 100001))
Warning: Failed to construct decoder for dinsm. Undecoded arguments: [size]
Warning: Failed to construct decoder for dinsu. Unrecognized field: (BVEXTRACT 4 0 (BVSUB (BVADD pos (BVZEROEXT 1 size)) 100001))
Warning: Failed to construct decoder for dinsu. Unrecognized field: (BVEXTRACT 4 0 (BVSUB pos 100000))
Warning: Failed to construct decoder for dinsu. Undecoded arguments: [pos, size]
</pre> MicroTESK for MIPS - Bug #9376 (New): Warning: Group MIPS64FpuOp contains two items add_fmt and m...https://forge.ispras.ru/issues/93762018-11-08T11:33:31ZSergey Smolovsmolov@ispras.ru
<p>The warning above appears upon project building. To reproduce it, run './gradlew assemble' in Unix-like OS or 'gradlew.bat assemble' in Windows OS.</p> Veritool - Bug #9184 (New): ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veri...https://forge.ispras.ru/issues/91842018-08-01T13:04:10ZSergey Smolovsmolov@ispras.ru
<p>Running the tool on the attached Verilog module with such parameters, as '--c --module=blocks --clk=clk --rst=rst --all blocks.v', causes the following error trace:<br /><pre>
ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veritool.conf
: error: target_design entry point is missing.
error: Code generator failure: -2
veritool failed
</pre></p> Local Support Project - Bug #6394 (New): Проект HDL Retrascope: на 17-дюймовом мониторе не масшта...https://forge.ispras.ru/issues/63942015-11-04T08:18:33ZSergey Smolovsmolov@ispras.ru
<p>В проекте HDL Retrascope при заходе через браузеры Firefox, Opera, IE не масштабируется таблица Задачи.<br />В других проектах на том же мониторе такая проблема не наблюдается.</p> Retrascope IDE - Bug #5547 (New): save Retrascope result not to ECLIPSE_HOME folderhttps://forge.ispras.ru/issues/55472015-01-05T19:24:18ZSergey Smolovsmolov@ispras.ru
<p>While using Retrascope IDE Configurator menu, engines that generate output file can be selected (like test-xml-printer, which generates test.xml file by default).<br />But if the full path to the output file is not specified, the Retrascope IDE saves output file to the ECLIPSE_HOME folder. Which causes an error, for example, in Windows 7 OS, where Eclipse IDE can be installed to the protected-for-writing folder like C:\Program Files.</p> CTESK - Bug #2494 (New): warning at build loghttps://forge.ispras.ru/issues/24942012-02-24T06:40:28ZSergey Smolovsmolov@ispras.ru
<p>При сборке возникает следующее предупреждение:</p>
<p>gcc -I. -g -ggdb -O0 -fno-inline -D_GLIBCXX_DEBUG -O -DATL_CLONE_DISABLE -DUSE_FOPEN64 -c c_tracer/c_tracer.c -o c_tracer/c_tracer.o<br />c_tracer/c_tracer.c: In function ‘addTraceToFile’:<br />c_tracer/c_tracer.c:117:7: warning: assignment makes pointer from integer without a cast</p>
<p>Сборка завершается корректно, так что это скорее небольшой досадный недочет.</p>