Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692020-04-08T09:12:41ZOpen-Source Projects
Redmine Verilog Translator - Bug #10237 (Closed): ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTes...https://forge.ispras.ru/issues/102372020-04-08T09:12:41ZSergey Smolovsmolov@ispras.ru
<p>The tool reports about cycle inclusion, but the described file does not contain includes at all.<br />Run <strong>ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2</strong> to reproduce it.</p> Verilog Translator - Bug #10216 (Closed): ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_n...https://forge.ispras.ru/issues/102162020-04-06T09:43:30ZSergey Smolovsmolov@ispras.ru
<pre>
ERROR: [Internal] null
java.lang.NullPointerException
at ru.ispras.verilog.parser.backends.syntax.checker.VerilogStaticChecker.onDefineParameterBegin(VerilogStaticChecker.java:388)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$14.onBegin(VerilogNodeVisitor.java:417)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:770)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:87)
at ru.ispras.verilog.parser.VerilogSyntaxBackend.start(VerilogSyntaxBackend.java:80)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:212)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogQuipTestSuite.runTest_nut_001(VerilogQuipTestSuite.java:345)
</pre> Retrascope - Bug #10174 (Closed): nondeterminism at EFSM transitions generationhttps://forge.ispras.ru/issues/101742020-03-18T15:26:22ZSergey Smolovsmolov@ispras.ru
<p>Fluctuations appear at EFSM transition number:<br /><pre>
java.lang.AssertionError: [b05]: 'engine=gadd-efsm-transformer modules=B05 states=313 transitions=482 efsms=3' should end with 'states=313 transitions=480 efsms=3'
at org.junit.Assert.fail(Assert.java:88)
at org.junit.Assert.assertTrue(Assert.java:41)
at ru.ispras.retrascope.engine.gadd.transformer.efsm.VhdlGaddEfsmBenchTest.runTest(VhdlGaddEfsmBenchTest.java:129)
at ru.ispras.retrascope.engine.gadd.transformer.efsm.VhdlGaddEfsmBenchTest.runTest(VhdlGaddEfsmBenchTest.java:55)
at ru.ispras.retrascope.engine.gadd.transformer.efsm.VhdlGaddEfsmTestSuite.runTest_b05(VhdlGaddEfsmTestSuite.java:92)
</pre></p> Verilog Translator - Bug #10173 (Closed): javadoc: DefineStructure.java:37: warning: no @returnhttps://forge.ispras.ru/issues/101732020-03-18T14:25:02ZSergey Smolovsmolov@ispras.ru
<pre>
> Task :javadoc
D:\Sergey\projects\veritrans\src\main\java\ru\ispras\verilog\parser\util\DefineStructure.java:37: warning: no @return
public String getString(List<String> params) {
^
1 warning
</pre> MicroTESK - Bug #10102 (Closed): incorrect ld scripts for x86 test programshttps://forge.ispras.ru/issues/101022020-02-06T10:22:06ZSergey Smolovsmolov@ispras.ru
<p>For x86 test programs emulation on QEMU4V, the following approach can be used. Test program should be compiled as <em>bootable drive</em> and run on QEMU4V ("-hda" option). The following linker script should be generated:<br /><pre>
SECTIONS
{
/* The BIOS loads the code from the disk to this location.
* We must tell that to the linker so that it can properly
* calculate the addresses of symbols we might jump to.
*/
. = 0x7c00;
.text :
{
__start = .;
*(.text)
/* Place the magic boot bytes at the end of the first 512 sector of the disk. */
. = 0x1FE;
SHORT(0xAA55)
}
}
</pre></p>
<p>Now ld scripts look as follows:<br /><pre>
ENTRY(_start)
SECTIONS
{
. = 0x7C00;
.text : { *(".text")}
. = 0x8000;
.data : { *(".data")}
.bss : { *(".bss COMMON")}
. = ALIGN(8);
. = . + 0x10000;
stack_top = .;
}
</pre></p> Retrascope - Bug #10081 (Closed): tool hangs right after final "Duration: " msghttps://forge.ispras.ru/issues/100812020-01-29T13:57:36ZSergey Smolovsmolov@ispras.ru
<p>It was ok at 1.0.1 but appear at 1.1.1</p> Retrascope - Bug #10023 (Closed): ru.ispras.retrascope.parser.verilog.VerilogParserTestCase: java...https://forge.ispras.ru/issues/100232020-01-07T12:37:30ZSergey Smolovsmolov@ispras.ru
<pre>
java.lang.Exception: Method runTest should have no parameters
at org.junit.runners.model.FrameworkMethod.validatePublicVoidNoArg(FrameworkMethod.java:76)
at org.junit.runners.ParentRunner.validatePublicVoidNoArgMethods(ParentRunner.java:155)
at org.junit.runners.BlockJUnit4ClassRunner.validateTestMethods(BlockJUnit4ClassRunner.java:208)
at org.junit.runners.BlockJUnit4ClassRunner.validateInstanceMethods(BlockJUnit4ClassRunner.java:188)
at org.junit.runners.BlockJUnit4ClassRunner.collectInitializationErrors(BlockJUnit4ClassRunner.java:128)
at org.junit.runners.ParentRunner.validate(ParentRunner.java:416)
at org.junit.runners.ParentRunner.<init>(ParentRunner.java:84)
at org.junit.runners.BlockJUnit4ClassRunner.<init>(BlockJUnit4ClassRunner.java:65)
at org.junit.internal.builders.JUnit4Builder.runnerForClass(JUnit4Builder.java:10)
at org.junit.vintage.engine.discovery.DefensiveAllDefaultPossibilitiesBuilder$DefensiveJUnit4Builder.runnerForClass(DefensiveAllDefaultPossibilitiesBuilder.java:128)
at org.junit.runners.model.RunnerBuilder.safeRunnerForClass(RunnerBuilder.java:59)
at org.junit.internal.builders.AllDefaultPossibilitiesBuilder.runnerForClass(AllDefaultPossibilitiesBuilder.java:26)
at org.junit.vintage.engine.discovery.DefensiveAllDefaultPossibilitiesBuilder.runnerForClass(DefensiveAllDefaultPossibilitiesBuilder.java:56)
at org.junit.runners.model.RunnerBuilder.safeRunnerForClass(RunnerBuilder.java:59)
at org.junit.vintage.engine.discovery.TestClassRequestResolver.createRunnerTestDescriptor(TestClassRequestResolver.java:55)
at org.junit.vintage.engine.discovery.VintageDiscoverer.lambda$discover$0(VintageDiscoverer.java:53)
at java.base/java.util.stream.ReferencePipeline$3$1.accept(ReferencePipeline.java:195)
at java.base/java.util.stream.ReferencePipeline$3$1.accept(ReferencePipeline.java:195)
at java.base/java.util.Iterator.forEachRemaining(Iterator.java:133)
at java.base/java.util.Spliterators$IteratorSpliterator.forEachRemaining(Spliterators.java:1801)
at java.base/java.util.stream.AbstractPipeline.copyInto(AbstractPipeline.java:484)
at java.base/java.util.stream.AbstractPipeline.wrapAndCopyInto(AbstractPipeline.java:474)
at java.base/java.util.stream.StreamSpliterators$WrappingSpliterator.forEachRemaining(StreamSpliterators.java:312)
at java.base/java.util.stream.Streams$ConcatSpliterator.forEachRemaining(Streams.java:734)
at java.base/java.util.stream.AbstractPipeline.copyInto(AbstractPipeline.java:484)
at java.base/java.util.stream.AbstractPipeline.wrapAndCopyInto(AbstractPipeline.java:474)
at java.base/java.util.stream.ForEachOps$ForEachOp.evaluateSequential(ForEachOps.java:150)
at java.base/java.util.stream.ForEachOps$ForEachOp$OfRef.evaluateSequential(ForEachOps.java:173)
at java.base/java.util.stream.AbstractPipeline.evaluate(AbstractPipeline.java:234)
at java.base/java.util.stream.ReferencePipeline.forEach(ReferencePipeline.java:497)
at org.junit.vintage.engine.discovery.VintageDiscoverer.discover(VintageDiscoverer.java:55)
at org.junit.vintage.engine.VintageTestEngine.discover(VintageTestEngine.java:62)
at org.junit.platform.launcher.core.DefaultLauncher.discoverEngineRoot(DefaultLauncher.java:130)
at org.junit.platform.launcher.core.DefaultLauncher.discoverRoot(DefaultLauncher.java:117)
at org.junit.platform.launcher.core.DefaultLauncher.execute(DefaultLauncher.java:90)
at org.gradle.api.internal.tasks.testing.junitplatform.JUnitPlatformTestClassProcessor$CollectAllTestClassesExecutor.processAllTestClasses(JUnitPlatformTestClassProcessor.java:92)
at org.gradle.api.internal.tasks.testing.junitplatform.JUnitPlatformTestClassProcessor$CollectAllTestClassesExecutor.access$100(JUnitPlatformTestClassProcessor.java:77)
at org.gradle.api.internal.tasks.testing.junitplatform.JUnitPlatformTestClassProcessor.stop(JUnitPlatformTestClassProcessor.java:73)
at org.gradle.api.internal.tasks.testing.SuiteTestClassProcessor.stop(SuiteTestClassProcessor.java:61)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:566)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:35)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:24)
at org.gradle.internal.dispatch.ContextClassLoaderDispatch.dispatch(ContextClassLoaderDispatch.java:32)
at org.gradle.internal.dispatch.ProxyDispatchAdapter$DispatchingInvocationHandler.invoke(ProxyDispatchAdapter.java:93)
at com.sun.proxy.$Proxy5.stop(Unknown Source)
at org.gradle.api.internal.tasks.testing.worker.TestWorker.stop(TestWorker.java:131)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:566)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:35)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:24)
at org.gradle.internal.remote.internal.hub.MessageHubBackedObjectConnection$DispatchWrapper.dispatch(MessageHubBackedObjectConnection.java:155)
at org.gradle.internal.remote.internal.hub.MessageHubBackedObjectConnection$DispatchWrapper.dispatch(MessageHubBackedObjectConnection.java:137)
at org.gradle.internal.remote.internal.hub.MessageHub$Handler.run(MessageHub.java:404)
at org.gradle.internal.concurrent.ExecutorPolicy$CatchAndRecordFailures.onExecute(ExecutorPolicy.java:63)
at org.gradle.internal.concurrent.ManagedExecutorImpl$1.run(ManagedExecutorImpl.java:46)
at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
at org.gradle.internal.concurrent.ThreadFactoryImpl$ManagedThreadRunnable.run(ThreadFactoryImpl.java:55)
at java.base/java.lang.Thread.run(Thread.java:834)
</pre>
<p>To reproduce the bug run the <strong>ru.ispras.retrascope.parser.verilog.VerilogParserTestCase</strong>. To see the described behavior, see last test results at <strong>Retrascope_Weekly_Build</strong> Jenkins item.</p> Verilog Translator - Bug #9993 (New): if two modules are passed to the tool and one includes anot...https://forge.ispras.ru/issues/99932019-12-18T12:43:15ZSergey Smolovsmolov@ispras.ru
<p>Suppose there are two files with Verilog modules: <em>a.v</em> and <em>b.v</em> (<em>a.v</em> contains "a" module, b.v contains "b" module). Module "a" includes module "b".</p>
<p>When the following args are used for the tool:<br /><pre>
a.v b.v --include-path /path/to/b/file --module-name a
</pre><br />the tool hangs. These arguments seem to be strange, because "b" module appears two times in the command line.<br />More adequate diagnostics should be shown here, and, of course, no freezes.</p> Verilog Translator - Bug #9962 (Closed): ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: j...https://forge.ispras.ru/issues/99622019-12-03T13:52:50ZSergey Smolovsmolov@ispras.ru
<pre>
ERROR: Cycle inclusion at: '/home/ssedai/projects/veritrans/src/test/verilog/rest-tests/mips16/mips_16_defs.v'
ERROR: Definition of 'PC_WIDTH' has not been found
ERROR: [Internal] null
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkFalse(InvariantChecks.java:68)
at ru.ispras.verilog.parser.VerilogTranslator.exit(VerilogTranslator.java:116)
at ru.ispras.verilog.parser.VerilogFrontend.expand(VerilogFrontend.java:254)
at ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor.mPP_EXPAND(VerilogLexer_VerilogPreprocessor.java:873)
at ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor.mTokens(VerilogLexer_VerilogPreprocessor.java:1566)
at ru.ispras.verilog.parser.grammar.VerilogLexer.mTokens(VerilogLexer.java:7673)
at org.antlr.runtime.Lexer.nextToken(Lexer.java:85)
at ru.ispras.verilog.parser.util.TokenSourceStack.getNextToken(TokenSourceStack.java:113)
at ru.ispras.verilog.parser.util.TokenSourceStack.nextToken(TokenSourceStack.java:133)
at org.antlr.runtime.BufferedTokenStream.fetch(BufferedTokenStream.java:143)
at org.antlr.runtime.BufferedTokenStream.sync(BufferedTokenStream.java:137)
at org.antlr.runtime.CommonTokenStream.consume(CommonTokenStream.java:68)
at org.antlr.runtime.BaseRecognizer.match(BaseRecognizer.java:106)
at ru.ispras.verilog.parser.grammar.VerilogParser.range(VerilogParser.java:6643)
at ru.ispras.verilog.parser.grammar.VerilogParser.port_declaration(VerilogParser.java:3688)
at ru.ispras.verilog.parser.grammar.VerilogParser.list_of_port_declarations(VerilogParser.java:2007)
at ru.ispras.verilog.parser.grammar.VerilogParser.module_declaration(VerilogParser.java:979)
at ru.ispras.verilog.parser.grammar.VerilogParser.description(VerilogParser.java:687)
at ru.ispras.verilog.parser.grammar.VerilogParser.source_code(VerilogParser.java:564)
at ru.ispras.verilog.parser.grammar.VerilogParser.startRule(VerilogParser.java:497)
at ru.ispras.verilog.parser.VerilogFrontend.startParser(VerilogFrontend.java:416)
at ru.ispras.verilog.parser.VerilogFrontend.startParser(VerilogFrontend.java:426)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:462)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:472)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:193)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.sample.VerilogPrinterTestCase.runTest(VerilogPrinterTestCase.java:48)
at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.lang.reflect.Method.invoke(Method.java:498)
at org.junit.runners.model.FrameworkMethod$1.runReflectiveCall(FrameworkMethod.java:47)
at org.junit.internal.runners.model.ReflectiveCallable.run(ReflectiveCallable.java:12)
at org.junit.runners.model.FrameworkMethod.invokeExplosively(FrameworkMethod.java:44)
at org.junit.internal.runners.statements.InvokeMethod.evaluate(InvokeMethod.java:17)
at org.junit.runners.ParentRunner.runLeaf(ParentRunner.java:271)
at org.junit.runners.BlockJUnit4ClassRunner.runChild(BlockJUnit4ClassRunner.java:70)
at org.junit.runners.BlockJUnit4ClassRunner.runChild(BlockJUnit4ClassRunner.java:50)
at org.junit.runners.ParentRunner$3.run(ParentRunner.java:238)
at org.junit.runners.ParentRunner$1.schedule(ParentRunner.java:63)
at org.junit.runners.ParentRunner.runChildren(ParentRunner.java:236)
at org.junit.runners.ParentRunner.access$000(ParentRunner.java:53)
at org.junit.runners.ParentRunner$2.evaluate(ParentRunner.java:229)
at org.junit.runners.ParentRunner.run(ParentRunner.java:309)
at org.gradle.api.internal.tasks.testing.junit.JUnitTestClassExecutor.runTestClass(JUnitTestClassExecutor.java:106)
at org.gradle.api.internal.tasks.testing.junit.JUnitTestClassExecutor.execute(JUnitTestClassExecutor.java:58)
at org.gradle.api.internal.tasks.testing.junit.JUnitTestClassExecutor.execute(JUnitTestClassExecutor.java:38)
at org.gradle.api.internal.tasks.testing.junit.AbstractJUnitTestClassProcessor.processTestClass(AbstractJUnitTestClassProcessor.java:66)
at org.gradle.api.internal.tasks.testing.SuiteTestClassProcessor.processTestClass(SuiteTestClassProcessor.java:51)
at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.lang.reflect.Method.invoke(Method.java:498)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:35)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:24)
at org.gradle.internal.dispatch.ContextClassLoaderDispatch.dispatch(ContextClassLoaderDispatch.java:32)
at org.gradle.internal.dispatch.ProxyDispatchAdapter$DispatchingInvocationHandler.invoke(ProxyDispatchAdapter.java:93)
at com.sun.proxy.$Proxy2.processTestClass(Unknown Source)
at org.gradle.api.internal.tasks.testing.worker.TestWorker.processTestClass(TestWorker.java:117)
at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.lang.reflect.Method.invoke(Method.java:498)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:35)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:24)
at org.gradle.internal.remote.internal.hub.MessageHubBackedObjectConnection$DispatchWrapper.dispatch(MessageHubBackedObjectConnection.java:155)
at org.gradle.internal.remote.internal.hub.MessageHubBackedObjectConnection$DispatchWrapper.dispatch(MessageHubBackedObjectConnection.java:137)
at org.gradle.internal.remote.internal.hub.MessageHub$Handler.run(MessageHub.java:404)
at org.gradle.internal.concurrent.ExecutorPolicy$CatchAndRecordFailures.onExecute(ExecutorPolicy.java:63)
at org.gradle.internal.concurrent.ManagedExecutorImpl$1.run(ManagedExecutorImpl.java:46)
at java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1149)
at java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:624)
at org.gradle.internal.concurrent.ThreadFactoryImpl$ManagedThreadRunnable.run(ThreadFactoryImpl.java:55)
at java.lang.Thread.run(Thread.java:748)
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkFalse(InvariantChecks.java:68)
at ru.ispras.verilog.parser.VerilogTranslator.exit(VerilogTranslator.java:116)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:221)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.sample.VerilogPrinterTestCase.runTest(VerilogPrinterTestCase.java:48)
</pre> Verilog Translator - Bug #9936 (Closed): tabs in "`define" directive cause java.lang.NumberFormat...https://forge.ispras.ru/issues/99362019-11-20T10:13:56ZSergey Smolovsmolov@ispras.ru
<p>Running the <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase#runTest_Pci_Bus_Verilog_Mv_files_PciNorm</strong> test case produces the following error log:<br /><pre>
ERROR: [Internal] For input string: " "
java.lang.NumberFormatException: For input string: " "
at java.lang.NumberFormatException.forInputString(NumberFormatException.java:65)
at java.lang.Integer.parseInt(Integer.java:569)
at java.lang.Integer.parseInt(Integer.java:615)
at ru.ispras.verilog.parser.model.util.Parser.parseSizeBase(Parser.java:313)
at ru.ispras.verilog.parser.model.util.Parser.parseNumber(Parser.java:177)
at ru.ispras.verilog.parser.model.basis.VerilogLiteral.parseNumber(VerilogLiteral.java:46)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_number(VerilogTreeBuilder.java:7636)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_primary(VerilogTreeBuilder.java:6390)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_operation(VerilogTreeBuilder.java:6274)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_expression(VerilogTreeBuilder.java:6128)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_extended_expression(VerilogTreeBuilder.java:5403)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_assignment(VerilogTreeBuilder.java:5333)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_assign_statement(VerilogTreeBuilder.java:4427)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4165)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:5237)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4255)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_process(VerilogTreeBuilder.java:3302)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_item(VerilogTreeBuilder.java:1031)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_module(VerilogTreeBuilder.java:758)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_unit(VerilogTreeBuilder.java:605)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:553)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:503)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:437)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:442)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:468)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:472)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:193)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:67)
at ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_Pci_Bus_Verilog_Mv_files_PciNorm(VerilogTexas97TestCase.java:673)
</pre><br />This exception is caused by the line 1045 of <em>hdl-benchmarks/hdl/texas97/PCI_BUS/Verilog-MV-files/PCInorm.v</em> file, where tab symbol is used:<br /><pre>
`define MemWrite 'h 7
</pre></p> Verilog Translator - Bug #9915 (Closed): "Cycle inclusion has been detected in fine <filename>" e...https://forge.ispras.ru/issues/99152019-11-13T12:01:33ZSergey Smolovsmolov@ispras.ru
<p>The tool reports "Cycle inclusion has been detected in fine <filename>" error for the case when "a.v" and "b.v" modules include "c.v" module.</p>
<p>To reproduce the bug, checkout to <a class="changeset" title="hdl-benchmark submodule update Signed-off-by: chudnovmaxim <chudnov@ispras.ru>" href="https://forge.ispras.ru/projects/veritrans/repository/veritrans/revisions/5ca788cdbc460bf393ccdef4b9cd6451f71acdd0">5ca788cd</a> commit and run <strong>ru.ispras.verilog.parser.VerilogQuipTestCase</strong>. It should be fail-free, but it is not.</p>
<p>IMPORTANT: please run all the project tests before push and compare your results with Jenkins!</p> Verilog Translator - Bug #9902 (New): java.lang.IllegalArgumentException: Descriptor for '<var na...https://forge.ispras.ru/issues/99022019-11-01T16:20:57ZSergey Smolovsmolov@ispras.ru
<p>When running the tool on the <a href="https://github.com/ispras/hdl-benchmarks/blob/master/hdl/iwls05/faraday/rtl/DMA/hdl/dma_chsel.v" class="external">dma_chsel.v</a> and <a href="https://github.com/ispras/hdl-benchmarks/blob/master/hdl/iwls05/faraday/rtl/DMA/hdl/dma_rrarb.v" class="external">dma_rrarb.v</a> modules the following error log appears:<br /><pre>
ru.ispras.verilog.parser.VerilogIwlsTestCase > runTest_dma_chsel STANDARD_ERROR
java.lang.IllegalArgumentException: Descriptor for 'dma_chsel.arb_chcsr_reg' has not been found: {dma_chsel.HCLK=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.HRSTn=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.dma_req=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.dma_ack=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.dma_tc=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.csr=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.sync=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.de_err_notify=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c0csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c0abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c0llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c1csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c1abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c1llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c2csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c2abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c2llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c3csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c3abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c3llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c4csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c4abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c4llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c5csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c5abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c5llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c6csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c6abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c6llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c7csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c7abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c7llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.arb_ch_sel=(BIT_VECTOR 3):(SHIFT 0)}
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:109)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute$1.apply(VerilogTransformerVariableSubstitute.java:121)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:169)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:229)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:213)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute.shiftRanges(VerilogTransformerVariableSubstitute.java:95)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute.transform(VerilogTransformerVariableSubstitute.java:142)
at ru.ispras.verilog.parser.transformer.VerilogTransformerComposite.transform(VerilogTransformerComposite.java:57)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:177)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:189)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.onDeclarationBegin(VerilogTransformer.java:67)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$13.onBegin(VerilogNodeVisitor.java:385)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:81)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.run(VerilogTransformer.java:52)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiate(VerilogInstantiator.java:145)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateDescriptor(VerilogInstantiator.java:124)
at ru.ispras.verilog.parser.elaborator.VerilogDesign$Builder.build(VerilogDesign.java:102)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:246)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:187)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:111)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:71)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:45)
at ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_dma_chsel(VerilogIwlsTestCase.java:51)
</pre></p>
<p>To reproduce the bug, run <strong>ru.ispras.verilog.parser.VerilogIwlsTestCase#runTest_dma_chsel</strong> test from <em>Retrascope Test Suite</em> project.</p> QEMU4V - Bug #9288 (Closed): /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’https://forge.ispras.ru/issues/92882018-09-28T08:44:54ZSergey Smolovsmolov@ispras.ru
<p>Compilation error:</p>
<pre>
/srv/****/workspace/QEMU4V/target/mips/translate.c: In function ‘gen_logic_imm’:
/srv/****/workspace/QEMU4V/target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’
else {
^~~~
/srv/****/workspace/QEMU4V/rules.mak:69: recipe for target 'target/mips/translate.o' failed
make[1]: *** [target/mips/translate.o] Error 1
Makefile:481: recipe for target 'subdir-mips-softmmu' failed
make: *** [subdir-mips-softmmu] Error 2
:make FAILED
</pre> Retrascope - Bug #5719 (Closed): EFSM Test Generator hangs on b11https://forge.ispras.ru/issues/57192015-03-18T07:20:55ZSergey Smolovsmolov@ispras.ru
<p>The EFSM Test Generator that is run at <strong>EfsmTestGeneratorVhdlTestCase</strong> hangs on b11 VHDL design (or this testcase continues more than <strong>8 hours</strong> - it is very suspicious).</p>
<p>The log fragment is attached below.</p> Retrascope - Bug #5680 (Closed): [efsm][generator][test][fate] DirectedFateGenerator.generateSequ...https://forge.ispras.ru/issues/56802015-03-04T08:01:26ZSergey Smolovsmolov@ispras.ru
<p>The error appears upon b07 design processing.</p>
<p>The stack trace:</p>
<p>[stack]<br />java.lang.NullPointerException<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.DirectedFateGenerator.generateSequence(DirectedFateGenerator.java:226)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.DirectedFateGenerator.getNextSequenceIterator(DirectedFateGenerator.java:163)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGenerator.start(EfsmFateTestGenerator.java:315)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGenerator.start(EfsmFateTestGenerator.java:52)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:200)<br /> at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:106)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:200)<br /> at ru.ispras.retrascope.Retrascope$Run.start(Retrascope.java:116)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:333)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:355)<br /> at ru.ispras.retrascope.util.VhdlUtilTest.runRetrascope(VhdlUtilTest.java:148)<br /> at ru.ispras.retrascope.util.VhdlUtilTest.runVhdl(VhdlUtilTest.java:73)<br /> at ru.ispras.retrascope.util.HdlUtilTest.runVhdl(HdlUtilTest.java:94)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGeneratorVhdlTestCase.generate(EfsmFateTestGeneratorVhdlTestCase.java:32)<br />[/stack]</p>
<p>Full log is attached below.</p>