Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692018-05-04T10:30:35ZOpen-Source Projects
Redmine Verilog Translator - Bug #8847 (Closed): test_17_01_01_2_1.v: Module 'pulldown' cannot be foundhttps://forge.ispras.ru/issues/88472018-05-04T10:30:35ZSergey Smolovsmolov@ispras.ru
<p>The 'pulldown' keyword is treated as module name.</p>
<p>To reproduce the bug, uncomment the <em>runTest_17_01_01_2_1()</em> method at <em>VerilogIeeeTestCase</em>. You'll get the following error log:<br /><pre>
runTest_17_01_01_2_1 STANDARD_OUT
Module name: disp
Including file 'L:\work\veritrans\src\test\verilog\ieee-tests\test_17_01_01_2_1.v' ...
Starting the backend 'static-checker'...
Instance: null
Declaration for node 'pd[]' has not been found
Declaration for node 'rval[]' has found: DECLARATION(rval)
Declaration for node 'rval[]' has found: DECLARATION(rval)
Declaration for node 'rval[]' has found: DECLARATION(rval)
Declaration for node 'rval[]' has found: DECLARATION(rval)
Declaration for node 'rval[]' has found: DECLARATION(rval)
Declaration for node 'rval[]' has found: DECLARATION(rval)
Declaration for node 'pd[]' has not been found
Starting the backend 'printer'...
module disp();
reg [31:0] rval;
/* DECL: null */
pulldown null
(
pd
);
initial
begin
rval /* DECL: rval */ = 101;
/* DECL: null */
$display(0010001001101100011000010110110101101001011000110110010101100100001000000110010000100101001000000111100001100101011010000010000001101000001001010010000000111101001000000110110001100001011101100111001000100010, rval, rval);
/* DECL: null */
$display(0010001001101110011010010110001000100000011000100010010100100000001111010010000001101100011000010111011001110010011011100101110001101100011000010111010001100011011011110010000001101111001001010010000000111101001000000110110001100001011101100111001000100010, rval, rval);
/* DECL: null */
$display(0010001001100101011101010110110001100001011101100010000001110010011001010111010001100011011000010111001001100001011010000110001100100000011010010110100101100011011100110110000100100000011000110010010100100000011100110110000101101000001000000110110001100001011101100111001000100010, rval);
/* DECL: null */
$display(00100010011101100010010100100000011100110110100100100000011001010111010101101100011000010111011000100000011010000111010001100111011011100110010101110010011101000111001100100000011001000111000000100010, pd);
/* DECL: null */
$display(001000100110110100100101001000000111001101101001001000000110010101110000011011110110001101110011001000000111010001101110011001010111001001110010011101010110001100100010);
/* DECL: null */
$display(001000100011000100110000001100010010000001110010011011110110011000100000011001010111010101101100011000010111011000100000011010010110100101100011011100110110000100100000011100110110100100100000011100110010010100100010, 101);
/* DECL: null */
$display(0010001001110100001001010010000001110011011010010010000001100101011011010110100101110100001000000110111001101111011010010111010001100001011011000111010101101101011010010111001100100010, f());
end
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(disp)'...
Bindings: {rval=rval}
Variables: {rval=DECLARATION(rval)}
Module 'pulldown' cannot be found
Unexpected exception thrown.
</pre></p> Verilog Translator - Bug #8846 (Closed): test_19_04_00_3.v: Module 'real_last' cannot be foundhttps://forge.ispras.ru/issues/88462018-05-04T10:20:00ZSergey Smolovsmolov@ispras.ru
<p>Here is the tool log for <em>test_19_04_00_3.v</em> module:<br /><pre>
runTest_19_04_00_3 STANDARD_ERROR
L:\work\veritrans\src\test\verilog\ieee-tests\test_19_04_00_3.v line 36:6 mismatched input 'initial' expecting LPAREN
ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 35:11 required (...)+ loop did not match anything at input 'initial'
ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 35:11 mismatched tree node: UP expecting AST_ATTRIBUTES
ru.ispras.verilog.parser.VerilogIeeeTestCase > runTest_19_04_00_3 STANDARD_OUT
Starting the backend 'static-checker'...
Instance: null
Starting the backend 'printer'...
module test();
initial
/* DECL: null */
$display(0010001000101110011001000110010101101110011010010110011001100101011001000010000001110100011011110110111000100000011101000110110001110101011100110110010101110010010111110111010001110011011000010110110000100000001011000110101101100011011011110110110001100010010111110110010001101110011011110110001101100101011100110010000000101100011010110110001101101111011011000110001001011111011101000111001101110010011010010110011000100010);
/* DECL: null */
real_last null
(
);
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(test)'...
Bindings: {}
Variables: {}
Module 'real_last' cannot be found
Unexpected exception thrown.
</pre></p>
<p>To reproduce the bug uncomment the <em>runTest_19_04_00_3</em> method (line 1759) at <em>VerilogIeeeTestCase</em></p> Verilog Translator - Bug #8832 (Closed): verilog/opencores/mips16/IF_stage.v: java.lang.IllegalSt...https://forge.ispras.ru/issues/88322018-04-16T13:53:13ZSergey Smolovsmolov@ispras.ru
<p>This error appears when running ru.ispras.retrascope.parser.verilog.sample.IfStageVerilogParserTestCase in the Retrascope project.</p>
<p>The corresponding Verilog file:</p>
<p>retrascope/src/test/verilog/opencores/mips16/IF_stage.v</p>
<p>The error log:<br /><pre>
Parameter is not a value: (BVSUB 8 1)
java.lang.IllegalStateException: Parameter is not a value: (BVSUB 8 1)
at ru.ispras.fortress.expression.NodeOperation.getParams(NodeOperation.java:260)
at ru.ispras.fortress.expression.NodeOperation.getDataType(NodeOperation.java:196)
at ru.ispras.retrascope.parser.verilog.VerilogCfgBuilder.declareVariables(VerilogCfgBuilder.java:110)
at ru.ispras.retrascope.parser.verilog.VerilogCfgBuilder.start(VerilogCfgBuilder.java:71)
at ru.ispras.verilog.parser.VerilogDesignBackends.start(VerilogDesignBackends.java:56)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:169)
at ru.ispras.retrascope.parser.verilog.VerilogParser.parse(VerilogParser.java:103)
at ru.ispras.retrascope.parser.basis.HdlParser.start(HdlParser.java:112)
at ru.ispras.retrascope.basis.Engine.start(Engine.java:217)
at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:111)
at ru.ispras.retrascope.basis.Engine.start(Engine.java:217)
at ru.ispras.retrascope.Retrascope$ToolRun.start(Retrascope.java:215)
at ru.ispras.retrascope.Retrascope.main(Retrascope.java:456)
at ru.ispras.retrascope.Retrascope.main(Retrascope.java:373)
at ru.ispras.retrascope.util.ToolTest.runTest(ToolTest.java:81)
at ru.ispras.retrascope.parser.verilog.VerilogParserTest.runTest(VerilogParserTest.java:40)
at ru.ispras.retrascope.parser.verilog.sample.IfStageVerilogParserTestCase.runTest(IfStageVerilogParserTestCase.java:50)
at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.lang.reflect.Method.invoke(Method.java:498)
at org.junit.runners.model.FrameworkMethod$1.runReflectiveCall(FrameworkMethod.java:44)
at org.junit.internal.runners.model.ReflectiveCallable.run(ReflectiveCallable.java:15)
at org.junit.runners.model.FrameworkMethod.invokeExplosively(FrameworkMethod.java:41)
at org.junit.internal.runners.statements.InvokeMethod.evaluate(InvokeMethod.java:20)
at org.junit.runners.BlockJUnit4ClassRunner.runChild(BlockJUnit4ClassRunner.java:76)
at org.junit.runners.BlockJUnit4ClassRunner.runChild(BlockJUnit4ClassRunner.java:50)
at org.junit.runners.ParentRunner$3.run(ParentRunner.java:193)
at org.junit.runners.ParentRunner$1.schedule(ParentRunner.java:52)
at org.junit.runners.ParentRunner.runChildren(ParentRunner.java:191)
at org.junit.runners.ParentRunner.access$000(ParentRunner.java:42)
at org.junit.runners.ParentRunner$2.evaluate(ParentRunner.java:184)
at org.junit.runners.ParentRunner.run(ParentRunner.java:236)
at org.gradle.api.internal.tasks.testing.junit.JUnitTestClassExecuter.runTestClass(JUnitTestClassExecuter.java:114)
at org.gradle.api.internal.tasks.testing.junit.JUnitTestClassExecuter.execute(JUnitTestClassExecuter.java:57)
at org.gradle.api.internal.tasks.testing.junit.JUnitTestClassProcessor.processTestClass(JUnitTestClassProcessor.java:66)
at org.gradle.api.internal.tasks.testing.SuiteTestClassProcessor.processTestClass(SuiteTestClassProcessor.java:51)
at sun.reflect.GeneratedMethodAccessor3.invoke(Unknown Source)
at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.lang.reflect.Method.invoke(Method.java:498)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:35)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:24)
at org.gradle.internal.dispatch.ContextClassLoaderDispatch.dispatch(ContextClassLoaderDispatch.java:32)
at org.gradle.internal.dispatch.ProxyDispatchAdapter$DispatchingInvocationHandler.invoke(ProxyDispatchAdapter.java:93)
at com.sun.proxy.$Proxy2.processTestClass(Unknown Source)
at org.gradle.api.internal.tasks.testing.worker.TestWorker.processTestClass(TestWorker.java:109)
at sun.reflect.GeneratedMethodAccessor2.invoke(Unknown Source)
at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.lang.reflect.Method.invoke(Method.java:498)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:35)
at org.gradle.internal.dispatch.ReflectionDispatch.dispatch(ReflectionDispatch.java:24)
at org.gradle.internal.remote.internal.hub.MessageHub$Handler.run(MessageHub.java:377)
at org.gradle.internal.concurrent.ExecutorPolicy$CatchAndRecordFailures.onExecute(ExecutorPolicy.java:54)
at org.gradle.internal.concurrent.StoppableExecutorImpl$1.run(StoppableExecutorImpl.java:40)
</pre></p> Verilog Translator - Bug #8831 (Closed): vcegar-benchmarks/ipbdp/ipbdp_hier.v: java.lang.IllegalA...https://forge.ispras.ru/issues/88312018-04-16T13:19:00ZSergey Smolovsmolov@ispras.ru
<p>This error appears when running ru.ispras.verilog.parser.sample.vcegar.VcegarIpbdpHierVerilogPrinterTestCase in the Retrascope MC Benchmark project.</p>
<p>The corresponding Verilog file:</p>
<p>retrascope-mc-benchmark/src/main/verilog/vcegar-benchmarks/ipbdp/ipbdp_hier.v</p>
<p>The error log:</p>
<pre>
Bit vector sizes do not match: 4 != 32.
java.lang.IllegalArgumentException: Bit vector sizes do not match: 4 != 32.
at ru.ispras.fortress.data.types.bitvector.BitVectorMath.checkEqualSize(BitVectorMath.java:938)
at ru.ispras.fortress.data.types.bitvector.BitVectorMath.transform(BitVectorMath.java:914)
at ru.ispras.fortress.data.types.bitvector.BitVectorMath.add(BitVectorMath.java:682)
at ru.ispras.fortress.data.types.bitvector.BitVectorMath.sub(BitVectorMath.java:695)
at ru.ispras.verilog.parser.calculator.VerilogOperations$10.calculate(VerilogOperations.java:224)
at ru.ispras.fortress.calculator.OperationGroup.calculate(OperationGroup.java:145)
at ru.ispras.fortress.transformer.Reducer$OperationRule.apply(Reducer.java:148)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:166)
at ru.ispras.fortress.transformer.NodeTransformer.updateNode(NodeTransformer.java:176)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:224)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Reducer.reduce(Reducer.java:184)
at ru.ispras.fortress.transformer.Reducer.reduce(Reducer.java:249)
at ru.ispras.verilog.parser.processor.VerilogExprTransformer.reduce(VerilogExprTransformer.java:77)
at ru.ispras.verilog.parser.model.basis.VerilogExpression.reduce(VerilogExpression.java:337)
at ru.ispras.verilog.parser.model.basis.VerilogExpression.reduce(VerilogExpression.java:349)
at ru.ispras.verilog.parser.processor.VerilogProcessorContextUtils.reduceExpression(VerilogProcessorContextUtils.java:66)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.reduce(VerilogStaticChecker.java:579)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:349)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:366)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.checkReference(VerilogStaticChecker.java:388)
at ru.ispras.verilog.parser.processor.VerilogStaticChecker.onAssignBegin(VerilogStaticChecker.java:106)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$2.onBegin(VerilogNodeVisitor.java:253)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:100)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:85)
at ru.ispras.verilog.parser.VerilogSyntaxBackend.start(VerilogSyntaxBackend.java:80)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:56)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:163)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:51)
at ru.ispras.verilog.parser.sample.VerilogPrinterTest.runTest(VerilogPrinterTest.java:48)
</pre> Verilog Translator - Bug #8779 (Closed): mips16/data_mem.v: wrong type for define-containing decl...https://forge.ispras.ru/issues/87792018-03-23T08:38:42ZSergey Smolovsmolov@ispras.ru
<p>The right-hand side of following statement:<br /><pre><code class="text syntaxhl" data-language="text">wire [`DATA_MEM_ADDR_WIDTH-1 : 0] ram_addr = mem_access_addr[`DATA_MEM_ADDR_WIDTH-1 : 0];
</code></pre><br />is represented by Verilog Translator as follows (SMT_LIB format):<br /><pre><code class="text syntaxhl" data-language="text">(BVEXTRACT 2 0 (BVEXTRACT 7 0 mem_access_addr))
</code></pre><br />The left-hand side has no ranges - it contains "ram_addr" variable only.</p> Verilog Translator - Bug #8738 (Closed): DataMemTestCase falls with errorhttps://forge.ispras.ru/issues/87382018-02-26T13:34:50ZSergey Smolovsmolov@ispras.ruRetrascope - Bug #8681 (Closed): EngineRegistry fails to create toolchain when HashSet\HashMap ar...https://forge.ispras.ru/issues/86812018-01-19T13:30:09ZSergey Smolovsmolov@ispras.ru
<p>The result of EngineRegistry toolchain construction mechanism implicitly depends from order in sets\maps.<br />When HashSet\HashMap classes are used, it can return null, while with LinkedHashSet\LinkedHashMap it is ok.<br />To reproduce the bug, substitute set\map classes from linked to non-linked and run HlddAssertSmvPrinterTestCase on JDK 1.8.</p> Verilog Translator - Bug #6363 (Closed): src/test/verilog/fifo0/mem_2p.v: AbstractMethodErrorhttps://forge.ispras.ru/issues/63632015-10-21T15:38:50ZSergey Smolovsmolov@ispras.ru
<p>Exception in thread "main" java.lang.AbstractMethodError: ru.ispras.verilog.parser.calculator.StandardIntegerOperations$12.validTypes([Lru/ispras/fortress/data/Data;)Z<br /> at ru.ispras.fortress.calculator.OperationGroup.isSupported(OperationGroup.java:109)<br /> at ru.ispras.fortress.transformer.OperationReducer.isSupported(OperationReducer.java:148)<br /> at ru.ispras.fortress.transformer.OperationReducer.calculate(OperationReducer.java:195)<br /> at ru.ispras.fortress.transformer.OperationReducer.reduce(OperationReducer.java:76)<br /> at ru.ispras.fortress.transformer.Transformer.reduce(Transformer.java:73)<br /> at ru.ispras.fortress.transformer.OperationReducer.analyzeOperands(OperationReducer.java:112)<br /> at ru.ispras.fortress.transformer.OperationReducer.<init>(OperationReducer.java:65)<br /> at ru.ispras.fortress.transformer.Transformer.reduce(Transformer.java:70)<br /> at ru.ispras.verilog.parser.model.basis.Expression.reduce(Unknown Source)<br /> at ru.ispras.verilog.parser.model.basis.Expression.reduce(Unknown Source)<br /> at ru.ispras.verilog.parser.processor.VerilogGenerateProcessor.reduce(Unknown Source)<br /> at ru.ispras.verilog.parser.processor.VerilogGenerateProcessor.reduce(Unknown Source)<br /> at ru.ispras.verilog.parser.processor.VerilogGenerateProcessor.reduce(Unknown Source)<br /> at ru.ispras.verilog.parser.processor.VerilogGenerateProcessor.onDeclarationBegin(Unknown Source)<br /> at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$13.onBegin(Unknown Source)<br /> at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(Unknown Source)<br /> at ru.ispras.verilog.parser.core.TreeWalker.onBegin(Unknown Source)<br /> at ru.ispras.verilog.parser.core.TreeWalker.start(Unknown Source)<br /> at ru.ispras.verilog.parser.VerilogBackend.start(Unknown Source)<br /> at ru.ispras.verilog.parser.VerilogBackends.start(Unknown Source)<br /> at ru.ispras.verilog.parser.VerilogTranslator.start(Unknown Source)</p> Verilog Translator - Bug #6355 (Closed): src/test/verilog/fifo/fifo_testbench.v: NullPointerExcep...https://forge.ispras.ru/issues/63552015-10-16T11:24:13ZSergey Smolovsmolov@ispras.ru
<p>While running VerilogPrinter on src/test/verilog/fifo/fifo_testbench.v the following error appears:<br /><pre>
Including file 'src/test/verilog/fifo/fifo_testbench.v'
java.lang.NullPointerException
at ru.ispras.fortress.data.types.bitvector.BitVector.notNullCheck(BitVector.java:772)
at ru.ispras.fortress.data.types.bitvector.BitVector.valueOf(BitVector.java:535)
at ru.ispras.verilog.parser.model.basis.Literal.getBitVector(Literal.java:222)
at ru.ispras.verilog.parser.model.basis.Literal.getValue(Literal.java:356)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_primary(VerilogTreeBuilder.java:7296)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_expression(VerilogTreeBuilder.java:7146)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_task_statement(VerilogTreeBuilder.java:5031)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4633)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:6057)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4737)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_process(VerilogTreeBuilder.java:3600)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_item(VerilogTreeBuilder.java:958)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_module(VerilogTreeBuilder.java:634)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:440)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:382)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:216)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:220)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:231)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:235)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:120)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:46)
</pre></p> Verilog Translator - Bug #5567 (Closed): VerilogStaticChecker.ExpressionVisitor is not abstract a...https://forge.ispras.ru/issues/55672015-01-22T11:55:30ZSergey Smolovsmolov@ispras.ru
<p>$ ant<br />Buildfile: /home/ssedai/projects/veritrans.svn/veritrans/build.xml</p>
<p>init:</p>
<p>parser:<br /> [echo] antlr VerilogLexer.g<br /> [echo] antlr VerilogParser.g<br /> [echo] antlr VerilogTreeBuilder.g</p>
<p>build:<br /> [javac] Compiling 50 source files to /home/ssedai/projects/veritrans.svn/veritrans/bin/main<br /> [javac] /home/ssedai/projects/veritrans.svn/veritrans/src/main/java/ru/ispras/verilog/parser/processor/VerilogStaticChecker.java:68: error: VerilogStaticChecker.ExpressionVisitor is not abstract and does not override abstract method getOperandOrder() in ExprTreeVisitor<br /> [javac] private final class ExpressionVisitor implements ExprTreeVisitor {<br /> [javac] ^<br /> [javac] 1 error</p>
<p>BUILD FAILED<br />/home/ssedai/projects/veritrans.svn/veritrans/build.xml:91: Compile failed; see the compiler error output for details.</p> Verilog Translator - Bug #5492 (Closed): retrascope + sapic.v = java.lang.IllegalStateException: ...https://forge.ispras.ru/issues/54922014-12-12T11:58:53ZSergey Smolovsmolov@ispras.ru
<p>Running the HDL Retrascope tool with the following parameters:</p>
<p>--target efsm /home/ssedai/projects/retrascope-internals.svn/tests/verilog/test_001/sapic.v</p>
<p>causes an error:</p>
<p>[log]</p>
<p>java.lang.IllegalStateException: Operand is not a constant integer value: 00000000000000000000000000000011<br /> at ru.ispras.fortress.expression.NodeOperation.getDataType(NodeOperation.java:151)<br /> at ru.ispras.fortress.expression.NodeOperation.getDataType(NodeOperation.java:141)<br /> at ru.ispras.fortress.expression.NodeOperation.getDataType(NodeOperation.java:141)<br /> at ru.ispras.fortress.expression.NodeOperation.getDataType(NodeOperation.java:141)<br /> at ru.ispras.retrascope.parser.verilog.VerilogCfgBuilder.parseAssignment(VerilogCfgBuilder.java:478)<br /> at ru.ispras.retrascope.parser.verilog.VerilogCfgBuilder.onAssignStatementBegin(VerilogCfgBuilder.java:680)<br /> at ru.ispras.verilog.parser.processor.VerilogGenerateProcessor.onAssignStatementBegin(Unknown Source)<br /> at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(Unknown Source)<br /> at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(Unknown Source)<br /> at ru.ispras.verilog.parser.core.TreeWalker.onBegin(Unknown Source)<br /> at ru.ispras.verilog.parser.core.TreeWalker.start(Unknown Source)<br /> at ru.ispras.verilog.parser.VerilogBackend.start(Unknown Source)<br /> at ru.ispras.verilog.parser.VerilogBackends.start(Unknown Source)<br /> at ru.ispras.verilog.parser.VerilogTranslator.start(Unknown Source)<br /> at ru.ispras.retrascope.parser.verilog.VerilogParser.parse(VerilogParser.java:88)<br /> at ru.ispras.retrascope.parser.basis.HDLParser.start(HDLParser.java:61)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:199)<br /> at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:106)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:199)<br /> at ru.ispras.retrascope.Retrascope$Run.start(Retrascope.java:115)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:325)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:346)<br /> at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)<br /> at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:57)<br /> at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)<br /> at java.lang.reflect.Method.invoke(Method.java:606)<br /> at com.intellij.rt.execution.application.AppMain.main(AppMain.java:134)<br />2014.12.12 14:46:01.833. ERROR: The exception has been encountered: java.lang.NullPointerException<br /> at ru.ispras.retrascope.basis.Engine.runBackends(Engine.java:253)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:201)<br /> at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:106)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:199)<br /> at ru.ispras.retrascope.Retrascope$Run.start(Retrascope.java:115)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:325)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:346)<br /> at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)<br /> at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:57)<br /> at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)<br /> at java.lang.reflect.Method.invoke(Method.java:606)<br /> at com.intellij.rt.execution.application.AppMain.main(AppMain.java:134)</p>
<p>[/log]</p> Retrascope - Bug #5404 (Closed): [verilog][parser][cfg] java.lang.IllegalArgumentException: Unsup...https://forge.ispras.ru/issues/54042014-11-02T12:15:20ZSergey Smolovsmolov@ispras.ru
<p>Running: verilog-parser<br />Options: {v=[D:\Sergey\projects\retrascope.svn\trunk\retrascope\src\test\verilog\ram\ram.v], args=D:\Sergey\projects\retrascope.svn\trunk\retrascope\src\test\verilog\ram\ram.v --target efsm --engine cgaa-efsm-transformer}<br />2014.11.02 14:02:28.860. INFO: Start observing module ram.<br />2014.11.02 14:02:28.860. INFO: add variable clk [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.861. INFO: add variable rst [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.862. INFO: add variable val_rd [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.862. INFO: add variable val_wr [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.863. INFO: add variable addr_in [(BIT_VECTOR 2)] (Data[type=(BIT_VECTOR 2), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.864. INFO: add variable data_in [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.864. INFO: add variable val_out [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.865. INFO: add variable data_out [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.866. INFO: add variable is_ready [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.866. INFO: add variable mem0 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.867. INFO: add variable mem1 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.868. INFO: add variable mem2 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.868. INFO: add variable mem3 [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.869. INFO: add variable result [(BIT_VECTOR 32)] (Data[type=(BIT_VECTOR 32), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.870. INFO: add variable state [(BIT_VECTOR 2)] (Data[type=(BIT_VECTOR 2), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.871. INFO: add variable RAM_IDLE [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.875. INFO: add variable RAM_READ [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.876. INFO: add variable RAM_WRITE [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />2014.11.02 14:02:28.877. INFO: add variable RAM_RESULT [(BIT_VECTOR 1)] (Data[type=(BIT_VECTOR 1), value=uninitialized]) to module ram.<br />Storing: cfg</p>
<p>Running: cfg-cgaa-transformer<br />Options: {args=D:\Sergey\projects\retrascope.svn\trunk\retrascope\src\test\verilog\ram\ram.v --target efsm --engine cgaa-efsm-transformer, cfg=<cfg>}<br />Storing: cgaa</p>
<p>Running: cgaa-efsm-transformer<br />Options: {cgaa=<cgaa>, args=D:\Sergey\projects\retrascope.svn\trunk\retrascope\src\test\verilog\ram\ram.v --target efsm --engine cgaa-efsm-transformer}<br />2014.11.02 14:02:28.888. ERROR: The exception has been encountered: java.lang.IllegalArgumentException: Unsupported data type: UNKNOWN<br /> at ru.ispras.fortress.solver.engine.z3.SMTStrings.textForData(SMTStrings.java:147)<br /> at ru.ispras.fortress.solver.engine.z3.SMTTextBuilder.onValue(SMTTextBuilder.java:303)<br /> at ru.ispras.fortress.solver.engine.z3.SMTTextBuilder.onValue(SMTTextBuilder.java:282)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitValue(ExprTreeWalker.java:209)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:152)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:192)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:160)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:192)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:160)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:192)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:160)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:127)<br /> at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:100)<br /> at ru.ispras.fortress.solver.engine.z3.Z3TextSolver.solve(Z3TextSolver.java:120)<br /> at ru.ispras.fortress.expression.ExprUtils.isSAT(ExprUtils.java:350)<br /> at ru.ispras.fortress.expression.ExprUtils.areCompatible(ExprUtils.java:335)<br /> at ru.ispras.retrascope.engine.cgaa.transformer.efsm.CgaaStateExprVisitor.isSAT(CgaaStateExprVisitor.java:203)<br /> at ru.ispras.retrascope.engine.cgaa.transformer.efsm.CgaaStateExprVisitor.checkConditionsIfNot(CgaaStateExprVisitor.java:192)<br /> at ru.ispras.retrascope.engine.cgaa.transformer.efsm.CgaaStateExprVisitor.onBasicBlockBegin(CgaaStateExprVisitor.java:183)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitBasicBlock(CfgWalker.java:255)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:133)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitCase(CfgWalker.java:247)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:139)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitSwitch(CfgWalker.java:229)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:145)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitCase(CfgWalker.java:247)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:139)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitSwitch(CfgWalker.java:229)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:145)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitSource(CfgWalker.java:213)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitNode(CfgWalker.java:151)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visit(CfgWalker.java:109)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitCfg(CfgWalker.java:204)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitProcess(CfgWalker.java:195)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitModule(CfgWalker.java:179)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.visitCfgModel(CfgWalker.java:166)<br /> at ru.ispras.retrascope.model.cfg.CfgWalker.start(CfgWalker.java:86)<br /> at ru.ispras.retrascope.engine.cfg.CfgEngine.start(CfgEngine.java:126)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:191)<br /> at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:106)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:191)<br /> at ru.ispras.retrascope.Retrascope$Run.start(Retrascope.java:117)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:320)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:341)<br /> at ru.ispras.retrascope.util.VerilogUtilTest.runRetrascope(VerilogUtilTest.java:120)<br /> at ru.ispras.retrascope.util.VerilogUtilTest.runVerilog(VerilogUtilTest.java:69)<br /> at ru.ispras.retrascope.util.HdlUtilTest.runVerilog(HdlUtilTest.java:137)<br /> at ru.ispras.retrascope.util.HdlUtilTest.runHdl(HdlUtilTest.java:51)</p> Java SoftFloat - Bug #5385 (Closed): Странная структура директорий проектаhttps://forge.ispras.ru/issues/53852014-10-24T07:55:28ZSergey Smolovsmolov@ispras.ru
<p>В репозитории проекта замечена папка jsoftfloat, находящаяся на том же уровне вложенности, что и традиционные branches, tags, trunk.<br />Это запланированное явление, или результат ошибки?</p> Retrascope - Bug #5096 (Closed): [basis] FileCreator: "Can't create file" errorhttps://forge.ispras.ru/issues/50962014-07-17T13:17:22ZSergey Smolovsmolov@ispras.ru
<p>Если файл уже был когда-то создан, то попытка пересоздать его с помощью метода newFile класса FileCreator приводит к ошибке "Can't create file".</p> Retrascope IDE - Bug #4991 (Closed): Не передается путь к HDL-описаниюhttps://forge.ispras.ru/issues/49912014-06-16T10:43:45ZSergey Smolovsmolov@ispras.ru
<p>Если во вкладке Input Files в меню Retrascope Tool Launcher выбрать *.vhd-файл, то инструменту Retrascope в качестве аргумента передается только имя файла без указания пути, что приводит к ошибке "File not found" VHDL-парсера.</p>