Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692020-04-08T09:12:41ZOpen-Source Projects
Redmine Verilog Translator - Bug #10237 (Closed): ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTes...https://forge.ispras.ru/issues/102372020-04-08T09:12:41ZSergey Smolovsmolov@ispras.ru
<p>The tool reports about cycle inclusion, but the described file does not contain includes at all.<br />Run <strong>ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2</strong> to reproduce it.</p> Verilog Translator - Bug #9915 (Closed): "Cycle inclusion has been detected in fine <filename>" e...https://forge.ispras.ru/issues/99152019-11-13T12:01:33ZSergey Smolovsmolov@ispras.ru
<p>The tool reports "Cycle inclusion has been detected in fine <filename>" error for the case when "a.v" and "b.v" modules include "c.v" module.</p>
<p>To reproduce the bug, checkout to <a class="changeset" title="hdl-benchmark submodule update Signed-off-by: chudnovmaxim <chudnov@ispras.ru>" href="https://forge.ispras.ru/projects/veritrans/repository/veritrans/revisions/5ca788cdbc460bf393ccdef4b9cd6451f71acdd0">5ca788cd</a> commit and run <strong>ru.ispras.verilog.parser.VerilogQuipTestCase</strong>. It should be fail-free, but it is not.</p>
<p>IMPORTANT: please run all the project tests before push and compare your results with Jenkins!</p> Retrascope - Task #9911 (Closed): merge "*/sample/*TestCase" Java test cases https://forge.ispras.ru/issues/99112019-11-12T08:52:05ZSergey Smolovsmolov@ispras.ru
<p>There are separate "*/sample/*TestCase" Java classes in the project. They contain duplicated code and should be merged the same way as benchmark-related test case collections at Verilog Translator project. See <strong>ru.ispras.verilog.parser.VerilogQuipTestCase</strong> for example.</p> QEMU4V - Bug #9288 (Closed): /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’https://forge.ispras.ru/issues/92882018-09-28T08:44:54ZSergey Smolovsmolov@ispras.ru
<p>Compilation error:</p>
<pre>
/srv/****/workspace/QEMU4V/target/mips/translate.c: In function ‘gen_logic_imm’:
/srv/****/workspace/QEMU4V/target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’
else {
^~~~
/srv/****/workspace/QEMU4V/rules.mak:69: recipe for target 'target/mips/translate.o' failed
make[1]: *** [target/mips/translate.o] Error 1
Makefile:481: recipe for target 'subdir-mips-softmmu' failed
make: *** [subdir-mips-softmmu] Error 2
:make FAILED
</pre> Verilog Translator - Bug #9215 (Rejected): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTes...https://forge.ispras.ru/issues/92152018-08-11T15:24:15ZSergey Smolovsmolov@ispras.ru
<pre>
Module name: mem
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 47:19 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 50:19 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 147:5 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 148:12 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 171:5 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/mem.v line 179:5 mismatched input 'reg' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 47:8 required (...)+ loop did not match anything at input 'wire'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 47:8 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Starting the backend 'printer'...
module mem(.clkclk /* DECL: clk */, .TS_TS_ /* DECL: TS_ */, .TTTT /* DECL: TT */, .GBL_GBL_ /* DECL: GBL_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .DBB_DBB_ /* DECL: DBB_ */, .TA_TA_ /* DECL: TA_ */, .DRTRY_DRTRY_ /* DECL: DRTRY_ */, .BG1_BG1_ /* DECL: BG1_ */, .BG2_BG2_ /* DECL: BG2_ */, .DBG1_DBG1_ /* DECL: DBG1_ */, clk /* DECL: clk */, TS_ /* DECL: TS_ */, TT /* DECL: TT */, GBL_ /* DECL: GBL_ */, AACK_ /* DECL: AACK_ */, ARTRY_ /* DECL: ARTRY_ */, DBB_ /* DECL: DBB_ */, TA_ /* DECL: TA_ */, DRTRY_ /* DECL: DRTRY_ */, BG1_ /* DECL: BG1_ */, BG2_ /* DECL: BG2_ */, DBG1_ /* DECL: DBG1_ */);
input clk;
input TS_;
input [00000000000000000000000000000000:00000000000000000000000000000100] TT;
input GBL_;
output AACK_;
input ARTRY_;
input DBB_;
output TA_;
output DRTRY_;
input BG1_;
input BG2_;
input DBG1_;
/* DECL: null */
AddrStatus null
(
);
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(mem)'...
Bindings: {clk=clk, TS_=TS_, TT=TT, GBL_=GBL_, AACK_=AACK_, ARTRY_=ARTRY_, DBB_=DBB_, TA_=TA_, DRTRY_=DRTRY_, BG1_=BG1_, BG2_=BG2_, DBG1_=DBG1_}
Variables: {clk=DECLARATION(clk), TS_=DECLARATION(TS_), TT=DECLARATION(TT), GBL_=DECLARATION(GBL_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), DBB_=DECLARATION(DBB_), TA_=DECLARATION(TA_), DRTRY_=DECLARATION(DRTRY_), BG1_=DECLARATION(BG1_), BG2_=DECLARATION(BG2_), DBG1_=DECLARATION(DBG1_)}
Module 'AddrStatus' cannot be found
</pre>
<p>To reproduce the bug, uncomment the <strong>runTest_PPC60X_bus_src_mem</strong> method in <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase</strong> and run it.</p> Verilog Translator - Bug #9214 (Rejected): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTes...https://forge.ispras.ru/issues/92142018-08-11T15:16:52ZSergey Smolovsmolov@ispras.ru
<pre>
Module name: cpu
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 155:17 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 157:14 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 159:16 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 161:14 mismatched input 'reg' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 228:37 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 229:44 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 230:36 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 233:26 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 234:33 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 235:27 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 236:34 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 321:33 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 322:33 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 323:32 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 324:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 325:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 326:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 327:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 328:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 329:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 330:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 331:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 332:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 333:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 334:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 338:39 extraneous input '&&' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 339:28 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 341:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 342:9 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 346:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 347:35 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 348:36 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 349:43 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 350:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 351:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 352:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 353:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 354:10 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 356:40 mismatched input '&&' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 356:46 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 359:36 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 360:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 361:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 362:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 363:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 364:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 365:12 mismatched input '==' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 387:47 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 388:43 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 389:46 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 390:19 extraneous input ')' expecting SEMI
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 403:51 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 404:58 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 407:44 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 408:51 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 409:45 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 410:52 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 436:14 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 643:74 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 644:46 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 645:39 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 646:45 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 647:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 648:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 649:44 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 650:42 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 651:39 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 652:48 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 653:56 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 654:41 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 655:40 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 656:47 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 885:6 no viable alternative at input ':'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 906:29 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 907:32 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 908:29 no viable alternative at input '||'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 909:29 no viable alternative at input ')'
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 909:57 mismatched input ')' expecting COLON
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 939:16 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 941:16 mismatched input 'wire' expecting LPAREN
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/cpu.v line 943:16 mismatched input 'wire' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 155:3 required (...)+ loop did not match anything at input 'reg'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 155:3 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR_[]' has been found: DECLARATION(BR_)
Declaration of 'BG_[]' has been found: DECLARATION(BG_)
Declaration of 'ABB_[]' has been found: DECLARATION(ABB_)
Declaration of 'ABB1_[]' has been found: DECLARATION(ABB1_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'TS1_[]' has been found: DECLARATION(TS1_)
Declaration of 'AP[]' has been found: DECLARATION(AP)
Declaration of 'APE_[]' has been found: DECLARATION(APE_)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'TT1[]' has been found: DECLARATION(TT1)
Declaration of 'TSIZ[]' has been found: DECLARATION(TSIZ)
Declaration of 'TBST_[]' has been found: DECLARATION(TBST_)
Declaration of 'TBST1_[]' has been found: DECLARATION(TBST1_)
Declaration of 'TC[]' has been found: DECLARATION(TC)
Declaration of 'CI_[]' has been found: DECLARATION(CI_)
Declaration of 'WT_[]' has been found: DECLARATION(WT_)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'GBL1_[]' has been found: DECLARATION(GBL1_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'ARTRY1_[]' has been found: DECLARATION(ARTRY1_)
Declaration of 'SHD_[]' has been found: DECLARATION(SHD_)
Declaration of 'DBG_[]' has been found: DECLARATION(DBG_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'DBB1_[]' has been found: DECLARATION(DBB1_)
Declaration of 'DP[]' has been found: DECLARATION(DP)
Declaration of 'DPE_[]' has been found: DECLARATION(DPE_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR_[]' has been found: DECLARATION(BR_)
Declaration of 'BG_[]' has been found: DECLARATION(BG_)
Declaration of 'ABB_[]' has been found: DECLARATION(ABB_)
Declaration of 'ABB1_[]' has been found: DECLARATION(ABB1_)
Declaration of 'TS1_[]' has been found: DECLARATION(TS1_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'AP[]' has been found: DECLARATION(AP)
Declaration of 'APE_[]' has been found: DECLARATION(APE_)
Declaration of 'TT1[]' has been found: DECLARATION(TT1)
Declaration of 'TT[]' has been found: DECLARATION(TT)
Declaration of 'TSIZ[]' has been found: DECLARATION(TSIZ)
Declaration of 'TBST1_[]' has been found: DECLARATION(TBST1_)
Declaration of 'TBST_[]' has been found: DECLARATION(TBST_)
Declaration of 'TC[]' has been found: DECLARATION(TC)
Declaration of 'CI_[]' has been found: DECLARATION(CI_)
Declaration of 'WT_[]' has been found: DECLARATION(WT_)
Declaration of 'GBL1_[]' has been found: DECLARATION(GBL1_)
Declaration of 'GBL_[]' has been found: DECLARATION(GBL_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY1_[]' has been found: DECLARATION(ARTRY1_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'SHD_[]' has been found: DECLARATION(SHD_)
Declaration of 'DBG_[]' has been found: DECLARATION(DBG_)
Declaration of 'DBB_[]' has been found: DECLARATION(DBB_)
Declaration of 'DBB1_[]' has been found: DECLARATION(DBB1_)
Declaration of 'DP[]' has been found: DECLARATION(DP)
Declaration of 'DPE_[]' has been found: DECLARATION(DPE_)
Declaration of 'TA_[]' has been found: DECLARATION(TA_)
Declaration of 'DRTRY_[]' has been found: DECLARATION(DRTRY_)
Starting the backend 'printer'...
module cpu(.clkclk /* DECL: clk */, .BR_BR_ /* DECL: BR_ */, .BG_BG_ /* DECL: BG_ */, .ABB_ABB_ /* DECL: ABB_ */, .ABB1_ABB1_ /* DECL: ABB1_ */, .TS_TS_ /* DECL: TS_ */, .TS1_TS1_ /* DECL: TS1_ */, .APAP /* DECL: AP */, .APE_APE_ /* DECL: APE_ */, .TTTT /* DECL: TT */, .TT1TT1 /* DECL: TT1 */, .TSIZTSIZ /* DECL: TSIZ */, .TBST_TBST_ /* DECL: TBST_ */, .TBST1_TBST1_ /* DECL: TBST1_ */, .TCTC /* DECL: TC */, .CI_CI_ /* DECL: CI_ */, .WT_WT_ /* DECL: WT_ */, .GBL_GBL_ /* DECL: GBL_ */, .GBL1_GBL1_ /* DECL: GBL1_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .ARTRY1_ARTRY1_ /* DECL: ARTRY1_ */, .SHD_SHD_ /* DECL: SHD_ */, .DBG_DBG_ /* DECL: DBG_ */, .DBB_DBB_ /* DECL: DBB_ */, .DBB1_DBB1_ /* DECL: DBB1_ */, .DPDP /* DECL: DP */, .DPE_DPE_ /* DECL: DPE_ */, .TA_TA_ /* DECL: TA_ */, .DRTRY_DRTRY_ /* DECL: DRTRY_ */, clk /* DECL: clk */, BR_ /* DECL: BR_ */, BG_ /* DECL: BG_ */, ABB_ /* DECL: ABB_ */, ABB1_ /* DECL: ABB1_ */, TS1_ /* DECL: TS1_ */, TS_ /* DECL: TS_ */, AP /* DECL: AP */, APE_ /* DECL: APE_ */, TT1 /* DECL: TT1 */, TT /* DECL: TT */, TSIZ /* DECL: TSIZ */, TBST1_ /* DECL: TBST1_ */, TBST_ /* DECL: TBST_ */, TC /* DECL: TC */, CI_ /* DECL: CI_ */, WT_ /* DECL: WT_ */, GBL1_ /* DECL: GBL1_ */, GBL_ /* DECL: GBL_ */, AACK_ /* DECL: AACK_ */, ARTRY1_ /* DECL: ARTRY1_ */, ARTRY_ /* DECL: ARTRY_ */, SHD_ /* DECL: SHD_ */, DBG_ /* DECL: DBG_ */, DBB_ /* DECL: DBB_ */, DBB1_ /* DECL: DBB1_ */, DP /* DECL: DP */, DPE_ /* DECL: DPE_ */, TA_ /* DECL: TA_ */, DRTRY_ /* DECL: DRTRY_ */);
input clk;
output BR_;
input BG_;
input ABB_;
output ABB1_;
output TS1_;
input TS_;
output [00000000000000000000000000000000:00000000000000000000000000000011] AP;
output APE_;
output [00000000000000000000000000000100:00000000000000000000000000000000] TT1;
input [00000000000000000000000000000100:00000000000000000000000000000000] TT;
output [00000000000000000000000000000010:00000000000000000000000000000000] TSIZ;
output TBST1_;
input TBST_;
output [00000000000000000000000000000000:00000000000000000000000000000010] TC;
output CI_;
output WT_;
output GBL1_;
input GBL_;
input AACK_;
output ARTRY1_;
input ARTRY_;
output SHD_;
input DBG_;
input DBB_;
output DBB1_;
output [00000000000000000000000000000000:00000000000000000000000000000111] DP;
output DPE_;
input TA_;
input DRTRY_;
/* DECL: null */
AddressTenure null
(
);
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(cpu)'...
Bindings: {clk=clk, BR_=BR_, BG_=BG_, ABB_=ABB_, ABB1_=ABB1_, TS_=TS_, TS1_=TS1_, AP=AP, APE_=APE_, TT=TT, TT1=TT1, TSIZ=TSIZ, TBST_=TBST_, TBST1_=TBST1_, TC=TC, CI_=CI_, WT_=WT_, GBL_=GBL_, GBL1_=GBL1_, AACK_=AACK_, ARTRY_=ARTRY_, ARTRY1_=ARTRY1_, SHD_=SHD_, DBG_=DBG_, DBB_=DBB_, DBB1_=DBB1_, DP=DP, DPE_=DPE_, TA_=TA_, DRTRY_=DRTRY_}
Variables: {clk=DECLARATION(clk), BR_=DECLARATION(BR_), BG_=DECLARATION(BG_), ABB_=DECLARATION(ABB_), ABB1_=DECLARATION(ABB1_), TS_=DECLARATION(TS_), TS1_=DECLARATION(TS1_), AP=DECLARATION(AP), APE_=DECLARATION(APE_), TT=DECLARATION(TT), TT1=DECLARATION(TT1), TSIZ=DECLARATION(TSIZ), TBST_=DECLARATION(TBST_), TBST1_=DECLARATION(TBST1_), TC=DECLARATION(TC), CI_=DECLARATION(CI_), WT_=DECLARATION(WT_), GBL_=DECLARATION(GBL_), GBL1_=DECLARATION(GBL1_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), ARTRY1_=DECLARATION(ARTRY1_), SHD_=DECLARATION(SHD_), DBG_=DECLARATION(DBG_), DBB_=DECLARATION(DBB_), DBB1_=DECLARATION(DBB1_), DP=DECLARATION(DP), DPE_=DECLARATION(DPE_), TA_=DECLARATION(TA_), DRTRY_=DECLARATION(DRTRY_)}
Module 'AddressTenure' cannot be found
</pre>
<p>To reproduce the bug, uncomment the <strong>runTest_PPC60X_bus_src_cpu</strong> method in <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase</strong> and run it.</p> Verilog Translator - Bug #9213 (Rejected): ru.ispras.verilog.parser.VerilogTexas97TestCase.runTes...https://forge.ispras.ru/issues/92132018-08-11T15:14:35ZSergey Smolovsmolov@ispras.ru
<pre>
Module name: arb2
Including file '/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/arbiter.v' ...
/home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PPC60X_bus/src/arbiter.v line 60:15 mismatched input 'reg' expecting LPAREN
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 60:1 required (...)+ loop did not match anything at input 'reg'
ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 60:1 mismatched tree node: UP expecting AST_ATTRIBUTES
Starting the backend 'static-checker'...
Instance: null
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR1_[]' has been found: DECLARATION(BR1_)
Declaration of 'BR2_[]' has been found: DECLARATION(BR2_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Declaration of 'DBG2_[]' has been found: DECLARATION(DBG2_)
Declaration of 'clk[]' has been found: DECLARATION(clk)
Declaration of 'BR1_[]' has been found: DECLARATION(BR1_)
Declaration of 'BR2_[]' has been found: DECLARATION(BR2_)
Declaration of 'BG1_[]' has been found: DECLARATION(BG1_)
Declaration of 'BG2_[]' has been found: DECLARATION(BG2_)
Declaration of 'TS_[]' has been found: DECLARATION(TS_)
Declaration of 'AACK_[]' has been found: DECLARATION(AACK_)
Declaration of 'ARTRY_[]' has been found: DECLARATION(ARTRY_)
Declaration of 'DBG1_[]' has been found: DECLARATION(DBG1_)
Declaration of 'DBG2_[]' has been found: DECLARATION(DBG2_)
Starting the backend 'printer'...
module arb2(.clkclk /* DECL: clk */, .BR1_BR1_ /* DECL: BR1_ */, .BR2_BR2_ /* DECL: BR2_ */, .BG1_BG1_ /* DECL: BG1_ */, .BG2_BG2_ /* DECL: BG2_ */, .TS_TS_ /* DECL: TS_ */, .AACK_AACK_ /* DECL: AACK_ */, .ARTRY_ARTRY_ /* DECL: ARTRY_ */, .DBG1_DBG1_ /* DECL: DBG1_ */, .DBG2_DBG2_ /* DECL: DBG2_ */, clk /* DECL: clk */, BR1_ /* DECL: BR1_ */, BR2_ /* DECL: BR2_ */, BG1_ /* DECL: BG1_ */, BG2_ /* DECL: BG2_ */, TS_ /* DECL: TS_ */, AACK_ /* DECL: AACK_ */, ARTRY_ /* DECL: ARTRY_ */, DBG1_ /* DECL: DBG1_ */, DBG2_ /* DECL: DBG2_ */);
input clk;
input BR1_;
input BR2_;
output BG1_;
output BG2_;
input TS_;
input AACK_;
input ARTRY_;
output DBG1_;
output DBG2_;
wire bus_request;
/* DECL: null */
ArbiterStatus null
(
);
endmodule
Starting the backend 'design-elaborator'...
Expanding node 'MODULE(arb2)'...
Bindings: {clk=clk, BR1_=BR1_, BR2_=BR2_, BG1_=BG1_, BG2_=BG2_, TS_=TS_, AACK_=AACK_, ARTRY_=ARTRY_, DBG1_=DBG1_, DBG2_=DBG2_, bus_request=bus_request}
Variables: {clk=DECLARATION(clk), BR1_=DECLARATION(BR1_), BR2_=DECLARATION(BR2_), BG1_=DECLARATION(BG1_), BG2_=DECLARATION(BG2_), TS_=DECLARATION(TS_), AACK_=DECLARATION(AACK_), ARTRY_=DECLARATION(ARTRY_), DBG1_=DECLARATION(DBG1_), DBG2_=DECLARATION(DBG2_), bus_request=DECLARATION(bus_request)}
Module 'ArbiterStatus' cannot be found
</pre>
<p>To reproduce the bug, uncomment the <strong>runTest_PPC60X_bus_src_arbiter</strong> method in <strong>ru.ispras.verilog.parser.VerilogTexas97TestCase</strong> and run it.</p> Retrascope - Bug #7423 (Rejected): rnd_fsm.vhd: empty tst filehttps://forge.ispras.ru/issues/74232016-07-26T09:17:40ZSergey Smolovsmolov@ispras.ru
<p>The RETGA-based test generation engine produces an <strong>empty</strong> test for the attached VHDL design.<br />Here is the tool cmdline:<br /><pre>
<path-to-design>/rnd_fsm.vhd --target vhdl-testbench --engine efsm-test-generator --overwrite-existing --loop-limit 25
</pre></p> Retrascope - Task #6808 (Rejected): Split CFG processes into independent partshttps://forge.ispras.ru/issues/68082016-02-04T09:18:30ZSergey Smolovsmolov@ispras.ru
<p>1. Annotate CFG representation basic block statements with information about control flow (from parent switch statements) and data flow (from other basic blocks) dependencies.<br />2. Create an oriented graph of such dependencies.<br />3. Split the graph into connected components.<br />4. Split CFG representation objects into connected components are received from step 3.</p> Retrascope - Task #6367 (Closed): Fortress expressions printing in an SMV formathttps://forge.ispras.ru/issues/63672015-10-25T18:19:41ZSergey Smolovsmolov@ispras.ru
<p>We need utility methods for Fortress expressions printing in an SMV format.</p>
<p>The most wanted use case is:</p>
<p>we have a collection of Fortress expressions: <code>e[1]</code>, <code>e[2]</code>, ... , <code>e[n]</code>;<br />we want to produce and SMV file of the following structure (it is supposed to be so):</p>
<pre>
declarations(e[1])
...
declarations(e[n])
formula(e[1])
...
formula(e[n])
</pre>
<p>where i = 1, ... , n; <code>declarations(e[i])</code> is a list of variable declarations that are used in <code>e[i]</code> expression; <code>formula(e[i])</code> is an SMV equivalent for <code>e[i]</code> expression.</p> Retrascope - Bug #5719 (Closed): EFSM Test Generator hangs on b11https://forge.ispras.ru/issues/57192015-03-18T07:20:55ZSergey Smolovsmolov@ispras.ru
<p>The EFSM Test Generator that is run at <strong>EfsmTestGeneratorVhdlTestCase</strong> hangs on b11 VHDL design (or this testcase continues more than <strong>8 hours</strong> - it is very suspicious).</p>
<p>The log fragment is attached below.</p> Retrascope - Bug #5680 (Closed): [efsm][generator][test][fate] DirectedFateGenerator.generateSequ...https://forge.ispras.ru/issues/56802015-03-04T08:01:26ZSergey Smolovsmolov@ispras.ru
<p>The error appears upon b07 design processing.</p>
<p>The stack trace:</p>
<p>[stack]<br />java.lang.NullPointerException<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.DirectedFateGenerator.generateSequence(DirectedFateGenerator.java:226)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.DirectedFateGenerator.getNextSequenceIterator(DirectedFateGenerator.java:163)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGenerator.start(EfsmFateTestGenerator.java:315)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGenerator.start(EfsmFateTestGenerator.java:52)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:200)<br /> at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:106)<br /> at ru.ispras.retrascope.basis.Engine.start(Engine.java:200)<br /> at ru.ispras.retrascope.Retrascope$Run.start(Retrascope.java:116)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:333)<br /> at ru.ispras.retrascope.Retrascope.main(Retrascope.java:355)<br /> at ru.ispras.retrascope.util.VhdlUtilTest.runRetrascope(VhdlUtilTest.java:148)<br /> at ru.ispras.retrascope.util.VhdlUtilTest.runVhdl(VhdlUtilTest.java:73)<br /> at ru.ispras.retrascope.util.HdlUtilTest.runVhdl(HdlUtilTest.java:94)<br /> at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGeneratorVhdlTestCase.generate(EfsmFateTestGeneratorVhdlTestCase.java:32)<br />[/stack]</p>
<p>Full log is attached below.</p> Retrascope - Bug #5648 (Rejected): EfsmSimulator.executeAssignment -> Unsupported data type of ra...https://forge.ispras.ru/issues/56482015-02-22T16:18:15ZSergey Smolovsmolov@ispras.ru
<p>Command line arguments: src\test\vhdl\itc99-poli2\b12\b12.vhd --target test --toplevel b12 --engine efsm-fate-test-generator</p>
<pre>
java.lang.IllegalArgumentException: Unsupported data type of ranged variable: (MAP LOGIC_INTEGER LOGIC_INTEGER)
at ru.ispras.retrascope.engine.efsm.simulator.EfsmSimulator.executeAssignment(EfsmSimulator.java:623)
at ru.ispras.retrascope.engine.efsm.simulator.EfsmSimulator.executeAction(EfsmSimulator.java:578)
at ru.ispras.retrascope.engine.efsm.simulator.EfsmSimulator.initialise(EfsmSimulator.java:300)
at ru.ispras.retrascope.engine.efsm.simulator.EfsmSimulator.processEvents(EfsmSimulator.java:259)
at ru.ispras.retrascope.engine.efsm.generator.test.fate.RandomFateGenerator.generateInputVectorRandomly(RandomFateGenerator.java:194)
at ru.ispras.retrascope.engine.efsm.generator.test.fate.RandomFateGenerator$RandomFateSequenceIterator.next(RandomFateGenerator.java:506)
at ru.ispras.retrascope.engine.efsm.generator.test.fate.RandomFateGenerator$RandomFateSequenceIterator.next(RandomFateGenerator.java:490)
at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGenerator.start(EfsmFateTestGenerator.java:264)
at ru.ispras.retrascope.engine.efsm.generator.test.fate.EfsmFateTestGenerator.start(EfsmFateTestGenerator.java:51)
at ru.ispras.retrascope.basis.Engine.start(Engine.java:199)
at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:106)
at ru.ispras.retrascope.basis.Engine.start(Engine.java:199)
at ru.ispras.retrascope.Retrascope$Run.start(Retrascope.java:115)
at ru.ispras.retrascope.Retrascope.main(Retrascope.java:331)
at ru.ispras.retrascope.Retrascope.main(Retrascope.java:353)
</pre> Retrascope - Bug #5263 (Rejected): [efsm][generator][test] EfsmTestGeneratorTestCase -> java.lang...https://forge.ispras.ru/issues/52632014-09-11T10:29:41ZSergey Smolovsmolov@ispras.ru
<p>Тест падает спустя два часа работы с ошибкой:</p>
<p><code>java.lang.OutOfMemoryError: Java heap space</code></p>
<p>Характеристики машины, на которой выполнялся тест:</p>
<p>cpu: AMD Athlon(tm) 64 X2 Dual Core Processor 4200+, 2211 MHz<br />RAM: 2 GB</p> С++TESK Development Environment - Task #3756 (New): Генерация C++ кода для модели сообщенийhttps://forge.ispras.ru/issues/37562012-12-05T15:32:06ZSergey Smolovsmolov@ispras.ru
<p>Небходимо разработать метод генерации C++ кода для модели сообщений.</p>
<p>На вход методу подается несколько объектов класса Adapter. В виде какой структуры данных эти "несколько" будут подаваться - на твое усмотрение. Например, можно взять ту же, что использовалась<br />в инструменте signalsGrouper для хранения набора накликанных "интерфейсов".<br />Т.к. все адаптеры между собой различны и полных совпадений между ними быть не должно, то из самых общих соображений могу предложить использовать java.util.Set.</p>
<p>Суть метода такова: проходим по всем адаптерам и извлекаем из них объекты MessageType и помещаем их в промежуточное хранилище (возможно, тот же Set). При этом необходимо проверять, что в хранилище ещё нет такого же типа сообщений (а при разработке адаптеров для разных интерфейсов вполне реально, что они будут использовать сообщения одного типа)- делать такую проверку лучше всего посредством разработки метода сравнения equals в классе MessageType.</p>
<p><strong>Шаблон для *.h-файла</strong></p>
<pre>
#pragma once
#include <hw/message.hpp>
namespace имя_пространства_имен {
</pre> Про извлечение название пространства имен смотри <a class="issue tracker-2 status-1 priority-4 priority-default" title="Task: namespace name for test system prototypes (New)" href="https://forge.ispras.ru/issues/3755">#3755</a>
<p>Для каждого типа сообщений далее генерируем следующий код:<br /><pre>
MESSAGE(имя_типа_сообщений)
{
public:
имя_типа_сообщений();
virtual ~имя_типа_сообщений();
SUPPORT_CLONE(имя_типа_сообщений);
</pre></p>
<p>Далее для всех полей сообщения данного типа генерируем вызов соответствующего макроса. Макросы бывают следующие:<br />1) Если размер поля больше 64 бит, то нужно использовать<br /> - CPPTESK_DECLARE_FIELD_ARRAY(имя_поля, размер_массива, размер_поля); - если маска не задана<br /> - CPPTESK_DECLARE_MASKED_FIELD_ARRAY(имя_поля, размер_массива, размер_поля, маска_поля); - если маска задана</p>
<p>В силу особенностей реализации параметр размер_поля делаем равным 64, а параметр размер_массива делаем таким, чтобы удовлетворялось следующее неравенство:</p>
<p>capacity <= размер_поля*размер_массива</p>
<p>где capacity - одноименное поле соответствующего экземпляра класса MessageField.</p>
<p>2) Если размер поля меньше, или равен 64 бит, то нужно использовать<br /> - CPPTESK_DECLARE_FIELD(имя_поля, размер_поля);<br /> - CPPTESK_DECLARE_MASKED_FIELD(имя_поля, размер_поля, маска_поля);<br /> - CPPTESK_DECLARE_BIT(имя_поля); - если размер поля равен 1</p>
<pre>
};
}
</pre>
<p>Заголовочный файл называем имя_пространства_имен_msg.h</p>
<p><strong>Шаблон для .cpp файла</strong></p>
<pre>
include <имя_пространства_имен_msg.h>
namespace имя_пространства_имен {
</pre>
<p>Для каждого из типов сообщений генерируем следующий код конструктора и деструктора</p>
<pre>
имя_типа_сообщений::имя_типа_сообщений(void)
{
</pre>
<p>Для всех полей сообщения, у которых incomparable равно false (см. <a class="issue tracker-2 status-5 priority-4 priority-default closed" title="Task: флаг incomparable в полях сообщений (Closed)" href="https://forge.ispras.ru/issues/3754">#3754</a>):<br /><pre>
ADD_FIELD(имя_типа_сообщений::имя_поля);
</pre></p>
<p>Для всех полей сообщения, у которых incomparable равно true (см. <a class="issue tracker-2 status-5 priority-4 priority-default closed" title="Task: флаг incomparable в полях сообщений (Closed)" href="https://forge.ispras.ru/issues/3754">#3754</a>):<br /><pre>
ADD_INCOMPARABLE_FIELD(имя_типа_сообщений::имя_поля);
</pre></p>
<p>Рандомизируем значения полей - только если оно соответствует входному интерфейсу!<br /><pre>
RANDOMIZE_MESSAGE(*this);
}
имя_типа_сообщений::~имя_типа_сообщений(void) {}
}
</pre></p>
<p>Рекомендация - данную задачу стоить решать посредством разработки нескольких относительно простых методов в соответствующих классах, а не одного сложного.</p>