Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692020-10-04T06:54:18ZOpen-Source Projects
Redmine Verilog Translator - Bug #10513 (New): macOS related line endings at Verilog moduleshttps://forge.ispras.ru/issues/105132020-10-04T06:54:18ZSergey Smolovsmolov@ispras.ru
<p>Verilog Translator does not support macOS related line endings ('\r') at Verilog modules. Is it ok for the tool?</p> Verilog Translator - Bug #10512 (New): ADDA162H90A_atop.v line 120:47 mismatched input ':' expect...https://forge.ispras.ru/issues/105122020-10-02T08:46:35ZSergey Smolovsmolov@ispras.ru
<pre>
RROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\faraday\rtl\DSP\hdl\CODEC\FXADDA162H90A\ADDA162H90A_atop.v line 120:47 mismatched input ':' expecting RPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\faraday\rtl\DSP\hdl\CODEC\FXADDA162H90A\ADDA162H90A_atop.v line 157:47 mismatched input ':' expecting RPAREN
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 117:36 mismatched tree node: <mismatched token: [@2436,3042:3042=':',<19>,120:47], resync=$width(posedgedac_phase_check,400.00:500.00:900.00,0,> expecting <UP>
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 117:36 mismatched tree node: AST_ATTRIBUTES expecting <UP>
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 117:36 mismatched tree node: <unexpected: [@2444,3089:3089=')',<276>,120:94], resync=n_flag_dac_phase_overlape> expecting <UP>
</pre> Verilog Translator - Bug #10510 (New): ERROR: [Internal] Bit vector sizes do not match: 32 != 2.https://forge.ispras.ru/issues/105102020-10-01T15:35:04ZSergey Smolovsmolov@ispras.ru
<pre>
java.lang.IllegalArgumentException: Bit vector sizes do not match: 32 != 2.
at ru.ispras.fortress.data.types.bitvector.BitVectorMath.checkEqualSize(BitVectorMath.java:1255)
at ru.ispras.fortress.data.types.bitvector.BitVectorMath.transform(BitVectorMath.java:1231)
at ru.ispras.fortress.data.types.bitvector.BitVectorMath.add(BitVectorMath.java:869)
at ru.ispras.fortress.data.types.bitvector.BitVectorMath.sub(BitVectorMath.java:888)
at ru.ispras.verilog.parser.interpreter.VerilogOperations$10.calculate(VerilogOperations.java:222)
at ru.ispras.fortress.calculator.OperationGroup.calculate(OperationGroup.java:141)
at ru.ispras.fortress.transformer.Reducer$OperationRule.apply(Reducer.java:147)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:173)
at ru.ispras.fortress.transformer.NodeTransformer.updateNode(NodeTransformer.java:183)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:231)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Reducer.reduce(Reducer.java:183)
at ru.ispras.verilog.parser.interpreter.VerilogCalculator.evaluate(VerilogCalculator.java:67)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.evaluate(VerilogElaborator.java:1161)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.defineParameter(VerilogElaborator.java:1073)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:526)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariablesAndBindings(VerilogElaborator.java:910)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariablesAndBindings(VerilogElaborator.java:883)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:330)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:231)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:212)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogIwlsTestSuite.runTest_risc_defgh(VerilogIwlsTestSuite.java:1692)
</pre> Verilog Translator - Bug #10509 (New): ERROR: [Internal] 0 must be > 0https://forge.ispras.ru/issues/105092020-10-01T15:15:47ZSergey Smolovsmolov@ispras.ru
<pre>
ERROR: [Internal] 0 must be > 0
java.lang.IllegalArgumentException: 0 must be > 0
at ru.ispras.fortress.util.InvariantChecks.checkGreaterThanZero(InvariantChecks.java:159)
at ru.ispras.fortress.data.types.bitvector.BitVector.newEmpty(BitVector.java:381)
at ru.ispras.verilog.parser.model.basis.VerilogLiteral.<init>(VerilogLiteral.java:188)
at ru.ispras.verilog.parser.model.basis.VerilogLiteral.parseString(VerilogLiteral.java:55)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_string(VerilogTreeBuilder.java:7916)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_primary(VerilogTreeBuilder.java:6628)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_operation(VerilogTreeBuilder.java:6502)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_expression(VerilogTreeBuilder.java:6356)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_task_statement(VerilogTreeBuilder.java:4716)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4393)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:5465)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4473)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_process(VerilogTreeBuilder.java:3514)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_item(VerilogTreeBuilder.java:1214)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_module(VerilogTreeBuilder.java:918)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_unit(VerilogTreeBuilder.java:765)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:713)
at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:663)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:455)
at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:460)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:486)
at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:490)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:206)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogIwlsTestSuite.runTest_usbf_top(VerilogIwlsTestSuite.java:4417)
</pre> Verilog Translator - Bug #10508 (New): ERROR: [Internal] Java heap spacehttps://forge.ispras.ru/issues/105082020-10-01T11:33:03ZSergey Smolovsmolov@ispras.ru
<p>The following test cases fall with "ERROR: [Internal] Java heap space":</p>
<p><strong>ru.ispras.verilog.parser.VerilogIwlsTestSuite#runTest_iscas_s35932<br />ru.ispras.verilog.parser.VerilogIwlsTestSuite#runTest_iscas_s38417<br />ru.ispras.verilog.parser.VerilogIwlsTestSuite#runTest_iscas_s15850</strong></p> Verilog Translator - Bug #10505 (New): ERROR: [Internal] 11 must be within range [0, 1)https://forge.ispras.ru/issues/105052020-09-30T10:51:18ZSergey Smolovsmolov@ispras.ru
<pre>
java.lang.IndexOutOfBoundsException: 11 must be within range [0, 1)
at ru.ispras.fortress.util.InvariantChecks.checkBounds(InvariantChecks.java:190)
at ru.ispras.fortress.data.types.bitvector.BitVector.field(BitVector.java:309)
at ru.ispras.verilog.parser.interpreter.VerilogOperations$34.calculate(VerilogOperations.java:745)
at ru.ispras.fortress.calculator.OperationGroup.calculate(OperationGroup.java:141)
at ru.ispras.fortress.transformer.Reducer$OperationRule.apply(Reducer.java:147)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:173)
at ru.ispras.fortress.transformer.NodeTransformer.updateNode(NodeTransformer.java:183)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:231)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Reducer.reduce(Reducer.java:183)
at ru.ispras.fortress.transformer.Reducer.reduce(Reducer.java:248)
at ru.ispras.verilog.parser.interpreter.VerilogCalculator.reduce(VerilogCalculator.java:50)
at ru.ispras.verilog.parser.transformer.VerilogTransformerOperation.transform(VerilogTransformerOperation.java:66)
at ru.ispras.verilog.parser.transformer.VerilogTransformerComposite.transform(VerilogTransformerComposite.java:57)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:214)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:226)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:245)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.onAssignStatementBegin(VerilogTransformer.java:84)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(VerilogNodeVisitor.java:285)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:770)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:81)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.run(VerilogTransformer.java:55)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiate(VerilogInstantiator.java:198)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateProcess(VerilogInstantiator.java:144)
at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:212)
at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:199)
at ru.ispras.verilog.parser.backends.design.typecast.VerilogTypeCaster.start(VerilogTypeCaster.java:43)
at ru.ispras.verilog.parser.VerilogDesignBackends.start(VerilogDesignBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:219)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogIwlsTestSuite.runTest_opencores_pci_target_unit(VerilogIwlsTestSuite.java:3941)
</pre> Verilog Translator - Bug #10502 (New): subbytes.v line 76:13 no viable alternative at input '['https://forge.ispras.ru/issues/105022020-09-28T08:20:09ZSergey Smolovsmolov@ispras.ru
<p>When processing the hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v module, the following errors appear:<br /><pre>
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 76:13 no viable alternative at input '['
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 77:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 78:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 79:21 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 80:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 81:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 82:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 83:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 84:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 85:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 86:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 87:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 88:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 89:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 90:19 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 91:18 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 95:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 96:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 97:21 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 98:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 99:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 100:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 101:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 102:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 103:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 104:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 105:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 106:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 107:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 108:19 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 109:18 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 113:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 114:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 115:21 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 116:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 117:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 118:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 119:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 120:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 121:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 122:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 123:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 124:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 125:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 126:19 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 127:18 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 1:0 extraneous input '\' expecting KW_END
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 1:0 extraneous input '\' expecting KW_END
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 1:0 mismatched input '\' expecting KW_END
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 245:17 mismatched input '=' expecting COLON
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 245:33 missing COLON at ';'
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 246:14 mismatched input '=' expecting COLON
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 246:25 missing COLON at ';'
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 247:2 extraneous input 'end' expecting KW_ENDCASE
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 73:0 mismatched tree node: <unexpected: [@6101,3705:3705='[',<214>,76:13], resync=data_reg_128> expecting <UP>
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 76:40 mismatched tree node: AST_STRENGTH expecting <UP>
</pre></p>
<p>The problem is connected with the following macro in Verilog:<br /><pre><code class="verilog syntaxhl" data-language="verilog"><span class="cp">`define</span> <span class="n">assign_array_to_128</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">127</span><span class="o">:</span><span class="mi">120</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">0</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">119</span><span class="o">:</span><span class="mi">112</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">1</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">111</span><span class="o">:</span><span class="mi">104</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">2</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">103</span><span class="o">:</span><span class="mi">96</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">3</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">95</span><span class="o">:</span><span class="mi">88</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">4</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">87</span><span class="o">:</span><span class="mi">80</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">5</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">79</span><span class="o">:</span><span class="mi">72</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">6</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">71</span><span class="o">:</span><span class="mi">64</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">7</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">63</span><span class="o">:</span><span class="mi">56</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">8</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">55</span><span class="o">:</span><span class="mi">48</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">9</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">47</span><span class="o">:</span><span class="mi">40</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">10</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">39</span><span class="o">:</span><span class="mi">32</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">11</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">31</span><span class="o">:</span><span class="mi">24</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">12</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">23</span><span class="o">:</span><span class="mi">16</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">13</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">15</span><span class="o">:</span><span class="mi">8</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">14</span><span class="p">];</span> \
<span class="n">data_reg_128</span><span class="p">[</span><span class="mi">7</span><span class="o">:</span><span class="mi">0</span><span class="p">]</span><span class="o">=</span><span class="n">data_reg_var</span><span class="p">[</span><span class="mi">15</span><span class="p">];</span>
</code></pre></p> MicroTESK - Task #10304 (New): deprecation warnings via compilationhttps://forge.ispras.ru/issues/103042020-04-23T12:19:57ZSergey Smolovsmolov@ispras.ru
<pre>
> Task :compileJava
/srv/****/workspace/MicroTESK/src/main/java/core/ru/ispras/microtesk/SysUtils.java:122: warning: [deprecation] newInstance() in Class has been deprecated
return cl.loadClass(className).newInstance();
^
where T is a type-variable:
T extends Object declared in class Class
/srv/****/workspace/MicroTESK/src/main/java/core/ru/ispras/microtesk/SysUtils.java:148: warning: [deprecation] newInstance() in Class has been deprecated
return (Plugin) pluginClass.newInstance();
^
where T is a type-variable:
T extends Object declared in class Class
/srv/****/workspace/MicroTESK/src/main/java/core/ru/ispras/microtesk/test/sequence/GeneratorNitems.java:78: warning: [unchecked] unchecked method invocation: method copyAll in class SharedObject is applied to given types
return SharedObject.copyAll((List) value);
^
required: List<T>
found: List
where T is a type-variable:
T extends SharedObject<T> declared in method <T>copyAll(List<T>)
/srv/****/workspace/MicroTESK/src/main/java/core/ru/ispras/microtesk/test/sequence/GeneratorNitems.java:78: warning: [unchecked] unchecked conversion
return SharedObject.copyAll((List) value);
^
required: List<T>
found: List
where T is a type-variable:
T extends SharedObject<T> declared in method <T>copyAll(List<T>)
/srv/****/workspace/MicroTESK/src/main/java/core/ru/ispras/microtesk/test/sequence/GeneratorNitems.java:78: warning: [unchecked] unchecked conversion
return SharedObject.copyAll((List) value);
^
required: List<T>
found: List
where T is a type-variable:
T extends Object declared in class GeneratorNitems
/srv/****/workspace/MicroTESK/src/main/java/core/ru/ispras/microtesk/test/sequence/GeneratorConfig.java:179: warning: [deprecation] newInstance() in Class has been deprecated
return type.newInstance();
^
where T is a type-variable:
T extends Object declared in class Class
6 warnings
</pre> Verilog Translator - Bug #10246 (Rejected): ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest...https://forge.ispras.ru/issues/102462020-04-09T13:28:43ZSergey Smolovsmolov@ispras.ru
<p>The tool takes 'lut_output.v' Verilog files as input, but reports it's absence.<br /><pre>
ERROR: Module 'lut_output' has not been found
ERROR: [Internal] null
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkFalse(InvariantChecks.java:68)
at ru.ispras.verilog.parser.VerilogTranslator.exit(VerilogTranslator.java:126)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:397)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:231)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:212)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogQuipTestSuite.runTest_nut_001(VerilogQuipTestSuite.java:355)
</pre></p> Verilog Translator - Bug #10241 (Closed): ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_d...https://forge.ispras.ru/issues/102412020-04-09T06:10:11ZSergey Smolovsmolov@ispras.ru
<p>Suddenly the tool starts to complain about line endings:<br /><pre>
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 1:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 2:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 3:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 4:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 5:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 6:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 7:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 8:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 9:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 10:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 11:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 12:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 13:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 14:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 15:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 16:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 17:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 18:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 19:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 20:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 21:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 22:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 23:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 24:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 25:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 26:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 27:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 28:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 29:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 30:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 31:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 32:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 33:70 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 34:1 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 35:12 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 36:3 mismatched character '\r' expecting '\n'
ERROR: D:\Sergey\projects\veritrans\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 37:68 mismatched character '\r' expecting '\n'
...
</pre></p>
<p>Run <strong>ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_dctub_jpeg</strong> to reproduce the behavior.</p> Verilog Translator - Bug #10215 (New): ERROR: Starting points limit has been exhausted: 2255https://forge.ispras.ru/issues/102152020-04-06T09:39:48ZSergey Smolovsmolov@ispras.ru
<pre>
ERROR: Starting points limit has been exhausted: 2255
ERROR: [Internal] null
java.lang.IllegalArgumentException
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
at ru.ispras.fortress.util.InvariantChecks.checkFalse(InvariantChecks.java:68)
at ru.ispras.verilog.parser.VerilogTranslator.exit(VerilogTranslator.java:126)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:223)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:212)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogQuipTestSuite.runTest_nut_000(VerilogQuipTestSuite.java:301)
</pre> Verilog Translator - Bug #10131 (Closed): ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_is...https://forge.ispras.ru/issues/101312020-02-21T11:14:53ZSergey Smolovsmolov@ispras.ru
<pre>
java.lang.OutOfMemoryError: Java heap space
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:223)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
at ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_iscas_s9234_1(VerilogIwlsTestCase.java:2057)
</pre>
<p>The specified test method is commented out.</p> MicroTESK - Bug #10121 (Open): technical output printing at 'compile.sh' script running with '--h...https://forge.ispras.ru/issues/101212020-02-13T14:42:42ZSergey Smolovsmolov@ispras.ru
<pre>
$ ./bin/compile.sh --help
Buildfile: /home/ssedai/Downloads/microtesk-2.5.1-beta-200127/bin/build.xml
clean:
[delete] Deleting directory /home/ssedai/Downloads/microtesk-2.5.1-beta-200127/gen
BUILD SUCCESSFUL
Total time: 0 seconds
usage: [options] Files to be processed
-ad,--arch-dirs <arg> Home directories for tested architectures [works with -g],
default=""
-ae,--asserts-enabled Enables assertion checks during simulation [works with -g],
default=false
-af,--align-format <arg> Alignment directive format [works with -g], default=".align %d"
-aff,--align-format2 <arg> Alignment directive format [works with -g], default=".align %d,
0x%02x"
-baf,--byte-align-format <arg> Byte alignment directive format [works with -g], default=".balign
%d"
-baff,--byte-align-format2 <arg> Byte alignment directive format [works with -g], default=".balign
%d, 0x%02x"
-bel,--branch-exec-limit <arg> Maximum execution count for an instruction [works with -g],
default=100
-bfbe,--binary-file-big-endian Use big endian for binary files, default=false
-bfe,--binary-file-extension <arg> Binary file extension [works with -g], default="bin"
-btn,--base-template-name <arg> Name of test template base class [works with -gt], default=""
-btp,--base-template-path <arg> Path to test template base class file [works with -gt],
default=""
-cd,--comments-debug Enables generation of detailed comments, depends on
--comments-enabled [works with -g], default=false
-ce,--comments-enabled Enables generation of comments [works with -g], default=false
-cfe,--code-file-extension <arg> Output file extension [works with -g], default="asm"
-cfp,--code-file-prefix <arg> Output file prefix [works with -g], default="test"
-cl,--coverage-log Enables coverage trace generation [works with -g], default=false
-ct,--comment-token <arg> Single-line comment text [works with -g], default="//"
-cte,--comment-token-end <arg> Text that ends a multiline comment [works with -g], default="*/"
-cts,--comment-token-start <arg> Text that starts a multiline comment [works with -g],
default="/*"
-d,--disassemble Disassembles binary files, default=false
-dfe,--data-file-extension <arg> Data file extension [works with -g], default="asm"
-dfp,--data-file-prefix <arg> Data file prefix [works with -g], default="data"
-dp,--debug-print Enables printing detailed debug messages [works with -g],
default=false
-dsk,--data-section-keyword <arg> Data section directive [works with -g], default=".data"
-dtd,--default-test-data Enables generation of default test data [works with -g],
default=false
-ed,--extension-dir <arg> Directory that stores user-defined Java code [works with -t],
default=""
-efp,--except-file-prefix <arg> Exception handler file prefix [works with -g],
default="test_except"
-fde,--fetch-decode-enabled Enables allocation, fetching and decoding of instructions [works
with -g], default=false
-g,--generate Generates test programs, default=false
-gb,--generate-binary Enables generating binary files (limited functionality for
debugging) [works with -g], default=false
-gf,--global-format <arg> Global directive format [works with -g], default=".globl %s"
-gt,--generate-template Generates test templates, default=false
-h,--help Shows help message, default=false
-i,--include <arg> Directory that stores include files [works with -t], default=""
-ii,--ignored-instructions <arg> Instructions to be ignored [works with -gt], default=""
-in,--instance-number <arg> Number of processing element instances [works with -g], default=1
-it,--indent-token <arg> Indentation text [works with -g], default="
"
-jtpm,--jruby-thread-pool-max <arg>JRuby: maximum number of threads to allow in pool [works with
-g], default=2147483647
-mn,--model-name <arg> Name of the constructed microprocessor model [works with -t],
default=""
-ns,--no-simulation Disables simulation of generated code [works with -g],
default=false
-od,--output-dir <arg> Directory to place generated files, default="./output"
-of,--origin-format <arg> Origin directive format [works with -g], default=".org 0x%x"
-off,--option-format <arg> Option directive format [works with -g], default=".option %s"
-paf,--power2-align-format <arg> Power of 2 alignment directive format [works with -g],
default=".p2align %d"
-paff,--power2-align-format2 <arg> Power of 2 alignment directive format [works with -g],
default=".p2align %d, 0x%02x"
-pll,--program-length-limit <arg> Maximum program length [works with -g], default=1000
-rd,--reserve-dependencies Enables automated reservation of registers that have dependencies
[works with -g], default=false
-re,--reserve-explicit Enables marking all explicitly specified registers as used [works
with -g], default=false
-ri,--rev-id <arg> Identifier of revision to be used, default=""
-rl,--rate-limit <arg> Minimum generation rate [works with -g], default=0
-rs,--random-seed <arg> Seed for randomizer [works with -g], default=0
-s,--solver <arg> Constraint solver engine to be used, default="cvc4"
-sc,--self-checks Enables inserting self-checks into test programs [works with -g],
default=false
-sd,--solver-debug Enables debug mode for SMT solvers [works with -g], default=false
-se,--symbolic-execute Performs symbolic execution, default=false
-st,--separator-token <arg> Text used to create separators [works with -g], default="="
-t,--translate Translates formal specifications, default=false
-tl,--tracer-log Enables generation of Tracer logs for simulation [works with -g],
default=false
-tll,--trace-length-limit <arg> Maximum execution trace length [works with -g], default=1000
-ts,--time-statistics Enables printing time statistics [works with -g], default=false
-tsk,--text-section-keyword <arg> Text section directive [works with -g], default=".text"
-tt,--transform-trace Transforms traces into templates, default=false
-v,--verbose Enables printing diagnostic messages, default=false
-wf,--weak-format <arg> Weak directive format [works with -g], default=".weak %s"
Buildfile: /home/ssedai/Downloads/microtesk-2.5.1-beta-200127/bin/build.xml
build:
[mkdir] Created dir: /home/ssedai/Downloads/microtesk-2.5.1-beta-200127/gen/bin
BUILD FAILED
/home/ssedai/Downloads/microtesk-2.5.1-beta-200127/bin/build.xml:47: srcdir "/home/ssedai/Downloads/microtesk-2.5.1-beta-200127/gen/src/java" does not exist!
</pre> MicroTESK - Bug #10102 (Closed): incorrect ld scripts for x86 test programshttps://forge.ispras.ru/issues/101022020-02-06T10:22:06ZSergey Smolovsmolov@ispras.ru
<p>For x86 test programs emulation on QEMU4V, the following approach can be used. Test program should be compiled as <em>bootable drive</em> and run on QEMU4V ("-hda" option). The following linker script should be generated:<br /><pre>
SECTIONS
{
/* The BIOS loads the code from the disk to this location.
* We must tell that to the linker so that it can properly
* calculate the addresses of symbols we might jump to.
*/
. = 0x7c00;
.text :
{
__start = .;
*(.text)
/* Place the magic boot bytes at the end of the first 512 sector of the disk. */
. = 0x1FE;
SHORT(0xAA55)
}
}
</pre></p>
<p>Now ld scripts look as follows:<br /><pre>
ENTRY(_start)
SECTIONS
{
. = 0x7C00;
.text : { *(".text")}
. = 0x8000;
.data : { *(".data")}
.bss : { *(".bss COMMON")}
. = ALIGN(8);
. = . + 0x10000;
stack_top = .;
}
</pre></p> MicroTESK - Bug #10094 (Closed): strange common code at LinkerScript.stghttps://forge.ispras.ru/issues/100942020-02-04T14:06:08ZSergey Smolovsmolov@ispras.ru
<p>The StringTemplate description for ld scripts looks as follows (<a class="external" href="https://forge.ispras.ru/projects/microtesk/repository/microtesk/revisions/master/entry/src/main/resources/core/stg/LinkerScript.stg">https://forge.ispras.ru/projects/microtesk/repository/microtesk/revisions/master/entry/src/main/resources/core/stg/LinkerScript.stg</a>):<br /><pre>
linker_script(
time,
section_ids,
section_vas,
section_flags
) ::= <<
<linker_script_header(time)>
ENTRY(_start)
SECTIONS
{
<section_ids, section_vas, section_flags : {id, va, fl | <section(id, va, fl)>}; separator="\n">
. = ALIGN(8);
. = . + 0x10000;
stack_top = .;
}
>>
section(id, va, common) ::= <<
<if(va)>. = <va>;<\n><endif><id> : { *("<id><if(common)> COMMON<endif>")}
>>
</pre></p>
<p>The following part is common for all linker scripts that are generated by the MicroTESK:<br /><pre>
. = ALIGN(8);
. = . + 0x10000;
stack_top = .;
</pre></p>
<p>It seems suspicious that this code is repeated for all ISAs.</p>