Open-Source Projects: Issueshttps://forge.ispras.ru/https://forge.ispras.ru/favicon.ico?16490126692021-01-29T20:12:49ZOpen-Source Projects
Redmine MicroTESK - Bug #10696 (New): Error: Failed to load custom data generators for plasma.https://forge.ispras.ru/issues/106962021-01-29T20:12:49ZAlexander Protsenkoprotsenko@ispras.ru
<p>В качестве примера используется проект: <a href="https://forge.ispras.ru/projects/microtesk-plasma/repository" class="external">MicroTESK for Plasma</a></p>
<p>Пример лога:<br /><pre>
ru.ispras.microtesk.model.plasma.InstructionAluTestCase > test STANDARD_OUT
Command line: -g -ae -tl -cl -cfp instruction_alu plasma src/main/arch/plasma/templates/instruction_alu.rb
Error: Failed to load custom data generators for plasma.
</pre></p>
<p>Этого можно добиться, убрав ссылки в settings.xml<br /><pre>
<extension name="beq-if-then" path="ru.ispras.microtesk.mips.test.branch.MipsEqDataGenerator"/>
</pre></p>
<p>Или в сборке<br /><pre>
'-ed',
"${project.projectDir}/build/target/arch/plasma/extensions"
</pre></p>
<p>Что нужно сделать:<br />1. Описать в документации (и возможно подробнее в логе) что же такое эти "custom data generators", зачем они нужны (например, в пустом тесте) и как их создать.<br />2. Если это возможно, сделать генератор по умолчанию.</p> MicroTESK - Bug #10124 (New): Double preparation of the same registerhttps://forge.ispras.ru/issues/101242020-02-18T15:27:23ZAlexander Kamkinaskamkin@gmail.com
<pre>
# Preparation
li a6, 0xfffffffffffffffe
li sp, 0xf0455f8f000e3ca0
or sp, zero, zero
li gp, 0x4da9d757a0275cb0
# Stimulus
add sp, sp, a6
sub gp, gp, sp
</pre> MicroTESK - Bug #10121 (Open): technical output printing at 'compile.sh' script running with '--h...https://forge.ispras.ru/issues/101212020-02-13T14:42:42ZSergey Smolovsmolov@ispras.ru
<pre>
$ ./bin/compile.sh --help
Buildfile: /home/ssedai/Downloads/microtesk-2.5.1-beta-200127/bin/build.xml
clean:
[delete] Deleting directory /home/ssedai/Downloads/microtesk-2.5.1-beta-200127/gen
BUILD SUCCESSFUL
Total time: 0 seconds
usage: [options] Files to be processed
-ad,--arch-dirs <arg> Home directories for tested architectures [works with -g],
default=""
-ae,--asserts-enabled Enables assertion checks during simulation [works with -g],
default=false
-af,--align-format <arg> Alignment directive format [works with -g], default=".align %d"
-aff,--align-format2 <arg> Alignment directive format [works with -g], default=".align %d,
0x%02x"
-baf,--byte-align-format <arg> Byte alignment directive format [works with -g], default=".balign
%d"
-baff,--byte-align-format2 <arg> Byte alignment directive format [works with -g], default=".balign
%d, 0x%02x"
-bel,--branch-exec-limit <arg> Maximum execution count for an instruction [works with -g],
default=100
-bfbe,--binary-file-big-endian Use big endian for binary files, default=false
-bfe,--binary-file-extension <arg> Binary file extension [works with -g], default="bin"
-btn,--base-template-name <arg> Name of test template base class [works with -gt], default=""
-btp,--base-template-path <arg> Path to test template base class file [works with -gt],
default=""
-cd,--comments-debug Enables generation of detailed comments, depends on
--comments-enabled [works with -g], default=false
-ce,--comments-enabled Enables generation of comments [works with -g], default=false
-cfe,--code-file-extension <arg> Output file extension [works with -g], default="asm"
-cfp,--code-file-prefix <arg> Output file prefix [works with -g], default="test"
-cl,--coverage-log Enables coverage trace generation [works with -g], default=false
-ct,--comment-token <arg> Single-line comment text [works with -g], default="//"
-cte,--comment-token-end <arg> Text that ends a multiline comment [works with -g], default="*/"
-cts,--comment-token-start <arg> Text that starts a multiline comment [works with -g],
default="/*"
-d,--disassemble Disassembles binary files, default=false
-dfe,--data-file-extension <arg> Data file extension [works with -g], default="asm"
-dfp,--data-file-prefix <arg> Data file prefix [works with -g], default="data"
-dp,--debug-print Enables printing detailed debug messages [works with -g],
default=false
-dsk,--data-section-keyword <arg> Data section directive [works with -g], default=".data"
-dtd,--default-test-data Enables generation of default test data [works with -g],
default=false
-ed,--extension-dir <arg> Directory that stores user-defined Java code [works with -t],
default=""
-efp,--except-file-prefix <arg> Exception handler file prefix [works with -g],
default="test_except"
-fde,--fetch-decode-enabled Enables allocation, fetching and decoding of instructions [works
with -g], default=false
-g,--generate Generates test programs, default=false
-gb,--generate-binary Enables generating binary files (limited functionality for
debugging) [works with -g], default=false
-gf,--global-format <arg> Global directive format [works with -g], default=".globl %s"
-gt,--generate-template Generates test templates, default=false
-h,--help Shows help message, default=false
-i,--include <arg> Directory that stores include files [works with -t], default=""
-ii,--ignored-instructions <arg> Instructions to be ignored [works with -gt], default=""
-in,--instance-number <arg> Number of processing element instances [works with -g], default=1
-it,--indent-token <arg> Indentation text [works with -g], default="
"
-jtpm,--jruby-thread-pool-max <arg>JRuby: maximum number of threads to allow in pool [works with
-g], default=2147483647
-mn,--model-name <arg> Name of the constructed microprocessor model [works with -t],
default=""
-ns,--no-simulation Disables simulation of generated code [works with -g],
default=false
-od,--output-dir <arg> Directory to place generated files, default="./output"
-of,--origin-format <arg> Origin directive format [works with -g], default=".org 0x%x"
-off,--option-format <arg> Option directive format [works with -g], default=".option %s"
-paf,--power2-align-format <arg> Power of 2 alignment directive format [works with -g],
default=".p2align %d"
-paff,--power2-align-format2 <arg> Power of 2 alignment directive format [works with -g],
default=".p2align %d, 0x%02x"
-pll,--program-length-limit <arg> Maximum program length [works with -g], default=1000
-rd,--reserve-dependencies Enables automated reservation of registers that have dependencies
[works with -g], default=false
-re,--reserve-explicit Enables marking all explicitly specified registers as used [works
with -g], default=false
-ri,--rev-id <arg> Identifier of revision to be used, default=""
-rl,--rate-limit <arg> Minimum generation rate [works with -g], default=0
-rs,--random-seed <arg> Seed for randomizer [works with -g], default=0
-s,--solver <arg> Constraint solver engine to be used, default="cvc4"
-sc,--self-checks Enables inserting self-checks into test programs [works with -g],
default=false
-sd,--solver-debug Enables debug mode for SMT solvers [works with -g], default=false
-se,--symbolic-execute Performs symbolic execution, default=false
-st,--separator-token <arg> Text used to create separators [works with -g], default="="
-t,--translate Translates formal specifications, default=false
-tl,--tracer-log Enables generation of Tracer logs for simulation [works with -g],
default=false
-tll,--trace-length-limit <arg> Maximum execution trace length [works with -g], default=1000
-ts,--time-statistics Enables printing time statistics [works with -g], default=false
-tsk,--text-section-keyword <arg> Text section directive [works with -g], default=".text"
-tt,--transform-trace Transforms traces into templates, default=false
-v,--verbose Enables printing diagnostic messages, default=false
-wf,--weak-format <arg> Weak directive format [works with -g], default=".weak %s"
Buildfile: /home/ssedai/Downloads/microtesk-2.5.1-beta-200127/bin/build.xml
build:
[mkdir] Created dir: /home/ssedai/Downloads/microtesk-2.5.1-beta-200127/gen/bin
BUILD FAILED
/home/ssedai/Downloads/microtesk-2.5.1-beta-200127/bin/build.xml:47: srcdir "/home/ssedai/Downloads/microtesk-2.5.1-beta-200127/gen/src/java" does not exist!
</pre> MicroTESK - Task #10107 (New): Entry point specification in templateshttps://forge.ispras.ru/issues/101072020-02-11T12:39:03ZAlexander Kamkinaskamkin@gmail.com
<p>Currently, it is assumed (in the linker script printer, in particular) that the entry point is called <code>_start</code>.</p> MicroTESK - Task #10106 (New): Support %b as format's specifierhttps://forge.ispras.ru/issues/101062020-02-11T12:36:41ZAlexander Kamkinaskamkin@gmail.com
<p>Currently, we use <code>%s</code>; however, the nML specification requires <code>%b</code></p> MicroTESK - Bug #10091 (New): [x86] ошибка при добавлении модели в src\main\etc\settings.xmlhttps://forge.ispras.ru/issues/100912020-02-03T13:32:38ZAlexander Protsenkoprotsenko@ispras.ru
<p>Исходный вариант:<br /><pre>
value="cpu=arch/demo/cpu/settings.xml:
vliw=arch/demo/vliw/settings.xml:
vmem=arch/demo/vmem/settings.xml:
x86gnu=arch/demo/x86/settings.xml:
x86nasm=arch/demo/x86/settings.xml:
minimips=arch/demo/minimips/settings.xml"
</pre></p>
<p>Изменения не приводящие к ошибке:<br /><pre>
value="cpu=arch/demo/cpu/settings.xml:
vliw=arch/demo/vliw/settings.xml:
vmem=arch/demo/vmem/settings.xml:
-> x86u=arch/demo/x86/settings.xml:
x86gnu=arch/demo/x86/settings.xml:
x86nasm=arch/demo/x86/settings.xml:
minimips=arch/demo/minimips/settings.xml"
</pre></p>
<p>Изменения <strong>приводящие</strong> к ошибке:<br /><pre>
value="cpu=arch/demo/cpu/settings.xml:
vliw=arch/demo/vliw/settings.xml:
vmem=arch/demo/vmem/settings.xml:
-> x86=arch/demo/x86/settings.xml:
x86gnu=arch/demo/x86/settings.xml:
x86nasm=arch/demo/x86/settings.xml:
minimips=arch/demo/minimips/settings.xml"
</pre></p>
<p>Ошибка:<br /><pre>
> Task :translateX86Gnu FAILED
********************************************************************************
ATTENTION! An unexpected error has occurred:
java.lang.IllegalStateException: Failed to parse C:\!microtesk\microtesk\microtesk\build\target\arch\demo\x86\revisions.xml.
The program will be terminated. Please contact us at:
microtesk-support@ispras.ru
We are sorry for the inconvenience.
Exception stack:
java.lang.IllegalStateException: Failed to parse C:\!microtesk\microtesk\microtesk\build\target\arch\demo\x86\revisions.xml.
at ru.ispras.microtesk.Config.loadRevisions(Config.java:195)
at ru.ispras.microtesk.MicroTESK.loadRevisions(MicroTESK.java:176)
at ru.ispras.microtesk.MicroTESK.translate(MicroTESK.java:147)
at ru.ispras.microtesk.MicroTESK.runTask(MicroTESK.java:142)
at ru.ispras.microtesk.MicroTESK.main(MicroTESK.java:80)
Caused by: java.nio.file.NoSuchFileException: C:\!microtesk\microtesk\microtesk\build\target\arch\demo\x86\revisions.xml
at java.base/sun.nio.fs.WindowsException.translateToIOException(WindowsException.java:85)
at java.base/sun.nio.fs.WindowsException.rethrowAsIOException(WindowsException.java:103)
at java.base/sun.nio.fs.WindowsException.rethrowAsIOException(WindowsException.java:108)
at java.base/sun.nio.fs.WindowsFileSystemProvider.newByteChannel(WindowsFileSystemProvider.java:235)
at java.base/java.nio.file.Files.newByteChannel(Files.java:370)
at java.base/java.nio.file.Files.newByteChannel(Files.java:421)
at java.base/java.nio.file.spi.FileSystemProvider.newInputStream(FileSystemProvider.java:420)
at java.base/java.nio.file.Files.newInputStream(Files.java:155)
at ru.ispras.microtesk.Config.loadRevisions(Config.java:189)
... 4 more
********************************************************************************
12 actionable tasks: 11 executed, 1 up-to-date
</pre></p>
<p>Нужна информация по этой "особенности".</p> MicroTESK - Feature #10074 (New): option that stores boot obj at the generated ld scripthttps://forge.ispras.ru/issues/100742020-01-27T12:51:20ZSergey Smolovsmolov@ispras.ru
<p>Generally speaking, assembler program for boot loader should not be included into the resulting binary for test program. However, in some cases (for example, our JUnit test cases for MiniMIPS model) it could be useful.</p>
<p>So, boot object and it's address should be mentioned in the <em>ld</em> script that is generated by the MicroTESK, when the specific option is enabled.</p>
<p>Here is the working example of <em>ld</em> script that is runnable on QEMU: <a class="external" href="https://forge.ispras.ru/projects/microtesk-book/repository/418/revisions/master/entry/examples/link_qemu.ls">https://forge.ispras.ru/projects/microtesk-book/repository/418/revisions/master/entry/examples/link_qemu.ls</a></p> MicroTESK - Feature #10071 (New): Влияние секции section_text на расположение exception_handlerhttps://forge.ispras.ru/issues/100712020-01-24T14:16:57ZAlexander Protsenkoprotsenko@ispras.ru
<pre>
section_text(:pa => 0x0000_2000, :va => 0x0000_2000) {}
#
# Defines .data section.
#
# pa: base physical address (used for memory allocation).
# va: base virtual address (used for encoding instructions that refer to labels).
#
section_data(:pa => 0x0008_0000, :va => 0x0008_0000) {}
#
# Simple exception handler. Continues execution from the next instruction.
#
exception_handler {
entry_point(:org => 0x380, :exception => ['IntegerOverflow', 'SystemCall', 'Breakpoint']) {
trace 'Exception handler (EPC = 0x%x)', location('COP0_R', 14)
mfc0 ra, rcop0(14)
addi ra, ra, 4
jr ra
nop
}
}
</pre>
<pre>
------------------------------- Allocating code --------------------------------
Section: .text [pa=0x0000000000002000, va=0x0000000000002000]
Directive: .org 0x380
0x0000000000002380 (PA): mfc0 $31, $14 (0x401F7000)
0x0000000000002384 (PA): addi $31, $31, 0x4 (0x23FF0004)
0x0000000000002388 (PA): jr $31 (0x03E00008)
0x000000000000238c (PA): nop (0x00000000)
</pre>
<p>Возможно стоит убрать это влияние, и записывать exception_handler, например, так:<br /><pre>
exception_handler(:pa => 0x0000_0000, :va => 0x0000_0000) {
entry_point(:org => 0x380, :exception => ['IntegerOverflow', 'SystemCall', 'Breakpoint']) {
trace 'Exception handler (EPC = 0x%x)', location('COP0_R', 14)
mfc0 ra, rcop0(14)
addi ra, ra, 4
jr ra
nop
}
}
</pre></p> MicroTESK - Bug #10070 (New): [minimips] Нужно больше информации об ошибке "NameError: undefined ...https://forge.ispras.ru/issues/100702020-01-24T12:26:51ZAlexander Protsenkoprotsenko@ispras.ru
<p>minimips_base.rb 82: ssnop<br /><pre>
NameError: undefined local variable or method `ssnop' for #<BubbleSortTemplate:0x6cbdd1c5>
method_missing at org/jruby/RubyBasicObject.java:1555
method_missing at C:/!microtesk/microtesk/microtesk/build/target/lib/ruby/template.rb:66
pre at C:/!microtesk/microtesk/microtesk/src/main/arch/demo/minimips/templates/minimips_base.rb:82
instance_eval at org/jruby/RubyBasicObject.java:1594
section at C:/!microtesk/microtesk/microtesk/build/target/lib/ruby/template.rb:877
pre at C:/!microtesk/microtesk/microtesk/src/main/arch/demo/minimips/templates/minimips_base.rb:59
pre at C:/!microtesk/microtesk/microtesk/src/main/arch/demo/minimips/templates/bubble_sort.rb:44
generate at C:/!microtesk/microtesk/microtesk/build/target/lib/ruby/template.rb:1007
main at C:\!microtesk\microtesk\microtesk\build\target\lib\ruby\microtesk.rb:33
each at org/jruby/RubyHash.java:1342
main at C:\!microtesk\microtesk\microtesk\build\target\lib\ruby\microtesk.rb:29
(root) at C:\!microtesk\microtesk\microtesk\build\target\lib\ruby\microtesk.rb:52
</pre></p>
<p>Необходимо в этой строке<br /><pre>
NameError: undefined local variable or method `ssnop' for #<BubbleSortTemplate:0x6cbdd1c5>
</pre><br />Указывать номер строки из файла с методом `ssnop'.<br /><pre>
pre at C:/!microtesk/microtesk/microtesk/src/main/arch/demo/minimips/templates/minimips_base.rb:82
</pre></p> MicroTESK - Bug #10069 (New): cpu.nml Error: Internal error: context [/Isa] 1:8 attribute file is...https://forge.ispras.ru/issues/100692020-01-24T12:11:55ZSergey Smolovsmolov@ispras.ru
<p>Upon building, the following error appears in Gradle log:<br /><pre>
> Task :translateCpu
Translating: src/main/arch/demo/cpu/model/cpu.nml
Model name: cpu
Included: src/main/arch/demo/cpu/model/cpu.nml
Error: Internal error: context [/Isa] 1:8 attribute file isn't defined
</pre></p> Verilog Translator - Bug #9993 (New): if two modules are passed to the tool and one includes anot...https://forge.ispras.ru/issues/99932019-12-18T12:43:15ZSergey Smolovsmolov@ispras.ru
<p>Suppose there are two files with Verilog modules: <em>a.v</em> and <em>b.v</em> (<em>a.v</em> contains "a" module, b.v contains "b" module). Module "a" includes module "b".</p>
<p>When the following args are used for the tool:<br /><pre>
a.v b.v --include-path /path/to/b/file --module-name a
</pre><br />the tool hangs. These arguments seem to be strange, because "b" module appears two times in the command line.<br />More adequate diagnostics should be shown here, and, of course, no freezes.</p> Verilog Translator - Bug #9902 (New): java.lang.IllegalArgumentException: Descriptor for '<var na...https://forge.ispras.ru/issues/99022019-11-01T16:20:57ZSergey Smolovsmolov@ispras.ru
<p>When running the tool on the <a href="https://github.com/ispras/hdl-benchmarks/blob/master/hdl/iwls05/faraday/rtl/DMA/hdl/dma_chsel.v" class="external">dma_chsel.v</a> and <a href="https://github.com/ispras/hdl-benchmarks/blob/master/hdl/iwls05/faraday/rtl/DMA/hdl/dma_rrarb.v" class="external">dma_rrarb.v</a> modules the following error log appears:<br /><pre>
ru.ispras.verilog.parser.VerilogIwlsTestCase > runTest_dma_chsel STANDARD_ERROR
java.lang.IllegalArgumentException: Descriptor for 'dma_chsel.arb_chcsr_reg' has not been found: {dma_chsel.HCLK=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.HRSTn=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.dma_req=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.dma_ack=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.dma_tc=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.csr=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.sync=(BIT_VECTOR 8):(SHIFT 0), dma_chsel.de_err_notify=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c0csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c0tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c0abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c0llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c1csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c1tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c1abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c1llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c2csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c2tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c2abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c2llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c3csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c3tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c3abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c3llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c4csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c4tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c4abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c4llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c5csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c5tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c5abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c5llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c6csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c6tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c6abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c6llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c7csr=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7cfg=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7sad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7dad=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7llp=(BIT_VECTOR 32):(SHIFT 0), dma_chsel.c7tsz=(BIT_VECTOR 12):(SHIFT 0), dma_chsel.c7abt=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.c7llpen=(BIT_VECTOR 1):(SHIFT 0), dma_chsel.arb_ch_sel=(BIT_VECTOR 3):(SHIFT 0)}
at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:109)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute$1.apply(VerilogTransformerVariableSubstitute.java:121)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:169)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:229)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:213)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute.shiftRanges(VerilogTransformerVariableSubstitute.java:95)
at ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute.transform(VerilogTransformerVariableSubstitute.java:142)
at ru.ispras.verilog.parser.transformer.VerilogTransformerComposite.transform(VerilogTransformerComposite.java:57)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:177)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.transform(VerilogTransformer.java:189)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.onDeclarationBegin(VerilogTransformer.java:67)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$13.onBegin(VerilogNodeVisitor.java:385)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:102)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:81)
at ru.ispras.verilog.parser.transformer.VerilogTransformer.run(VerilogTransformer.java:52)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiate(VerilogInstantiator.java:145)
at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateDescriptor(VerilogInstantiator.java:124)
at ru.ispras.verilog.parser.elaborator.VerilogDesign$Builder.build(VerilogDesign.java:102)
at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:246)
at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:187)
at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:111)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:71)
at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:45)
at ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_dma_chsel(VerilogIwlsTestCase.java:51)
</pre></p>
<p>To reproduce the bug, run <strong>ru.ispras.verilog.parser.VerilogIwlsTestCase#runTest_dma_chsel</strong> test from <em>Retrascope Test Suite</em> project.</p> MicroTESK - Developer Request #9870 (New): Входной параметр в виде инструкцииhttps://forge.ispras.ru/issues/98702019-10-15T13:03:38ZAlexander Protsenkoprotsenko@ispras.ru
<p>В данный момент для общего шаблона генерации тестов для отдельных инструкций используется код:<br /><pre>
xxx_dist = dist(range(:value => [x_instruction], :bias => 100))
define_op_group('xxx', xxx_dist)
xxx v0, v8, v28
</pre><br />Где<br /><pre>
generate_simple_tests(x_instruction)
</pre><br />И вызывается, например:<br /><pre>
generate_simple_tests('vadd')
</pre></p>
<p>Необходим более простой вариант:<br /><pre>
get_instruction('xxx', x_instruction)
xxx v0, v8, v28
</pre></p>
<p>Существует ли в инструменте что-то подобное?</p> MicroTESK - Bug #9869 (New): Генерация граничных значений для регистров инструкцийhttps://forge.ispras.ru/issues/98692019-10-15T12:32:32ZAlexander Protsenkoprotsenko@ispras.ru
<p>В качестве примера можно посмотреть шаблон:<br /><a class="external" href="https://forge.ispras.ru/projects/microtesk-riscv/repository/385/revisions/master/entry/src/main/arch/riscv/templates/sequence/boundary_data.rb">https://forge.ispras.ru/projects/microtesk-riscv/repository/385/revisions/master/entry/src/main/arch/riscv/templates/sequence/boundary_data.rb</a></p>
<pre>
sequence {
add a0, a1, a2 do testdata('boundary') end
sub a3, a0, a4 do testdata('boundary') end
}.run
</pre>
<p>Не учитывается зависимость:<br /><pre>
Preparation
li a1, 0x7fffffffffffffff
li a2, 0x7fffffffffffffff
li a0, 0x7fffffffffffffff
li a4, 0x7fffffffffffffff
Stimulus
add a0, a1, a2
sub a3, a0, a4
</pre></p>
<p>Так же нужен пример, где генерируются граничные значения для регистров a1, a2, a4 и итерация идет для каждого из регистра.</p> Retrascope IDE - Task #5093 (New): [cfg][visualizator][zest] Следует открывать граф в области ред...https://forge.ispras.ru/issues/50932014-07-16T11:17:51ZAlexander Kamkinaskamkin@gmail.com
<p>Открывать граф в области редактора.</p>