public final class VerilogDesign
extends java.lang.Object
VerilogDesign
represents an elaborated design.Modifier and Type | Class and Description |
---|---|
static class |
VerilogDesign.Builder |
Modifier and Type | Method and Description |
---|---|
java.lang.String |
getName()
Returns the name of the design.
|
java.util.Map<java.lang.String,VerilogParameter> |
getParameters() |
java.lang.Iterable<VerilogProcess> |
getProcesses()
Returns the iterator over the design processes.
|
java.util.Map<java.lang.String,VerilogDescriptor> |
getVariables() |
public java.lang.String getName()
public java.util.Map<java.lang.String,VerilogParameter> getParameters()
public java.util.Map<java.lang.String,VerilogDescriptor> getVariables()
public java.lang.Iterable<VerilogProcess> getProcesses()