public final class VerilogTransformerVariableRename extends VerilogTransformer
VerilogTransformerVariableRename
implements an engine that renames local variables.NodeVisitor.Result
Constructor and Description |
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VerilogTransformerVariableRename() |
Modifier and Type | Method and Description |
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ru.ispras.fortress.expression.Node |
transform(ru.ispras.fortress.expression.Node node) |
static void |
transform(VerilogNode node) |
onAssignBegin, onAssignStatementBegin, onCaseStatementBegin, onCaseStatementItemBegin, onDeclarationBegin, onDelayedStatementBegin, onIfStatementBegin, onLoopStatementBegin, onTaskStatementBegin, onWaitStatementBegin, run
onActivityBegin, onActivityEnd, onAssignEnd, onAssignmentBegin, onAssignmentEnd, onAssignStatementEnd, onAttributeBegin, onAttributeEnd, onBlockGenerateBegin, onBlockGenerateEnd, onBlockStatementBegin, onBlockStatementEnd, onCaseGenerateBegin, onCaseGenerateEnd, onCaseGenerateItemBegin, onCaseGenerateItemEnd, onCaseStatementEnd, onCaseStatementItemEnd, onCodeBegin, onCodeEnd, onDeclarationEnd, onDefineParameterBegin, onDefineParameterEnd, onDelayedStatementEnd, onDisableStatementBegin, onDisableStatementEnd, onGenerateBegin, onGenerateEnd, onIfGenerateBegin, onIfGenerateBranchBegin, onIfGenerateBranchEnd, onIfGenerateEnd, onIfStatementBranchBegin, onIfStatementBranchEnd, onIfStatementEnd, onInstantiationBegin, onInstantiationEnd, onLoopGenerateBegin, onLoopGenerateEnd, onLoopStatementEnd, onModuleBegin, onModuleEnd, onNullStatementBegin, onNullStatementEnd, onPathDeclarationBegin, onPathDeclarationEnd, onPortBegin, onPortConnectionBegin, onPortConnectionEnd, onPortEnd, onProcedureBegin, onProcedureEnd, onPulseStyleBegin, onPulseStyleEnd, onShowCancelledBegin, onShowCancelledEnd, onSpecifyBegin, onSpecifyEnd, onTableBegin, onTableEnd, onTableEntryBegin, onTableEntryEnd, onTaskStatementEnd, onTriggerStatementBegin, onTriggerStatementEnd, onWaitStatementEnd
onBegin, onEnd
public static void transform(VerilogNode node)
public ru.ispras.fortress.expression.Node transform(ru.ispras.fortress.expression.Node node)
transform
in class VerilogTransformer