public final class VerilogTableEntry extends VerilogNode
VerilogTableEntry
represents UDP table entries.VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogTableEntry(VerilogNode parent)
Creates a UDP table entry.
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VerilogTableEntry(VerilogTableEntry other,
VerilogNode parent)
Creates a copy of the UDP table entry.
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Modifier and Type | Method and Description |
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void |
addEdge(java.lang.String edge)
Adds the edge to the list.
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void |
addInput1(java.lang.String input1)
Adds the input to the list (1).
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void |
addInput2(java.lang.String input2)
Adds the input to the list (2).
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void |
addOutput(java.lang.String output)
Adds the output to the list.
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VerilogTableEntry |
clone()
Clones the symbol table.
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java.util.List<java.lang.String> |
getEdge()
Returns the edges.
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java.util.List<java.lang.String> |
getInputs1()
Returns the input signals (1).
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java.util.List<java.lang.String> |
getInputs2()
Returns the input signals (2).
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java.util.List<java.lang.String> |
getOutputs()
Returns the output signals.
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getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogTableEntry(VerilogNode parent)
parent
- the parent node.public VerilogTableEntry(VerilogTableEntry other, VerilogNode parent)
other
- the UDP table entry,parent
- the parent node.public java.util.List<java.lang.String> getInputs1()
public void addInput1(java.lang.String input1)
input1
- the input to be added.public java.util.List<java.lang.String> getInputs2()
public void addInput2(java.lang.String input2)
input2
- the input to be added.public java.util.List<java.lang.String> getEdge()
public void addEdge(java.lang.String edge)
edge
- the edge to be added.public java.util.List<java.lang.String> getOutputs()
public void addOutput(java.lang.String output)
output
- the output to be added.public VerilogTableEntry clone()
AbstractSymbolTable
clone
in class VerilogNode