- gate_identifier() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- gate_identifier_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.gate_identifier_return
-
- generate_block() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- generate_block_identifier() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- generate_block_identifier_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.generate_block_identifier_return
-
- generate_block_or_null() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- generate_block_or_null_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.generate_block_or_null_return
-
- generate_block_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.generate_block_return
-
- generate_region() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- generate_region_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.generate_region_return
-
- genvar_assignment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- genvar_assignment_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.genvar_assignment_return
-
- genvar_decl() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- genvar_decl_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.genvar_decl_return
-
- genvar_declaration() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- genvar_declaration_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.genvar_declaration_return
-
- genvar_identifier() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- genvar_identifier_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.genvar_identifier_return
-
- get() - Static method in class ru.ispras.verilog.parser.VerilogLibrary
-
Returns an library instance.
- getArguments() - Method in class ru.ispras.verilog.parser.model.VerilogTaskStatement
-
Returns the arguments of the task statement.
- getArguments() - Method in class ru.ispras.verilog.parser.model.VerilogTriggerStatement
-
Returns the arguments of the trigger statement.
- getAssignment() - Method in class ru.ispras.verilog.parser.model.VerilogAssign
-
Returns the assignment itself.
- getAssignment() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Returns the assignment of the statement (the pair of l- and r-values).
- getAttributes() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Returns the expression attributes.
- getAttributes() - Method in class ru.ispras.verilog.parser.model.basis.VerilogMinTypMax
-
Returns the expression attributes.
- getAttributes() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Returns the attributes of the node.
- getBase() - Method in class ru.ispras.verilog.parser.model.util.Parser.SizeBase
-
Returns the number system of the literal.
- getBigInteger() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Returns the big integer value of the literal.
- getBindings() - Method in class ru.ispras.verilog.parser.elaborator.VerilogContext
-
- getBitSize() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Returns the bit width of the literal.
- getBitSize() - Method in class ru.ispras.verilog.parser.model.util.Parser.SizeBase
-
Returns the bit size of the literal.
- getBitsPerDigit() - Method in class ru.ispras.verilog.parser.model.util.Parser.SizeBase
-
Returns the number of bits per digit.
- getBitsSelection() - Method in class ru.ispras.verilog.parser.model.basis.VerilogReference
-
Returns the range for bits selection.
- getBitVector() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Returns the bit vector value of the literal.
- getBoolean() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Returns the boolean value of the literal.
- getByteArray() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Returns the byte array representation of the literal.
- getCalculatorEngine() - Static method in enum ru.ispras.verilog.parser.interpreter.VerilogOperations
-
- getCases() - Method in class ru.ispras.verilog.parser.model.VerilogCaseGenerate
-
Returns the cases.
- getCases() - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatement
-
Returns the cases.
- getCurrentFileName() - Method in class ru.ispras.verilog.parser.VerilogFrontend
-
Returns the name of the file being processed by the front-end.
- getDataType() - Method in class ru.ispras.verilog.parser.elaborator.VerilogDescriptor
-
- getDataType(VerilogDeclaration, ValueProvider, List<VerilogIndexRange>) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
- getDataType(VerilogDeclaration, List<VerilogIndexRange>) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
- getDeclaration() - Method in class ru.ispras.verilog.parser.elaborator.VerilogDescriptor
-
- getDeclaration() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Returns the function declaration (for function calls only).
- getDeclaration() - Method in class ru.ispras.verilog.parser.model.basis.VerilogReference
-
Returns the declaration (the reference descriptor).
- getDeclaration() - Method in class ru.ispras.verilog.parser.model.VerilogInstantiation
-
Returns the module declaration.
- getDeclaration() - Method in class ru.ispras.verilog.parser.model.VerilogTaskStatement
-
Returns the task declaration.
- getDeclarations() - Method in class ru.ispras.verilog.parser.VerilogLibrary
-
- getDefinedVariables(VerilogAssignment) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
Returns the set of variables used in the LHS of the assignment.
- getDelay() - Method in class ru.ispras.verilog.parser.model.basis.VerilogEventControl
-
Returns the delay of the delay-based control.
- getDelay() - Method in class ru.ispras.verilog.parser.model.VerilogAssign
-
Returns the assignment delay.
- getDelay() - Method in class ru.ispras.verilog.parser.model.VerilogInstantiation
-
Returns the delay of the instance's port connections.
- getDelay() - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Returns the path delay value (only for SIMPLE
).
- getDelays() - Method in class ru.ispras.verilog.parser.model.basis.VerilogDelay
-
Returns the list of expressions representing delay values.
- getDelegates() - Method in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- getDelegates() - Method in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- getDelegates() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- getDelegates() - Method in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- getDescription() - Method in class ru.ispras.verilog.parser.grammar.VerilogLexer.DFA11
-
- getDescription() - Method in class ru.ispras.verilog.parser.grammar.VerilogLexer.DFA26
-
- getDescription() - Method in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor.DFA11
-
- getDescription() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.DFA135
-
- getDescription() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.DFA158
-
- getDescription() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.DFA232
-
- getDescription() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.DFA240
-
- getDescription() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.DFA242
-
- getDescription() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.DFA61
-
- getDescription() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.DFA94
-
- getDescription() - Method in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.DFA47
-
- getDescription() - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Returns the path description (only for SIMPLE
).
- getDesign() - Method in class ru.ispras.verilog.parser.elaborator.VerilogElaborator
-
Returns the elaborated design.
- getDimensions() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Returns the dimensions of the declared element.
- getEdge() - Method in class ru.ispras.verilog.parser.model.basis.VerilogEvent
-
Returns the edge of the event.
- getEdge() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Returns the edge type of the path description.
- getEdge() - Method in class ru.ispras.verilog.parser.model.VerilogTableEntry
-
Returns the edges.
- getElementType() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Returns the type of the declared element.
- getElementType() - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Returns the return value type of the procedure.
- getElseGenerate() - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerate
-
Returns the generate block related to the branch else
.
- getElseStatement() - Method in class ru.ispras.verilog.parser.model.VerilogIfStatement
-
Returns the statement related to the branch else
.
- getEventControl() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Returns the control of the statement (the delay or event).
- getEventControl() - Method in class ru.ispras.verilog.parser.model.VerilogDelayedStatement
-
Returns the delay of the delayed statement.
- getEvents() - Method in class ru.ispras.verilog.parser.model.basis.VerilogEventControl
-
Returns the events of the event-based control.
- getEvents() - Method in class ru.ispras.verilog.parser.model.basis.VerilogRepeatEvents
-
Returns the list of events to be repeated.
- getExpression() - Method in class ru.ispras.verilog.parser.model.basis.VerilogEvent
-
Returns the expression of the event.
- getExpression() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Returns the data source expression of the path description.
- getExpression() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathItem
-
Returns the instance index of the path item.
- getExpression() - Method in class ru.ispras.verilog.parser.model.basis.VerilogRepeatEvents
-
Returns the repeat count expression.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogAttribute
-
Returns the expression of the attribute.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogCaseGenerate
-
Returns the case selection expression.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogCaseGenerateItem
-
Returns the condition associated with the case.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatement
-
Returns the case selection expression.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatementItem
-
Returns the condition associated with the case.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Returns the expression representing the initial value.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogDefineParameter
-
Returns the parameter expression.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerate
-
Returns the condition.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerateBranch
-
Returns the condition associated with the branch.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogIfStatement
-
Returns the condition.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogIfStatementBranch
-
Returns the condition associated with the branch.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogLoopGenerate
-
Returns the continue condition of the loop.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Returns the expression of the loop.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Returns the condition of the path declaration (only for IF
).
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogPortConnection
-
Returns the expression connected to the port.
- getExpression() - Method in class ru.ispras.verilog.parser.model.VerilogWaitStatement
-
Returns the wait expression.
- getExpressions() - Method in class ru.ispras.verilog.parser.model.VerilogCaseGenerateItem
-
Returns the expressions of the case.
- getExpressions() - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatementItem
-
Returns the expressions of the case.
- getFileName() - Method in class ru.ispras.verilog.parser.model.VerilogCode
-
Returns the name of the source code file.
- getFullName() - Method in class ru.ispras.verilog.parser.core.AbstractNode
-
Returns the fully qualified name of the node.
- getFullName(String) - Method in class ru.ispras.verilog.parser.elaborator.VerilogContext
-
- getGenerate() - Method in class ru.ispras.verilog.parser.model.VerilogCaseGenerateItem
-
Returns the generate block of the case.
- getGenerate() - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerateBranch
-
Returns the branch body.
- getGenerate() - Method in class ru.ispras.verilog.parser.model.VerilogLoopGenerate
-
Returns the loop body.
- getGenvars() - Method in class ru.ispras.verilog.parser.elaborator.VerilogContext
-
- getGenvarValue(String) - Method in class ru.ispras.verilog.parser.elaborator.VerilogContext
-
- getGlobalName() - Method in class ru.ispras.verilog.parser.elaborator.VerilogVariable
-
- getGlobalNode() - Method in class ru.ispras.verilog.parser.elaborator.VerilogVariable
-
- getGrammarFileName() - Method in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- getGrammarFileName() - Method in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- getGrammarFileName() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- getGrammarFileName() - Method in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- getIndexRanges() - Method in class ru.ispras.verilog.parser.elaborator.VerilogDescriptor
-
- getIndicesAndBitsSelection() - Method in class ru.ispras.verilog.parser.model.basis.VerilogReference
-
Returns the list of ranges.
- getInitialization() - Method in class ru.ispras.verilog.parser.model.VerilogLoopGenerate
-
Returns the initialization assignment of the loop.
- getInitialization() - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Returns the initialization assignment of the FOR
loop.
- getInputs() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Returns the source references of the path description.
- getInputs1() - Method in class ru.ispras.verilog.parser.model.VerilogTableEntry
-
Returns the input signals (1).
- getInputs2() - Method in class ru.ispras.verilog.parser.model.VerilogTableEntry
-
Returns the input signals (2).
- getInteger() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Returns the integer value of the literal.
- getIteration() - Method in class ru.ispras.verilog.parser.model.VerilogLoopGenerate
-
Returns the iteration assignment of the loop.
- getIteration() - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Returns the iteration assignment of the FOR
loop.
- getLastParentToken() - Method in class ru.ispras.verilog.parser.util.TokenSourceStack
-
- getLeftExpression() - Method in class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Returns the left expression of the range.
- getLevel() - Method in enum ru.ispras.verilog.parser.VerilogStandard
-
- getLhs() - Method in class ru.ispras.verilog.parser.elaborator.VerilogBinding
-
- getLhsNode() - Method in class ru.ispras.verilog.parser.model.VerilogAssignment
-
Returns the expression representation of the assignment's left hand side.
- getLiteral() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Returns the literal.
- getLocalName() - Method in class ru.ispras.verilog.parser.elaborator.VerilogVariable
-
- getLocalNode() - Method in class ru.ispras.verilog.parser.elaborator.VerilogVariable
-
- getLowerBit(VerilogRange, ValueProvider) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
- getLowerBit(VerilogRange) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
- getMaxExpression() - Method in class ru.ispras.verilog.parser.model.basis.VerilogMinTypMax
-
Returns the maximal value expression.
- getMinExpression() - Method in class ru.ispras.verilog.parser.model.basis.VerilogMinTypMax
-
Returns the minimal value expression.
- getModuleName() - Method in class ru.ispras.verilog.parser.elaborator.VerilogElaborator
-
Returns the name of the module to be elaborated.
- getModuleName() - Method in class ru.ispras.verilog.parser.model.VerilogInstantiation
-
Returns the module name of the instance.
- getName() - Method in class ru.ispras.verilog.parser.core.AbstractNode
-
Returns the name of the node.
- getName() - Method in class ru.ispras.verilog.parser.elaborator.VerilogDesign
-
Returns the name of the design.
- getName() - Method in class ru.ispras.verilog.parser.elaborator.VerilogParameter
-
- getName() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathItem
-
Returns the instance name of the path item.
- getName() - Method in class ru.ispras.verilog.parser.VerilogDesignBackend
-
Returns the name of the back-end.
- getName() - Method in enum ru.ispras.verilog.parser.VerilogStandard
-
- getName() - Method in class ru.ispras.verilog.parser.VerilogSyntaxBackend
-
Returns the name of the back-end.
- getNode() - Method in class ru.ispras.verilog.parser.elaborator.VerilogContext
-
- getNode() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Returns the expression representation.
- getNode() - Method in class ru.ispras.verilog.parser.model.basis.VerilogReference
-
Returns the node representing the reference.
- getOffset() - Method in class ru.ispras.verilog.parser.elaborator.VerilogDescriptor
-
- getOperation() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Returns the operation node (if the expression is an operation).
- getOperationArity() - Method in enum ru.ispras.verilog.parser.interpreter.VerilogOperations
-
- getOperationId() - Method in enum ru.ispras.verilog.parser.interpreter.VerilogOperations
-
- getOutput() - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Returns the output of the procedure.
- getOutputs() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Returns the destination references of the path description.
- getOutputs() - Method in class ru.ispras.verilog.parser.model.VerilogTableEntry
-
Returns the output signals.
- getParameters() - Method in class ru.ispras.verilog.parser.elaborator.VerilogDesign.Builder
-
- getParameters() - Method in class ru.ispras.verilog.parser.elaborator.VerilogDesign
-
- getParent() - Method in class ru.ispras.verilog.parser.core.AbstractNode
-
Returns the parent of the node.
- getParentBindings() - Method in class ru.ispras.verilog.parser.elaborator.VerilogContext
-
- getParentContext() - Method in class ru.ispras.verilog.parser.elaborator.VerilogContext
-
- getParentNode() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Returns the parent node.
- getPath() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Returns the path to the source-code function.
- getPath() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPath
-
Returns the list of path items.
- getPath() - Method in class ru.ispras.verilog.parser.model.basis.VerilogReference
-
Returns the reference path.
- getPath() - Method in class ru.ispras.verilog.parser.model.VerilogDefineParameter
-
Returns the parameter path.
- getPath() - Method in class ru.ispras.verilog.parser.model.VerilogDisableStatement
-
Returns the path to the object being disabled.
- getPath() - Method in class ru.ispras.verilog.parser.model.VerilogTaskStatement
-
Returns the path to the task.
- getPath() - Method in class ru.ispras.verilog.parser.model.VerilogTriggerStatement
-
Returns the path to the trigger statement.
- getPathItem() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPath
-
Return the first path item of the path.
- getPolarity() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Returns the polarity of the path description.
- getPorts() - Method in class ru.ispras.verilog.parser.model.VerilogModule
-
Returns the signature of the module (i.e., the list of its ports).
- getPorts() - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Returns the signature of the procedure (i.e., the list of its ports).
- getPriority() - Method in enum ru.ispras.verilog.parser.elaborator.VerilogParameter.Type
-
- getProcesses() - Method in class ru.ispras.verilog.parser.elaborator.VerilogDesign
-
Returns the iterator over the design processes.
- getRange() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Returns the range of the element.
- getRange() - Method in class ru.ispras.verilog.parser.model.VerilogInstantiation
-
Returns the range of the instantiation array.
- getReal() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Returns the real value of the literal.
- getReference() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Returns the reference (if the expression is primary).
- getReference(Node) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
- getReferences() - Method in class ru.ispras.verilog.parser.model.VerilogAssignment
-
Returns the l-value (reference) of the assignment.
- getReferences() - Method in class ru.ispras.verilog.parser.model.VerilogPort
-
Returns the port references.
- getReferences() - Method in class ru.ispras.verilog.parser.model.VerilogPulseStyle
-
Returns the references of the pulse style specification.
- getReferences() - Method in class ru.ispras.verilog.parser.model.VerilogShowCancelled
-
Returns the references of the show-cancelled construct.
- getRepeat() - Method in class ru.ispras.verilog.parser.model.basis.VerilogEventControl
-
Returns the repetition number of the event-based control.
- getRhs() - Method in class ru.ispras.verilog.parser.elaborator.VerilogBinding
-
- getRhsExpression() - Method in class ru.ispras.verilog.parser.model.VerilogAssignment
-
Returns the r-value (expression) of the assignment.
- getRightExpression() - Method in class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Returns the right expression of the range.
- getSource() - Method in class ru.ispras.verilog.parser.util.TokenSourceStack
-
- getSourceName() - Method in class ru.ispras.verilog.parser.util.TokenSourceStack
-
- getStatement() - Method in class ru.ispras.verilog.parser.elaborator.VerilogProcess
-
- getStatement() - Method in class ru.ispras.verilog.parser.model.VerilogActivity
-
Returns the statement of the process.
- getStatement() - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatementItem
-
Returns the statement of the case.
- getStatement() - Method in class ru.ispras.verilog.parser.model.VerilogDelayedStatement
-
Returns the statement of the delayed statement.
- getStatement() - Method in class ru.ispras.verilog.parser.model.VerilogIfStatementBranch
-
Returns the branch body.
- getStatement() - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Returns the loop body.
- getStatement() - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Returns the statement of the procedure.
- getStatement() - Method in class ru.ispras.verilog.parser.model.VerilogWaitStatement
-
Returns the statement.
- getStrength() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Returns the strength.
- getStrength() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Returns the charge strength.
- getStrength() - Method in class ru.ispras.verilog.parser.model.VerilogAssign
-
Returns the drive strength.
- getStrength() - Method in class ru.ispras.verilog.parser.model.VerilogInstantiation
-
Returns the strength of the instance's port connections.
- getStrength0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Returns the drive strength for 0.
- getStrength1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Returns the drive strength for 1.
- getString() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Returns the string value of the literal.
- getTag() - Method in class ru.ispras.verilog.parser.core.AbstractNode
-
Returns the tag of the node.
- getThen() - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Returns the child path declaration (only for IF
and IF_NONE
).
- getThenGenerate() - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerate
-
Returns the generate block related to the branch then
.
- getThenStatement() - Method in class ru.ispras.verilog.parser.model.VerilogIfStatement
-
Returns the statement related to the branch then
.
- getTokenNames() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- getTokenNames() - Method in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.additive_operator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.always_construct_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.attribute_assignment_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.attribute_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.attribute_instance_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.attributes_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.begin_block_statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.bitwise_and_operator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.bitwise_or_operator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.bitwise_xor_operator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.block_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.block_item_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.block_variable_array_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.block_variable_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.block_variable_type_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.case_generate_item_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.case_generate_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.case_item_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.case_statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.charge_strength_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.checktime_condition_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.compare_operator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.concatenation_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.continuous_assign_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.continuous_assignment_statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.data_event_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.defparam_assignment_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.delay_control_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.delay_or_event_control_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.delay_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.delay_value_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.delayed_data_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.delayed_reference_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.delayed_statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.description_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.disable_statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.discrete_assignment_statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.drive_strength_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.edge_control_specifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.edge_descriptor_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.edge_indicator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.edge_symbol_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.end_edge_offset_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.equality_operator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.event_array_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.event_based_flag_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.event_control_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.event_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.event_expression_1_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.event_expression_2_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.event_expression_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.event_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.event_trigger_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_0_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_10_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_11_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_12_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_13_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_14_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_1_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_2_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_3_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_4_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_5_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_6_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_7_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_8_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_9_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.expression_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.fork_block_statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.fullskew_timing_check_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.function_call_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.function_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.function_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.function_item_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.function_return_type_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.gate_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.generate_block_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.generate_block_or_null_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.generate_block_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.generate_region_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.genvar_assignment_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.genvar_decl_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.genvar_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.genvar_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.hierarchical_event_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.hierarchical_function_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.hierarchical_identifier_item_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.hierarchical_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.hierarchical_parameter_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.hierarchical_task_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.hold_timing_check_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.if_generate_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.if_statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.initial_construct_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.level_symbol_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.list_of_expressions_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.list_of_mintypmax_expressions_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.list_of_parameter_assignments_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.list_of_port_connections_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.list_of_port_declarations_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.list_of_port_references_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.list_of_ports_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.localparam_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.logical_and_operator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.logical_or_operator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.loop_generate_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.loop_statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.lvalue_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.mintypmax_expression_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.module_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.module_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.module_instance_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.module_instance_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.module_instantiation_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.module_or_generate_item_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.module_parameter_list_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.multiplicative_operator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.net_assignment_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.net_decl_assignment_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.net_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.net_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.net_type_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.nochange_timing_check_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.notifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.null_statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.number_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.pair_of_level_symbols_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.param_assignment_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.parameter_assignment_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.parameter_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.parameter_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.parameter_override_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.parameter_type_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.path_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.path_delay_value_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.path_description_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.period_timing_check_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.port_connection_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.port_decl_assignment_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.port_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.port_expression_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.port_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.port_reference_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.port_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.port_type_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.power_operator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.primary_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.procedural_timing_control_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.pulsestyle_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.range_expression_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.range_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.recovery_timing_check_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.recrem_timing_check_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.reference_event_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.reference_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.reg_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.remain_active_flag_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.removal_timing_check_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.repeat_event_control_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.replication_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.setup_timing_check_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.setuphold_timing_check_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.shift_operator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.showcancelled_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.skew_timing_check_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.source_code_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.specify_block_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.specify_item_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.specify_terminal_descriptor_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.specparam_assignment_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.specparam_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.specparam_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.stamptime_condition_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.start_edge_offset_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.startRule_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.state_dependent_path_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.state_independent_path_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.strength_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.strength_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.string_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.system_function_call_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.system_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.system_task_enable_statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.system_timing_check_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.table_entry_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.task_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.task_enable_statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.task_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.task_item_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.terminal_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.ternary_operator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.threshold_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.timeskew_timing_check_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.timing_check_condition_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.timing_check_event_control_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.timing_check_event_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.timing_check_limit_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.udp_declaration_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.udp_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.udp_item_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.udp_table_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.unary_operator_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.variable_assignment_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.variable_deassignment_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.variable_decl_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.variable_identifier_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.wait_statement_return
-
- getTree() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.width_timing_check_return
-
- getTreeAdaptor() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- getType() - Method in class ru.ispras.verilog.parser.elaborator.VerilogBinding
-
- getType() - Method in class ru.ispras.verilog.parser.elaborator.VerilogParameter
-
- getType() - Method in class ru.ispras.verilog.parser.elaborator.VerilogProcess
-
- getType() - Method in class ru.ispras.verilog.parser.elaborator.VerilogVariable
-
- getType() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Returns the element type.
- getType() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Returns the literal type (INTEGER
, REAL
, or STRING
).
- getType() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Returns the type of the path description.
- getType() - Method in class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Returns the type of the range.
- getType() - Method in class ru.ispras.verilog.parser.model.VerilogActivity
-
Returns the type of the process.
- getType() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Returns the assignment statement type.
- getType() - Method in class ru.ispras.verilog.parser.model.VerilogBlockStatement
-
Returns the type of the block statement (BEGIN
or FORK
).
- getType() - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatement
-
Returns the case statement type.
- getType() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Returns the declaration type.
- getType() - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerateBranch
-
Returns the branch type (THEN
or ELSE
).
- getType() - Method in class ru.ispras.verilog.parser.model.VerilogIfStatementBranch
-
Returns the branch type (THEN
or ELSE
).
- getType() - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Returns the type of the loop.
- getType() - Method in class ru.ispras.verilog.parser.model.VerilogModule
-
Returns the type of the module.
- getType() - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Returns the type of the path declaration.
- getType() - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Returns the type of the procedure.
- getType() - Method in class ru.ispras.verilog.parser.model.VerilogPulseStyle
-
Returns the type of the pulse style specification.
- getType() - Method in class ru.ispras.verilog.parser.model.VerilogShowCancelled
-
Returns the show-cancelled construct type (SHOW
or NO_SHOW
).
- getTypExpression() - Method in class ru.ispras.verilog.parser.model.basis.VerilogMinTypMax
-
Returns the typical value expression.
- getUpperBit(VerilogRange, ValueProvider) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
- getUpperBit(VerilogRange) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
- getUpperTable() - Method in class ru.ispras.verilog.parser.core.AbstractSymbolTable
-
Returns the symbol table of the upper scope.
- getUsedVariables(VerilogAssignment) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
Returns the set of variables used in the RHS of the assignment.
- getValue() - Method in class ru.ispras.verilog.parser.elaborator.VerilogParameter
-
- getValue() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Returns the value node (if the expression is a value).
- getValue(VerilogLiteral) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
- getVariable(NodeVariable) - Method in class ru.ispras.verilog.parser.elaborator.VerilogContext
-
- getVariable() - Method in class ru.ispras.verilog.parser.elaborator.VerilogDescriptor
-
- getVariable() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Returns the variable node (if the expression is a variable).
- getVariable(VerilogReference, ValueProvider) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
- getVariable(VerilogReference) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
- getVariable(VerilogDeclaration, ValueProvider) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
- getVariable(VerilogDeclaration) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
- getVariableName(VerilogDeclaration) - Static method in class ru.ispras.verilog.parser.model.util.ModelUtils
-
- getVariables() - Method in class ru.ispras.verilog.parser.elaborator.VerilogDesign
-
- getXMask() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Returns the X mask of the literal.
- getZMask() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Returns the Z mask of the literal.
- gParent - Variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- GREATER - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- GREATER - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- GREATER - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- GREATER - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- GREATEREQ - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- GREATEREQ - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- GREATEREQ - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- GREATEREQ - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- gVerilogLexer - Variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- identifier() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- identifier_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.identifier_return
-
- if_generate() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- if_generate_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.if_generate_return
-
- if_statement() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- if_statement_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.if_statement_return
-
- IncludeFileFinder - Class in ru.ispras.verilog.parser.util
-
- IncludeFileFinder() - Constructor for class ru.ispras.verilog.parser.util.IncludeFileFinder
-
- INCORRECT_TOKEN - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- INCORRECT_TOKEN - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- INCORRECT_TOKEN - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- INCORRECT_TOKEN - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- info(String, Object...) - Static method in class ru.ispras.verilog.parser.VerilogLogger
-
- initial_construct() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- initial_construct_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.initial_construct_return
-
- instantiateDescriptor(VerilogVariable, Map<String, VerilogDescriptor>, Map<String, VerilogParameter>) - Method in class ru.ispras.verilog.parser.elaborator.VerilogInstantiator
-
- instantiateProcess(Map<String, VerilogDescriptor>, Map<String, VerilogParameter>) - Method in class ru.ispras.verilog.parser.elaborator.VerilogInstantiator
-
- interpret(VerilogStatement, Map<String, Data>) - Static method in class ru.ispras.verilog.parser.interpreter.VerilogInterpreter
-
Interprets the given statement in the given context.
- isActivity() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is ACTIVITY
.
- isAllowed(VerilogStandard) - Method in class ru.ispras.verilog.parser.VerilogFrontend
-
- isAlways() - Method in class ru.ispras.verilog.parser.elaborator.VerilogProcess
-
- isAlways() - Method in class ru.ispras.verilog.parser.model.VerilogActivity
-
Checks whether the process type is ALWAYS
.
- isAssign() - Method in class ru.ispras.verilog.parser.elaborator.VerilogProcess
-
- isAssign() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Checks whether the statement is ASSIGN
.
- isAssign() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is ASSIGN
.
- isAssignment() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is ASSIGNMENT
.
- isAssignStatement() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is ASSIGN_STATEMENT
.
- isAttribute() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is ATTRIBUTE
.
- isAutomatic() - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Checks whether the procedure is automatic.
- isBegin() - Method in class ru.ispras.verilog.parser.model.VerilogBlockStatement
-
Checks whether the statement BEGIN
.
- isBitVector() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Checks whether the literal is BIT_VECTOR
.
- isBlockGenerate() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is BLOCK_GENERATE
.
- isBlocking() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Checks whether the statement is BLOCKING
.
- isBlockStatement() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is BLOCK_STATEMENT
.
- isCase() - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatement
-
Checks whether the statement is CASE
.
- isCaseGenerate() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is CASE_GENERATE
.
- isCaseGenerateItem() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is CASE_GENERATE_ITEM
.
- isCaseStatement() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is CASE_STATEMENT
.
- isCaseStatementItem() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is CASE_STATEMENT_ITEM
.
- isCaseX() - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatement
-
Checks whether the statement is CASEX
.
- isCaseZ() - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatement
-
Checks whether the statement is CASEZ
.
- isCode() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is CODE
.
- isCompliantWith(VerilogStandard) - Method in enum ru.ispras.verilog.parser.VerilogStandard
-
- isConnection() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is PORT_CONNECTION
.
- isDeassign() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Checks whether the statement is DEASSIGN
.
- isDeclaration() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is DECLARATION
.
- isDefined(String) - Method in class ru.ispras.verilog.parser.VerilogFrontend
-
- isDelayedStatement() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is DELAYED_STATEMENT
.
- isDelays() - Method in class ru.ispras.verilog.parser.model.basis.VerilogEventControl
-
Checks whether the control is delay-based.
- isDisableStatement() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is DISABLE_STATEMENT
.
- isElse() - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerateBranch
-
Checks whether the branch is ELSE
.
- isElse() - Method in class ru.ispras.verilog.parser.model.VerilogIfStatementBranch
-
Checks whether the branch is ELSE
.
- isEmpty() - Method in class ru.ispras.verilog.parser.model.basis.VerilogEventControl
-
Checks whether the control is absent.
- isEvent() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Checks whether the declaration is EVENT
.
- isEvents() - Method in class ru.ispras.verilog.parser.model.basis.VerilogEventControl
-
Checks whether the control is event-based.
- isFor() - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Checks whether the loop is FOR
.
- isForce() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Checks whether the statement is FORCE
.
- isForever() - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Checks whether the loop is FOREVER
.
- isFork() - Method in class ru.ispras.verilog.parser.model.VerilogBlockStatement
-
Checks whether the statement FORK
.
- isFull() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Checks whether the path description is FULL
.
- isFunction() - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Checks whether the procedure is FUNCTION
.
- isGatePrimitive() - Method in class ru.ispras.verilog.parser.model.VerilogModule
-
Checks whether the module is GATE_PRIMITIVE
.
- isGenerate() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is GENERATE
.
- isGenvar() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Checks whether the declaration is GENVAR
.
- isHidden() - Method in class ru.ispras.verilog.parser.VerilogFrontend
-
- isHierarchical() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPath
-
Checks whether the path is hierarchical.
- isHighZ0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 0 is HIGHZ
.
- isHighZ1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 1 is HIGHZ
.
- isIf() - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Checks whether the path declaration is IF
.
- isIfGenerate() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is IF_GENERATE
.
- isIfGenerateBranch() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is IF_GENERATE_BRANCH
.
- isIfNone() - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Checks whether the path declaration is IF_NONE
.
- isIfStatement() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is IF_STATEMENT
.
- isIfStatementBranch() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is IF_STATEMENT_BRANCH
.
- isInitial() - Method in class ru.ispras.verilog.parser.elaborator.VerilogProcess
-
- isInitial() - Method in class ru.ispras.verilog.parser.model.VerilogActivity
-
Checks whether the process type is INITIAL
.
- isInout() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Checks whether the declaration is INOUT
.
- isInput() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Checks whether the declaration is INPUT
.
- isInstantiation() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is INSTANTIATION
.
- isInteger() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is INTEGER
.
- isInteger() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Checks whether the literal is INTEGER
.
- isLarge() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the charge strength is LARGE
.
- isLarge0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 0 is LARGE
.
- isLarge1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 1 is LARGE
.
- isLocalparam() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Checks whether the declaration is LOCALPARAM
.
- isLoopGenerate() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is LOOP_GENERATE
.
- isLoopStatement() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is LOOP_STATEMENT
.
- isMacromodule() - Method in class ru.ispras.verilog.parser.model.VerilogModule
-
Checks whether the module is MACROMODULE
.
- isMedium() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the charge strength is MEDIUM
.
- isMedium0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 0 is MEDIUM
.
- isMedium1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 1 is MEDIUM
.
- isMinus() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Checks whether the polarity is MINUS
.
- isMinus() - Method in class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Checks whether the range is MINUS
.
- isModule() - Method in class ru.ispras.verilog.parser.model.VerilogModule
-
Checks whether the module is MODULE
.
- isModule() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is MODULE
.
- isNet() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is a net.
- isNonBlocking() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Checks whether the statement is NON_BLOCKING
.
- isNoShow() - Method in class ru.ispras.verilog.parser.model.VerilogShowCancelled
-
Checks whether the construct is NO_SHOW
.
- isNull() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Checks whether the expression is null.
- isNullStatement() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is NULL_STATEMENT
.
- isNumeric() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is a numeric variable (INTEGER
or REAL
).
- isOnDetect() - Method in class ru.ispras.verilog.parser.model.VerilogPulseStyle
-
Checks whether the pulse style is ON_DETECT
.
- isOnEvent() - Method in class ru.ispras.verilog.parser.model.VerilogPulseStyle
-
Checks whether the pulse style is ON_EVENT
.
- isOperation() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Checks whether the expression is an operation.
- isOutput() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Checks whether the declaration is OUTPUT
.
- isParallel() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Checks whether the path description is PARALLEL
.
- isParam() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Checks whether the declaration is a parameter
(PARAMETER
, SPECPARAM
, or LOCALPARAM
).
- isParameter() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Checks whether the declaration is PARAMETER
.
- isPathDeclaration() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is PATH_DECLARATION
.
- isPlus() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Checks whether the polarity is PLUS
.
- isPlus() - Method in class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Checks whether the range is PLUS
.
- isPort() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Checks whether the declaration is a port (INPUT
, OUTPUT
, or INOUT
).
- isPort() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is PORT
.
- isPortConnection() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is PORT_CONNECTION
.
- isProcedure() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is PROCEDURE
.
- isPull0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 0 is PULL
.
- isPull1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 1 is PULL
.
- isPulseStyle() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is PULSE_STYLE
.
- isRange() - Method in class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Checks whether the range is RANGE
.
- isReal() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is REAL
.
- isReal() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Checks whether the literal is REAL
.
- isRealtime() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is REALTIME
.
- isReference() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Checks whether the expression is a reference.
- isReg() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is REG
.
- isRegister() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is a register.
- isRelease() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Checks whether the statement is RELEASE
.
- isRepeat() - Method in class ru.ispras.verilog.parser.model.basis.VerilogEventControl
-
Checks whether the control is event-based and has the repeat construct.
- isRepeat() - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Checks whether the loop is REPEAT
.
- isRootSource() - Method in class ru.ispras.verilog.parser.util.TokenSourceStack
-
- isScalared() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is scalared.
- isShow() - Method in class ru.ispras.verilog.parser.model.VerilogShowCancelled
-
Checks whether the construct is SHOW
.
- isShowCancelled() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is SHOW_CANCELLED
.
- isSigned() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is signed.
- isSigned() - Method in class ru.ispras.verilog.parser.model.util.Parser.SizeBase
-
Returns the signed/unsigned flag of the literal.
- isSmall() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the charge strength is SMALL
.
- isSmall0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 0 is SMALL
.
- isSmall1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 1 is SMALL
.
- isSpecified() - Method in class ru.ispras.verilog.parser.model.basis.VerilogDelay
-
Checks whether the delay is specified (i.e.
- isSpecified() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the type is specified (something is written in the code).
- isSpecify() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is SPECIFY
.
- isSpecparam() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Checks whether the declaration is SPECPARAMETER
.
- isString() - Method in class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Checks whether the literal is STRING
.
- isStrong0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 0 is STRONG
.
- isStrong1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 1 is STRONG
.
- isSupply0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is SUPPLY0
.
- isSupply0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 0 is SUPPLY
.
- isSupply1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is SUPPLY1
.
- isSupply1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 1 is SUPPLY
.
- isSystem() - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Checks whether the procedure is a system one.
- isTable() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is TABLE
.
- isTableEntry() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is TABLE_ENTRY
.
- isTask() - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Checks whether the procedure is TASK
.
- isTaskStatement() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is TASK_STATEMENT
.
- isTemporal() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is a temporal variable (TIME
or REALTIME
).
- isThen() - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerateBranch
-
Checks whether the branch is THEN
.
- isThen() - Method in class ru.ispras.verilog.parser.model.VerilogIfStatementBranch
-
Checks whether the branch is THEN
.
- isTime() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is TIME
.
- isTransparent() - Method in class ru.ispras.verilog.parser.core.AbstractNode
-
Checks whether the node is transparent (i.e.
- isTri() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is TRI
.
- isTri0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is TRI0
.
- isTri1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is TRI1
.
- isTriand() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is TRIAND
.
- isTriggerStatement() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is TRIGGER_STATEMENT
.
- isTrior() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is TRIOR
.
- isTrireg() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is TRIREG
.
- isUndefined() - Method in class ru.ispras.verilog.parser.model.util.Parser.SizeBase
-
Checks whether size/base information is undefined.
- isUserPrimitive() - Method in class ru.ispras.verilog.parser.model.VerilogModule
-
Checks whether the module is USER_PRIMITIVE
.
- isUsual() - Method in class ru.ispras.verilog.parser.model.basis.VerilogMinTypMax
-
Checks whether the expression is usual.
- isUwire() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is UWIRE
.
- isValue() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Checks whether the expression is a value.
- isVariable() - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Checks whether the expression is a variable.
- isVariable() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Checks whether the declaration is VARIABLE
.
- isVectored() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is vectored.
- isWaitStatement() - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Checks whether the node is WAIT_STATEMENT
.
- isWand() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is WAND
.
- isWeak0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 0 is WEAK
.
- isWeak1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Checks whether the drive strength for 1 is WEAK
.
- isWhile() - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Checks whether the loop is WHILE
.
- isWire() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is WIRE
.
- isWor() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Checks whether the element is WOR
.
- items() - Method in class ru.ispras.verilog.parser.core.AbstractNode
-
- items(Tag) - Method in class ru.ispras.verilog.parser.core.AbstractNode
-
- items(EnumSet<Tag>) - Method in class ru.ispras.verilog.parser.core.AbstractNode
-
- items() - Method in class ru.ispras.verilog.parser.core.AbstractSymbolTable
-
Returns the symbol table's items.
- items(EnumSet<Tag>) - Method in class ru.ispras.verilog.parser.core.AbstractSymbolTable
-
Returns the items whose tags belong to the given set.
- items(Tag) - Method in class ru.ispras.verilog.parser.core.AbstractSymbolTable
-
Returns the items with the given tag.
- items(Tag, Tag) - Method in class ru.ispras.verilog.parser.core.AbstractSymbolTable
-
Returns the items with the given tags.
- items(Tag, Tag, Tag) - Method in class ru.ispras.verilog.parser.core.AbstractSymbolTable
-
Returns the items with the given tags.
- SEMI - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- SEMI - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- SEMI - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- SEMI - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- setAlways() - Method in class ru.ispras.verilog.parser.model.VerilogActivity
-
Sets the process type to ALWAYS
.
- setAssign() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Sets the type of the statement to ASSIGN
.
- setAssignment(VerilogAssignment) - Method in class ru.ispras.verilog.parser.model.VerilogAssign
-
Sets the assignment.
- setAssignment(VerilogAssignment) - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Sets the assignment of the statement (the pair of l- and r-values).
- setAttributes(List<VerilogAttribute>) - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Sets the expression attributes.
- setAttributes(List<VerilogAttribute>) - Method in class ru.ispras.verilog.parser.model.basis.VerilogMinTypMax
-
Sets the expression attributes.
- setAttributes(Collection<VerilogAttribute>) - Method in class ru.ispras.verilog.parser.model.VerilogNode
-
Sets attributes of the node.
- setAutomatic() - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Makes the procedure automatic.
- setBase(int) - Method in class ru.ispras.verilog.parser.model.util.Parser.SizeBase
-
Sets the number system of the literal.
- setBegin() - Method in class ru.ispras.verilog.parser.model.VerilogBlockStatement
-
Sets the type of the statement to BEGIN
.
- setBitSize(int) - Method in class ru.ispras.verilog.parser.model.util.Parser.SizeBase
-
Sets the bit size of the literal.
- setBitsSelection(boolean) - Method in class ru.ispras.verilog.parser.model.basis.VerilogReference
-
Sets the bits selection flag.
- setBlocking() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Sets the type of the statement to BLOCKING
.
- setCase() - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatement
-
Sets the type of the statement to CASE
.
- setCaseX() - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatement
-
Sets the type of the statement to CASEX
.
- setCaseZ() - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatement
-
Sets the type of the statement to CASEZ
.
- setDeassign() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Sets the type of the statement to DEASSIGN
.
- setDeclaration(VerilogProcedure) - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Sets the function declaration (for function calls only).
- setDeclaration(VerilogDeclaration) - Method in class ru.ispras.verilog.parser.model.basis.VerilogReference
-
Sets the declaration (the reference descriptor).
- setDeclaration(VerilogModule) - Method in class ru.ispras.verilog.parser.model.VerilogInstantiation
-
Sets the module declaration.
- setDeclaration(VerilogProcedure) - Method in class ru.ispras.verilog.parser.model.VerilogTaskStatement
-
Sets the task declaration.
- setDelay(VerilogDelay) - Method in class ru.ispras.verilog.parser.model.basis.VerilogEventControl
-
Sets the delay of the delay-based control.
- setDelay(VerilogDelay) - Method in class ru.ispras.verilog.parser.model.VerilogAssign
-
Sets the assignment delay.
- setDelay(VerilogDelay) - Method in class ru.ispras.verilog.parser.model.VerilogInstantiation
-
Sets the delay of the instance's port connections.
- setDelay(VerilogDelay) - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Sets the path delay value (only for SIMPLE
).
- setDescription(VerilogPathDescription) - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Sets the path description (only for SIMPLE
).
- setEdge(VerilogEdge) - Method in class ru.ispras.verilog.parser.model.basis.VerilogEvent
-
Sets the edge of the event.
- setEdge(VerilogEdge) - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Sets the edge type of the path description.
- setElementType(VerilogElementType) - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Sets the type of the declared element.
- setElse() - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerateBranch
-
Sets the branch type to ELSE
.
- setElse() - Method in class ru.ispras.verilog.parser.model.VerilogIfStatementBranch
-
Sets the branch type to ELSE
.
- setElseGenerate(VerilogBlockGenerate) - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerate
-
Sets the generate block related to the else branch.
- setElseStatement(VerilogStatement) - Method in class ru.ispras.verilog.parser.model.VerilogIfStatement
-
Sets the statement related to the branch else
.
- setEvent() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Sets the type of the statement to EVENT
.
- setEventControl(VerilogEventControl) - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Sets the control of the statement (the delay or event).
- setEventControl(VerilogEventControl) - Method in class ru.ispras.verilog.parser.model.VerilogDelayedStatement
-
Sets the delay of the delayed statement.
- setEvents(List<VerilogEvent>) - Method in class ru.ispras.verilog.parser.model.basis.VerilogEventControl
-
Sets the events of the event-based control.
- setEvents(List<VerilogEvent>) - Method in class ru.ispras.verilog.parser.model.basis.VerilogRepeatEvents
-
Sets a list of events to be repeated.
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.basis.VerilogEvent
-
Sets the expression of the event.
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Sets the data source expression of the path description.
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathItem
-
Sets the instance index of the path item.
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.basis.VerilogRepeatEvents
-
Sets a repeat count expression.
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.VerilogAttribute
-
Sets the expression of the attribute.
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.VerilogCaseGenerate
-
Sets the case selection expression.
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatement
-
Sets the case selection expression.
- setExpression(VerilogMinTypMax) - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Sets the expression representing the initial value.
- setExpression(VerilogMinTypMax) - Method in class ru.ispras.verilog.parser.model.VerilogDefineParameter
-
Sets the parameter expression.
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerate
-
Sets the condition.
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.VerilogIfStatement
-
Sets the condition.
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.VerilogLoopGenerate
-
Sets the continue condition of the loop.
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Sets the expression of the loop.
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Sets the condition of the path declaration (only for IF
).
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.VerilogPortConnection
-
Sets the expression connected to the port.
- setExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.VerilogWaitStatement
-
Sets a wait expression.
- setFileName(String) - Method in class ru.ispras.verilog.parser.model.VerilogCode
-
Sets the name of the source code file.
- setFor() - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Sets the type of loop to FOR
.
- setForce() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Sets the type of the statement to FORCE
.
- setForever() - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Sets the type of loop to FOREVER
.
- setFork() - Method in class ru.ispras.verilog.parser.model.VerilogBlockStatement
-
Sets the type of the statement to FORK
.
- setFrontend(VerilogFrontend) - Method in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
Sets the Verilog front-end.
- setFull() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Sets the path description type to FULL
.
- setFunction() - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Sets the type of the procedure to FUNCTION
.
- setGatePrimitive() - Method in class ru.ispras.verilog.parser.model.VerilogModule
-
Sets the type of the module to GATE_PRIMITIVE
.
- setGenerate(VerilogBlockGenerate) - Method in class ru.ispras.verilog.parser.model.VerilogCaseGenerateItem
-
Sets the generate block of the case.
- setGenerate(VerilogBlockGenerate) - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerateBranch
-
Sets the branch body.
- setGenerate(VerilogBlockGenerate) - Method in class ru.ispras.verilog.parser.model.VerilogLoopGenerate
-
Sets the loop body.
- setGenvar() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Sets the type of the statement to GENVAR
.
- setHighZ0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 0 to HIGHZ
.
- setHighZ1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 1 to HIGHZ
.
- setIf() - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Sets the path declaration type to IF
.
- setIfNone() - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Sets the path declaration type to IF_NONE
.
- setInitial() - Method in class ru.ispras.verilog.parser.model.VerilogActivity
-
Sets the process type to INITIAL
.
- setInitialization(VerilogAssignment) - Method in class ru.ispras.verilog.parser.model.VerilogLoopGenerate
-
Sets the initialization assignment of the loop.
- setInitialization(VerilogAssignment) - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Sets the initialization assignment of the FOR
loop.
- setInout() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Sets the type of the statement to INOUT
.
- setInput() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Sets the type of the statement to INPUT
.
- setInteger() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to INTEGER
.
- setIteration(VerilogAssignment) - Method in class ru.ispras.verilog.parser.model.VerilogLoopGenerate
-
Sets the iteration assignment of the loop.
- setIteration(VerilogAssignment) - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Sets the iteration assignment of the FOR
loop.
- setLarge() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the charge strength to LARGE
.
- setLarge0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 0 to LARGE
.
- setLarge1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 1 to LARGE
.
- setLastParentToken(Token) - Method in class ru.ispras.verilog.parser.util.TokenSourceStack
-
- setLastParentToken(int, Token) - Method in class ru.ispras.verilog.parser.util.TokenSourceStack
-
- setLeftExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Sets the left expression of the range.
- setLocalparam() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Sets the type of the statement to LOCALPARAM
.
- setMacromodule() - Method in class ru.ispras.verilog.parser.model.VerilogModule
-
Sets the type of the module to MACROMODULE
.
- setMaxExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.basis.VerilogMinTypMax
-
Sets the maximal value expression.
- setMedium() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the charge strength to MEDIUM
.
- setMedium0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 0 to MEDIUM
.
- setMedium1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 1 to MEDIUM
.
- setMinExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.basis.VerilogMinTypMax
-
Sets the minimal value expression.
- setMinTypMaxExpression(VerilogMinTypMax) - Method in class ru.ispras.verilog.parser.model.basis.VerilogMinTypMax
-
Set the minimal, the typical, and the maximal expressions.
- setMinus() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Sets the path description polarity to MINUS
.
- setMinus() - Method in class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Sets the range type to MINUS
.
- setModule() - Method in class ru.ispras.verilog.parser.model.VerilogModule
-
Sets the type of the module to MODULE
.
- setModuleName(String) - Method in class ru.ispras.verilog.parser.elaborator.VerilogElaborator
-
Sets the name of the module to be elaborated.
- setModuleName(String) - Method in class ru.ispras.verilog.parser.model.VerilogInstantiation
-
- setName(String) - Method in class ru.ispras.verilog.parser.core.AbstractNode
-
Sets the name of the node.
- setName(String) - Method in class ru.ispras.verilog.parser.elaborator.VerilogDesign.Builder
-
- setName(String) - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathItem
-
Sets the instance name of the path item.
- setNode(Node) - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Sets the original representation of the expression and resets the elaborated representation.
- setNode(Node) - Method in class ru.ispras.verilog.parser.model.basis.VerilogReference
-
Sets the node representation of the reference.
- setNonBlocking() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Sets the type of the statement to NON_BLOCKING
.
- setNoShow() - Method in class ru.ispras.verilog.parser.model.VerilogShowCancelled
-
Sets the construct type to NO_SHOW
.
- setOnDetect() - Method in class ru.ispras.verilog.parser.model.VerilogPulseStyle
-
Sets a pulse style type to ON_DETECT
.
- setOnEvent() - Method in class ru.ispras.verilog.parser.model.VerilogPulseStyle
-
Sets a pulse style type to ON_EVENT
.
- setOutput() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Sets the type of the statement to OUTPUT
.
- setOutput(String, VerilogElementType) - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Sets the return value type of the procedure and declares the output.
- setOutput(VerilogDeclaration) - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Set the output from the declaration.
- setParallel() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Sets the path description type to PARALLEL
.
- setParameter() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Sets the type of the statement to PARAMETER
.
- setParent(AbstractNode<Tag>) - Method in class ru.ispras.verilog.parser.core.AbstractNode
-
Sets the parent of the node.
- setPath(VerilogPath) - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Sets a path to the source-code function.
- setPath(VerilogPath) - Method in class ru.ispras.verilog.parser.model.basis.VerilogReference
-
Sets the reference path.
- setPath(VerilogPath) - Method in class ru.ispras.verilog.parser.model.VerilogDefineParameter
-
Sets the parameter path.
- setPath(VerilogPath) - Method in class ru.ispras.verilog.parser.model.VerilogDisableStatement
-
Sets the path to the object being disabled.
- setPath(VerilogPath) - Method in class ru.ispras.verilog.parser.model.VerilogTaskStatement
-
Sets the path of the task.
- setPath(VerilogPath) - Method in class ru.ispras.verilog.parser.model.VerilogTriggerStatement
-
Sets the path of the trigger statement.
- setPlus() - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Sets the path description polarity to PLUS
.
- setPlus() - Method in class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Sets the range type to PLUS
.
- setPolarity(VerilogPathDescription.Polarity) - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Sets the polarity of the path description.
- setPull0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 0 to PULL
.
- setPull1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 1 to PULL
.
- setRange(VerilogRange) - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets a range of the element.
- setRange() - Method in class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Sets the range type to RANGE
.
- setRange(VerilogRange) - Method in class ru.ispras.verilog.parser.model.VerilogInstantiation
-
Sets the range of the instantiation array.
- setReal() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to REAL
.
- setRealtime() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to REALTIME
.
- setRedefinitionHandler(ErrorHandler<Tag>) - Method in class ru.ispras.verilog.parser.core.AbstractNode
-
Sets the redefinition handler.
- setReference(VerilogReference) - Method in class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Sets the reference.
- setReg() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to REG
.
- setRelease() - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Sets the type of the statement to RELEASE
.
- setRepeat(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.basis.VerilogEventControl
-
Sets the number of repetitions of the event-based control.
- setRepeat() - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Sets the type of loop to REPEAT
.
- setRepeatEvents(VerilogRepeatEvents) - Method in class ru.ispras.verilog.parser.model.basis.VerilogEventControl
-
Sets the number of repetitions and the events of the event-based control.
- setRhsExpression(VerilogMinTypMax) - Method in class ru.ispras.verilog.parser.model.VerilogAssignment
-
Sets the r-value (expression) of the assignment.
- setRightExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Sets the right expression of the range.
- setScalared() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the scalared property.
- setShow() - Method in class ru.ispras.verilog.parser.model.VerilogShowCancelled
-
Sets the construct type to SHOW
.
- setSigned() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the signed property.
- setSigned(boolean) - Method in class ru.ispras.verilog.parser.model.util.Parser.SizeBase
-
Sets the signed/unsigned flag of the literal.
- setSmall() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the charge strength to SMALL
.
- setSmall0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 0 to SMALL
.
- setSmall1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 1 to SMALL
.
- setSpecparam() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Sets the type of the statement to SPECPARAM
.
- setStatement(VerilogStatement) - Method in class ru.ispras.verilog.parser.model.VerilogActivity
-
Sets the statement to the process.
- setStatement(VerilogStatement) - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatementItem
-
Sets the statement of the case.
- setStatement(VerilogStatement) - Method in class ru.ispras.verilog.parser.model.VerilogDelayedStatement
-
Sets the statement of the delayed statement.
- setStatement(VerilogStatement) - Method in class ru.ispras.verilog.parser.model.VerilogIfStatementBranch
-
Sets the branch body.
- setStatement(VerilogStatement) - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Sets the loop body.
- setStatement(VerilogStatement) - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Sets the statement of the procedure.
- setStatement(VerilogStatement) - Method in class ru.ispras.verilog.parser.model.VerilogWaitStatement
-
Sets the statement.
- setStrength(VerilogStrength) - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the strength.
- setStrength(VerilogStrength.Type) - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the charge strength.
- setStrength(VerilogStrength) - Method in class ru.ispras.verilog.parser.model.VerilogAssign
-
Sets the drive strength.
- setStrength(VerilogStrength) - Method in class ru.ispras.verilog.parser.model.VerilogInstantiation
-
Sets the strength of the instance's port connections.
- setStrength0(VerilogStrength.Type) - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 0.
- setStrength1(VerilogStrength.Type) - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 1.
- setStrong0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 0 to STRONG
.
- setStrong1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 1 to STRONG
.
- setSupply0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to SUPPLY0
.
- setSupply0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 0 to SUPLLY
.
- setSupply1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to SUPPLY1
.
- setSupply1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 1 to SUPPLY
.
- setTag(Tag) - Method in class ru.ispras.verilog.parser.core.AbstractNode
-
Sets the tag of the node.
- setTask() - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Sets the type of the procedure to TASK
.
- setThen() - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerateBranch
-
Sets the branch type to THEN
.
- setThen() - Method in class ru.ispras.verilog.parser.model.VerilogIfStatementBranch
-
Sets the branch type to THEN
.
- setThen(VerilogPathDeclaration) - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Sets the child path declaration (only for IF
).
- setThenGenerate(VerilogBlockGenerate) - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerate
-
Sets the generate block related to the branch then
.
- setThenStatement(VerilogStatement) - Method in class ru.ispras.verilog.parser.model.VerilogIfStatement
-
Sets the statement related to the branch then
.
- setTime() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to TIME
.
- setTreeAdaptor(TreeAdaptor) - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- setTri() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to TRI
.
- setTri0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to TRI0
.
- setTri1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to TRI1
.
- setTriand() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to TRIAND
.
- setTrior() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to TRIOR
.
- setTrireg() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to TRIREG
.
- setType(VerilogElementType.Type) - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type.
- setType(VerilogPathDescription.Type) - Method in class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Sets the type of the path description.
- setType(VerilogRange.Type) - Method in class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Sets the type of the range.
- setType(VerilogActivity.Type) - Method in class ru.ispras.verilog.parser.model.VerilogActivity
-
Sets the type of the process.
- setType(VerilogAssignStatement.Type) - Method in class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Sets the assignment statement type.
- setType(VerilogBlockStatement.Type) - Method in class ru.ispras.verilog.parser.model.VerilogBlockStatement
-
Sets the type of the block statement.
- setType(VerilogCaseStatement.Type) - Method in class ru.ispras.verilog.parser.model.VerilogCaseStatement
-
Sets the case statement type.
- setType(VerilogDeclaration.Type) - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Sets the declaration type.
- setType(VerilogIfGenerateBranch.Type) - Method in class ru.ispras.verilog.parser.model.VerilogIfGenerateBranch
-
Sets the branch type.
- setType(VerilogIfStatementBranch.Type) - Method in class ru.ispras.verilog.parser.model.VerilogIfStatementBranch
-
Sets the branch type.
- setType(VerilogLoopStatement.Type) - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Sets the type of the loop.
- setType(VerilogModule.Type) - Method in class ru.ispras.verilog.parser.model.VerilogModule
-
Sets the type of the module.
- setType(VerilogPathDeclaration.Type) - Method in class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Sets the type of the path declaration.
- setType(VerilogProcedure.Type) - Method in class ru.ispras.verilog.parser.model.VerilogProcedure
-
Sets the type of the procedure.
- setType(VerilogPulseStyle.Type) - Method in class ru.ispras.verilog.parser.model.VerilogPulseStyle
-
Sets the type of the pulse style specification.
- setType(VerilogShowCancelled.Type) - Method in class ru.ispras.verilog.parser.model.VerilogShowCancelled
-
Sets the show-cancelled construct type (SHOW
or NO_SHOW
).
- setTypExpression(VerilogExpression) - Method in class ru.ispras.verilog.parser.model.basis.VerilogMinTypMax
-
Sets the typical value expression.
- SETUP_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- SETUP_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- SETUP_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- SETUP_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- setup_timing_check() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- setup_timing_check_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.setup_timing_check_return
-
- SETUPHOLD_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- SETUPHOLD_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- SETUPHOLD_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- SETUPHOLD_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- setuphold_timing_check() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- setuphold_timing_check_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.setuphold_timing_check_return
-
- setUpperTable(AbstractSymbolTable<Tag>) - Method in class ru.ispras.verilog.parser.core.AbstractSymbolTable
-
Sets the symbol table of the upper scope.
- setUserPrimitive() - Method in class ru.ispras.verilog.parser.model.VerilogModule
-
Sets the type of the module to USER_PRIMITIVE
.
- setUwire() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to UWIRE
.
- setVariable() - Method in class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Sets the type of the statement to VARIABLE
.
- setVectored() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the vectored property.
- setVerbose(boolean) - Method in class ru.ispras.verilog.parser.VerilogLogger
-
- setWand() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to WAND
.
- setWeak0() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 0 to WEAK
.
- setWeak1() - Method in class ru.ispras.verilog.parser.model.basis.VerilogStrength
-
Sets the drive strength for 1 to WEAK
.
- setWhile() - Method in class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Sets the type of loop to WHILE
.
- setWire() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to WIRE
.
- setWor() - Method in class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Sets the element type to WOR
.
- SHARP - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- SHARP - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- SHARP - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- SHARP - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- shift_operator() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- shift_operator_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.shift_operator_return
-
- showcancelled_declaration() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- showcancelled_declaration_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.showcancelled_declaration_return
-
- SIZE - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- SIZE - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- SIZE - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- SIZE - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- SizeBase(int, boolean, int) - Constructor for class ru.ispras.verilog.parser.model.util.Parser.SizeBase
-
Constructs a size/base object.
- SizeBase() - Constructor for class ru.ispras.verilog.parser.model.util.Parser.SizeBase
-
Constructs a default size/base object.
- SKEW_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- SKEW_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- SKEW_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- SKEW_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- skew_timing_check() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- skew_timing_check_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.skew_timing_check_return
-
- SL_COMMENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- SL_COMMENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- SL_COMMENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- SL_COMMENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- source - Variable in class ru.ispras.verilog.parser.util.TokenSourceStack.TokenSourceEntry
-
- source_code() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- source_code_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.source_code_return
-
- SPACE - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- SPACE - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- SPACE - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- SPACE - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- specialStateTransition(int, IntStream) - Method in class ru.ispras.verilog.parser.grammar.VerilogLexer.DFA11
-
- specialStateTransition(int, IntStream) - Method in class ru.ispras.verilog.parser.grammar.VerilogLexer.DFA26
-
- specialStateTransition(int, IntStream) - Method in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor.DFA11
-
- specialStateTransition(int, IntStream) - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.DFA135
-
- specialStateTransition(int, IntStream) - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.DFA158
-
- specialStateTransition(int, IntStream) - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.DFA232
-
- specialStateTransition(int, IntStream) - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.DFA240
-
- specialStateTransition(int, IntStream) - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.DFA61
-
- specialStateTransition(int, IntStream) - Method in class ru.ispras.verilog.parser.grammar.VerilogParser.DFA94
-
- specialStateTransition(int, IntStream) - Method in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.DFA47
-
- specify_block() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- specify_block_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.specify_block_return
-
- specify_item() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- specify_item_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.specify_item_return
-
- specify_terminal_descriptor() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- specify_terminal_descriptor_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.specify_terminal_descriptor_return
-
- specparam_assignment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- specparam_assignment_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.specparam_assignment_return
-
- specparam_declaration() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- specparam_declaration_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.specparam_declaration_return
-
- specparam_identifier() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- specparam_identifier_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.specparam_identifier_return
-
- stamptime_condition() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- stamptime_condition_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.stamptime_condition_return
-
- STAR - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- STAR - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- STAR - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- STAR - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- start(VerilogDesign) - Method in class ru.ispras.verilog.parser.backends.design.typecast.VerilogTypeCaster
-
- start() - Method in class ru.ispras.verilog.parser.core.TreeWalker
-
Starts DFS traversal.
- start(VerilogNode) - Method in class ru.ispras.verilog.parser.elaborator.VerilogElaborator
-
- start(VerilogDesign) - Method in class ru.ispras.verilog.parser.sample.VerilogDesignPrinter
-
- start(VerilogDesign) - Method in class ru.ispras.verilog.parser.VerilogDesignBackend
-
Processes the elaborated design.
- start(VerilogDesign) - Method in class ru.ispras.verilog.parser.VerilogDesignBackends
-
Processes the elaborated design.
- start(List<String>) - Method in class ru.ispras.verilog.parser.VerilogFrontend
-
- start(String[]) - Method in class ru.ispras.verilog.parser.VerilogFrontend
-
- start(VerilogNode) - Method in class ru.ispras.verilog.parser.VerilogSyntaxBackend
-
Processes the abstract syntax tree (AST).
- start(VerilogNode) - Method in class ru.ispras.verilog.parser.VerilogSyntaxBackends
-
Processes the abstract syntax tree (AST).
- start(String[]) - Method in class ru.ispras.verilog.parser.VerilogTranslator
-
Launches the Verilog translator.
- start_edge_offset() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- start_edge_offset_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.start_edge_offset_return
-
- startBuilder(CommonTreeNodeStream) - Method in class ru.ispras.verilog.parser.VerilogFrontend
-
- startBuilder(CommonTree) - Method in class ru.ispras.verilog.parser.VerilogFrontend
-
- startLexer(List<String>) - Method in class ru.ispras.verilog.parser.VerilogFrontend
-
- startParser(CommonTokenStream) - Method in class ru.ispras.verilog.parser.VerilogFrontend
-
- startParser(TokenSource) - Method in class ru.ispras.verilog.parser.VerilogFrontend
-
- startRule() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- startRule() - Method in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- startRule_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.startRule_return
-
- startSublexer(CharStream) - Method in class ru.ispras.verilog.parser.VerilogFrontend
-
- stat() - Static method in class ru.ispras.verilog.parser.VerilogLogger
-
- state_dependent_path_declaration() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- state_dependent_path_declaration_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.state_dependent_path_declaration_return
-
- state_independent_path_declaration() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- state_independent_path_declaration_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.state_independent_path_declaration_return
-
- statement() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- statement_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.statement_return
-
- strength() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- strength_identifier() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- strength_identifier_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.strength_identifier_return
-
- strength_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.strength_return
-
- STRING - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- STRING - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- STRING - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- string() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- STRING - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- string_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.string_return
-
- synpred10_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred10_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred110_VerilogTreeBuilder() - Method in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- synpred110_VerilogTreeBuilder_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- synpred11_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred11_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred12_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred12_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred13_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred13_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred145_VerilogTreeBuilder() - Method in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- synpred145_VerilogTreeBuilder_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- synpred14_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred14_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred15_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred15_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred16_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred16_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred17_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred17_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred1_VerilogLexer() - Method in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- synpred1_VerilogLexer_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- synpred1_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred1_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred2_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred2_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred3_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred3_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred4_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred4_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred5_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred5_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred6_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred6_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred7_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred7_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred8_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred8_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred9_VerilogParser() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- synpred9_VerilogParser_fragment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- system_function_call() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- system_function_call_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.system_function_call_return
-
- SYSTEM_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- SYSTEM_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- SYSTEM_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- SYSTEM_IDENT - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
-
- system_identifier() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- system_identifier_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.system_identifier_return
-
- system_task_enable_statement() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- system_task_enable_statement_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.system_task_enable_statement_return
-
- system_timing_check() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- system_timing_check_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.system_timing_check_return
-
- validTypes(Data...) - Method in enum ru.ispras.verilog.parser.interpreter.VerilogOperations
-
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.core.AbstractNode.NodeKind
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.core.NodeVisitor.Result
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.elaborator.VerilogBinding.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.elaborator.VerilogParameter.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.elaborator.VerilogProcess.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.elaborator.VerilogVariable.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.interpreter.VerilogOperations
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogEdge
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogElementType.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogLiteral.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogPathDescription.Polarity
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogPathDescription.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogRange.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogStrength.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogActivity.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogAssignStatement.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogBlockStatement.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogCaseStatement.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogDeclaration.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogIfGenerateBranch.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogIfStatementBranch.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogLoopStatement.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogModule.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogNode.Tag
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogPathDeclaration.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogProcedure.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogPulseStyle.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.model.VerilogShowCancelled.Type
-
Returns the enum constant of this type with the specified name.
- valueOf(String) - Static method in enum ru.ispras.verilog.parser.VerilogStandard
-
Returns the enum constant of this type with the specified name.
- values() - Static method in enum ru.ispras.verilog.parser.core.AbstractNode.NodeKind
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.core.NodeVisitor.Result
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.elaborator.VerilogBinding.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.elaborator.VerilogParameter.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.elaborator.VerilogProcess.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.elaborator.VerilogVariable.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.interpreter.VerilogOperations
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogEdge
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogElementType.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogLiteral.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogPathDescription.Polarity
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogPathDescription.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogRange.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.basis.VerilogStrength.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogActivity.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogAssignStatement.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogBlockStatement.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogCaseStatement.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogDeclaration.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogIfGenerateBranch.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogIfStatementBranch.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogLoopStatement.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogModule.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogNode.Tag
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogPathDeclaration.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogProcedure.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogPulseStyle.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.model.VerilogShowCancelled.Type
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- values() - Static method in enum ru.ispras.verilog.parser.VerilogStandard
-
Returns an array containing the constants of this enum type, in
the order they are declared.
- variable_assignment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- variable_assignment_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.variable_assignment_return
-
- variable_deassignment() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- variable_deassignment_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.variable_deassignment_return
-
- variable_decl() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- variable_decl_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.variable_decl_return
-
- variable_identifier() - Method in class ru.ispras.verilog.parser.grammar.VerilogParser
-
- variable_identifier_return() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser.variable_identifier_return
-
- verbose(boolean) - Static method in class ru.ispras.verilog.parser.VerilogLogger
-
- VerilogActivity - Class in ru.ispras.verilog.parser.model
-
- VerilogActivity(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogActivity
-
Creates a process.
- VerilogActivity(VerilogActivity, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogActivity
-
Creates a copy of the process.
- VerilogActivity.Type - Enum in ru.ispras.verilog.parser.model
-
- VerilogAssign - Class in ru.ispras.verilog.parser.model
-
VerilogAssign
represents continuous assignments (assign
).
- VerilogAssign(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogAssign
-
Constructs a continuous assignment.
- VerilogAssign(VerilogAssign, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogAssign
-
Creates a copy of the continuous assignment.
- VerilogAssignment - Class in ru.ispras.verilog.parser.model
-
- VerilogAssignment(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogAssignment
-
Creates an assignment.
- VerilogAssignment(VerilogAssignment, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogAssignment
-
Creates a copy of the assignment.
- VerilogAssignStatement - Class in ru.ispras.verilog.parser.model
-
- VerilogAssignStatement(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Creates an assignment statement.
- VerilogAssignStatement(VerilogAssignStatement, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogAssignStatement
-
Creates a copy of the assignment statement.
- VerilogAssignStatement.Type - Enum in ru.ispras.verilog.parser.model
-
- VerilogAttribute - Class in ru.ispras.verilog.parser.model
-
- VerilogAttribute(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogAttribute
-
Creates an attribute.
- VerilogAttribute(VerilogAttribute, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogAttribute
-
Creates a copy of the attribute.
- VerilogBinding - Class in ru.ispras.verilog.parser.elaborator
-
- VerilogBinding(VerilogBinding.Type, VerilogVariable, Node) - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogBinding
-
- VerilogBinding.Type - Enum in ru.ispras.verilog.parser.elaborator
-
- VerilogBlockGenerate - Class in ru.ispras.verilog.parser.model
-
- VerilogBlockGenerate(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogBlockGenerate
-
Creates a generate block.
- VerilogBlockGenerate(VerilogBlockGenerate, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogBlockGenerate
-
Creates a copy of the generate block.
- VerilogBlockStatement - Class in ru.ispras.verilog.parser.model
-
- VerilogBlockStatement(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogBlockStatement
-
Creates a block statement.
- VerilogBlockStatement(VerilogBlockStatement, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogBlockStatement
-
Creates a copy of the block statement.
- VerilogBlockStatement.Type - Enum in ru.ispras.verilog.parser.model
-
- VerilogCalculator - Class in ru.ispras.verilog.parser.interpreter
-
- VerilogCallCollector - Class in ru.ispras.verilog.parser.elaborator
-
VerilogCallCollector
collects information on function calls and
replaces function calls with newly created return-value variables.
- VerilogCallCollector() - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogCallCollector
-
- VerilogCaseGenerate - Class in ru.ispras.verilog.parser.model
-
- VerilogCaseGenerate(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogCaseGenerate
-
Creates a generate case construct.
- VerilogCaseGenerate(VerilogCaseGenerate, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogCaseGenerate
-
Creates a copy of the generate case construct.
- VerilogCaseGenerateItem - Class in ru.ispras.verilog.parser.model
-
- VerilogCaseGenerateItem(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogCaseGenerateItem
-
Creates a generate case item.
- VerilogCaseGenerateItem(VerilogCaseGenerateItem, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogCaseGenerateItem
-
Creates a copy of the generate case item.
- VerilogCaseStatement - Class in ru.ispras.verilog.parser.model
-
- VerilogCaseStatement(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogCaseStatement
-
Creates a case statement.
- VerilogCaseStatement(VerilogCaseStatement, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogCaseStatement
-
Creates a copy of the case statement.
- VerilogCaseStatement.Type - Enum in ru.ispras.verilog.parser.model
-
- VerilogCaseStatementItem - Class in ru.ispras.verilog.parser.model
-
- VerilogCaseStatementItem(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogCaseStatementItem
-
Creates a case item.
- VerilogCaseStatementItem(VerilogCaseStatementItem, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogCaseStatementItem
-
Creates a copy of the case item.
- VerilogCode - Class in ru.ispras.verilog.parser.model
-
- VerilogCode() - Constructor for class ru.ispras.verilog.parser.model.VerilogCode
-
Creates a source code node.
- VerilogCode(VerilogCode) - Constructor for class ru.ispras.verilog.parser.model.VerilogCode
-
Creates a copy of the source code node.
- VerilogContext - Class in ru.ispras.verilog.parser.elaborator
-
- VerilogContext() - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogContext
-
- VerilogContext(VerilogContext) - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogContext
-
- VerilogDeclaration - Class in ru.ispras.verilog.parser.model
-
- VerilogDeclaration(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Creates a declaration.
- VerilogDeclaration(VerilogDeclaration, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogDeclaration
-
Creates a copy of the declaration.
- VerilogDeclaration.Type - Enum in ru.ispras.verilog.parser.model
-
- VerilogDefineParameter - Class in ru.ispras.verilog.parser.model
-
VerilogAssign
represents parameter definition statements (defparam
).
- VerilogDefineParameter(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogDefineParameter
-
Constructs a parameter definition statement.
- VerilogDefineParameter(VerilogDefineParameter, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogDefineParameter
-
Constructs a copy of the parameter definition statement.
- VerilogDelay - Class in ru.ispras.verilog.parser.model.basis
-
- VerilogDelay() - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogDelay
-
Creates an empty delay object.
- VerilogDelay(VerilogDelay) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogDelay
-
Creates a copy of the delay object.
- VerilogDelayedStatement - Class in ru.ispras.verilog.parser.model
-
- VerilogDelayedStatement(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogDelayedStatement
-
Creates a delayed statement.
- VerilogDelayedStatement(VerilogDelayedStatement, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogDelayedStatement
-
Creates a delayed statement.
- VerilogDescriptor - Class in ru.ispras.verilog.parser.elaborator
-
- VerilogDescriptor(VerilogVariable, VerilogDeclaration) - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogDescriptor
-
- VerilogDesign - Class in ru.ispras.verilog.parser.elaborator
-
- VerilogDesign.Builder - Class in ru.ispras.verilog.parser.elaborator
-
- VerilogDesignBackend - Class in ru.ispras.verilog.parser
-
- VerilogDesignBackend(String) - Constructor for class ru.ispras.verilog.parser.VerilogDesignBackend
-
Creates a back-end.
- VerilogDesignBackends - Class in ru.ispras.verilog.parser
-
- VerilogDesignBackends() - Constructor for class ru.ispras.verilog.parser.VerilogDesignBackends
-
- VerilogDesignPrinter - Class in ru.ispras.verilog.parser.sample
-
- VerilogDesignPrinter(String) - Constructor for class ru.ispras.verilog.parser.sample.VerilogDesignPrinter
-
- VerilogDisableStatement - Class in ru.ispras.verilog.parser.model
-
- VerilogDisableStatement(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogDisableStatement
-
Creates a disable statement.
- VerilogDisableStatement(VerilogDisableStatement, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogDisableStatement
-
Creates a copy of the disable statement.
- VerilogEdge - Enum in ru.ispras.verilog.parser.model.basis
-
VerilogEdge
represents signal edge types (positive, negative, or undefined).
- VerilogElaborator - Class in ru.ispras.verilog.parser.elaborator
-
- VerilogElaborator(String) - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogElaborator
-
Creates an elaboration engine.
- VerilogElaborator(String, String) - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogElaborator
-
Creates an elaboration engine.
- VerilogElementType - Class in ru.ispras.verilog.parser.model.basis
-
- VerilogElementType() - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Creates an element type.
- VerilogElementType(VerilogElementType) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogElementType
-
Creates a copy of the element type.
- VerilogElementType.Type - Enum in ru.ispras.verilog.parser.model.basis
-
- VerilogEmptyVisitor - Class in ru.ispras.verilog.parser.walker
-
This class implements an empty Verilog node visitor.
- VerilogEmptyVisitor() - Constructor for class ru.ispras.verilog.parser.walker.VerilogEmptyVisitor
-
- VerilogEvent - Class in ru.ispras.verilog.parser.model.basis
-
- VerilogEvent() - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogEvent
-
Creates an event.
- VerilogEvent(VerilogEvent) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogEvent
-
Creates a copy of the event.
- VerilogEventControl - Class in ru.ispras.verilog.parser.model.basis
-
- VerilogEventControl() - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogEventControl
-
Creates an event control.
- VerilogEventControl(VerilogEventControl) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogEventControl
-
Creates a copy of the event control.
- VerilogExpression - Class in ru.ispras.verilog.parser.model.basis
-
- VerilogExpression() - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Creates a null expression.
- VerilogExpression(Node) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Creates an expression with the given syntax.
- VerilogExpression(VerilogExpression) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogExpression
-
Creates a copy of the expression.
- VerilogFrontend - Class in ru.ispras.verilog.parser
-
- VerilogFrontend() - Constructor for class ru.ispras.verilog.parser.VerilogFrontend
-
- VerilogGenerate - Class in ru.ispras.verilog.parser.model
-
- VerilogGenerate(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogGenerate
-
Creates a generate construct.
- VerilogGenerate(VerilogGenerate, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogGenerate
-
Creates a copy of the generate construct.
- VerilogIfGenerate - Class in ru.ispras.verilog.parser.model
-
- VerilogIfGenerate(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogIfGenerate
-
Creates a if-then-else generate construct.
- VerilogIfGenerate(VerilogIfGenerate, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogIfGenerate
-
Creates a if-then-else generate construct.
- VerilogIfGenerateBranch - Class in ru.ispras.verilog.parser.model
-
- VerilogIfGenerateBranch(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogIfGenerateBranch
-
Creates an if generate branch.
- VerilogIfGenerateBranch(VerilogIfGenerateBranch.Type, VerilogBlockGenerate, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogIfGenerateBranch
-
Creates an if generate branch.
- VerilogIfGenerateBranch(VerilogIfGenerateBranch, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogIfGenerateBranch
-
Creates a copy of the if generate branch.
- VerilogIfGenerateBranch.Type - Enum in ru.ispras.verilog.parser.model
-
- VerilogIfStatement - Class in ru.ispras.verilog.parser.model
-
- VerilogIfStatement(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogIfStatement
-
Creates an if-then-else statement.
- VerilogIfStatement(VerilogIfStatement, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogIfStatement
-
Creates a copy of the if-then-else statement.
- VerilogIfStatementBranch - Class in ru.ispras.verilog.parser.model
-
- VerilogIfStatementBranch(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogIfStatementBranch
-
Creates an if-then-else statement branch.
- VerilogIfStatementBranch(VerilogIfStatementBranch.Type, VerilogStatement, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogIfStatementBranch
-
Create an if-then-else statement branch.
- VerilogIfStatementBranch(VerilogIfStatementBranch, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogIfStatementBranch
-
- VerilogIfStatementBranch.Type - Enum in ru.ispras.verilog.parser.model
-
- VerilogIndexRange - Class in ru.ispras.verilog.parser.elaborator
-
- VerilogIndexRange(int, int) - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogIndexRange
-
- VerilogInstantiation - Class in ru.ispras.verilog.parser.model
-
- VerilogInstantiation(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogInstantiation
-
Creates an instantiation.
- VerilogInstantiation(VerilogInstantiation, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogInstantiation
-
Creates a copy of the instantiation.
- VerilogInstantiator - Class in ru.ispras.verilog.parser.elaborator
-
- VerilogInstantiator(VerilogActivity, VerilogContext) - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogInstantiator
-
- VerilogInstantiator(VerilogAssign, VerilogContext) - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogInstantiator
-
- VerilogInstantiator(VerilogDeclaration, VerilogContext, boolean) - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogInstantiator
-
- VerilogInterpreter - Class in ru.ispras.verilog.parser.interpreter
-
- VerilogLexer - Class in ru.ispras.verilog.parser.grammar
-
- VerilogLexer(CharStream, VerilogFrontend) - Constructor for class ru.ispras.verilog.parser.grammar.VerilogLexer
-
Constructs the Verilog lexer.
- VerilogLexer() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- VerilogLexer(CharStream) - Constructor for class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- VerilogLexer(CharStream, RecognizerSharedState) - Constructor for class ru.ispras.verilog.parser.grammar.VerilogLexer
-
- VerilogLexer.DFA11 - Class in ru.ispras.verilog.parser.grammar
-
- VerilogLexer.DFA26 - Class in ru.ispras.verilog.parser.grammar
-
- VerilogLexer_VerilogPreprocessor - Class in ru.ispras.verilog.parser.grammar
-
- VerilogLexer_VerilogPreprocessor() - Constructor for class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- VerilogLexer_VerilogPreprocessor(CharStream, VerilogLexer) - Constructor for class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- VerilogLexer_VerilogPreprocessor(CharStream, RecognizerSharedState, VerilogLexer) - Constructor for class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
-
- VerilogLexer_VerilogPreprocessor.DFA11 - Class in ru.ispras.verilog.parser.grammar
-
- VerilogLibrary - Class in ru.ispras.verilog.parser
-
- VerilogLiteral - Class in ru.ispras.verilog.parser.model.basis
-
- VerilogLiteral(BitVector, BitVector, BitVector) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Creates a bit vector literal.
- VerilogLiteral(BitVector) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Creates a bit vector literal with no X and Z digits.
- VerilogLiteral(int, int) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Creates a bit vector literal.
- VerilogLiteral(int) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Creates an integer literal.
- VerilogLiteral(boolean) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Creates an integer literal.
- VerilogLiteral(BigInteger) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Creates an integer literal.
- VerilogLiteral(double) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Creates a real literal.
- VerilogLiteral(String) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Creates a string literal.
- VerilogLiteral(Data) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Creates a literal.
- VerilogLiteral(VerilogLiteral) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogLiteral
-
Creates a copy of the literal.
- VerilogLiteral.Type - Enum in ru.ispras.verilog.parser.model.basis
-
- VerilogLogger - Class in ru.ispras.verilog.parser
-
- VerilogLoopGenerate - Class in ru.ispras.verilog.parser.model
-
- VerilogLoopGenerate(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogLoopGenerate
-
Creates a generate loop.
- VerilogLoopGenerate(VerilogLoopGenerate, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogLoopGenerate
-
Creates a copy of the generate loop.
- VerilogLoopStatement - Class in ru.ispras.verilog.parser.model
-
- VerilogLoopStatement(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Creates a loop statement.
- VerilogLoopStatement(VerilogLoopStatement, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogLoopStatement
-
Creates a copy of the loop statement.
- VerilogLoopStatement.Type - Enum in ru.ispras.verilog.parser.model
-
- VerilogMinTypMax - Class in ru.ispras.verilog.parser.model.basis
-
- VerilogMinTypMax() - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogMinTypMax
-
Creates a min:typ:max expression.
- VerilogMinTypMax(VerilogExpression) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogMinTypMax
-
Creates a min:typ:max expression.
- VerilogMinTypMax(VerilogMinTypMax) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogMinTypMax
-
Creates a copy of the min:typ:max expression.
- VerilogModule - Class in ru.ispras.verilog.parser.model
-
VerilogModule
represents the abstract syntax of the module declaration.
- VerilogModule(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogModule
-
Creates a module.
- VerilogModule(VerilogModule, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogModule
-
Creates a copy of the module.
- VerilogModule.Type - Enum in ru.ispras.verilog.parser.model
-
- VerilogNode - Class in ru.ispras.verilog.parser.model
-
VerilogNode
represents a basic AST node for the Verilog HDL.
- VerilogNode(VerilogNode.Tag, EnumSet<VerilogNode.Tag>, AbstractNode.NodeKind, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogNode
-
Creates a node.
- VerilogNode(VerilogNode.Tag, EnumSet<VerilogNode.Tag>, AbstractNode.NodeKind) - Constructor for class ru.ispras.verilog.parser.model.VerilogNode
-
Creates a top-level node (i.e.
- VerilogNode(VerilogNode, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogNode
-
Creates a copy of the node.
- VerilogNode.Tag - Enum in ru.ispras.verilog.parser.model
-
- VerilogNodePrinter - Class in ru.ispras.verilog.parser.sample
-
- VerilogNodePrinter(boolean) - Constructor for class ru.ispras.verilog.parser.sample.VerilogNodePrinter
-
Creates a node printer.
- VerilogNodeVisitor - Class in ru.ispras.verilog.parser.walker
-
This class represents a base Verilog node visitor.
- VerilogNodeVisitor() - Constructor for class ru.ispras.verilog.parser.walker.VerilogNodeVisitor
-
- VerilogNullStatement - Class in ru.ispras.verilog.parser.model
-
- VerilogNullStatement(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogNullStatement
-
Creates a null statement.
- VerilogNullStatement(VerilogNullStatement, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogNullStatement
-
Creates a copy of the null statement.
- VerilogOperations - Enum in ru.ispras.verilog.parser.interpreter
-
- VerilogParameter - Class in ru.ispras.verilog.parser.elaborator
-
- VerilogParameter(VerilogParameter.Type, String, Data) - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogParameter
-
Creates a parameter definition.
- VerilogParameter.Type - Enum in ru.ispras.verilog.parser.elaborator
-
- VerilogParser - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser(TokenStream) - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser
-
- VerilogParser(TokenStream, RecognizerSharedState) - Constructor for class ru.ispras.verilog.parser.grammar.VerilogParser
-
- VerilogParser.additive_operator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.always_construct_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.attribute_assignment_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.attribute_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.attribute_instance_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.attributes_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.begin_block_statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.bitwise_and_operator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.bitwise_or_operator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.bitwise_xor_operator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.block_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.block_item_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.block_variable_array_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.block_variable_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.block_variable_type_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.case_generate_item_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.case_generate_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.case_item_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.case_statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.charge_strength_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.checktime_condition_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.compare_operator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.concatenation_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.continuous_assign_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.continuous_assignment_statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.data_event_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.defparam_assignment_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.delay_control_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.delay_or_event_control_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.delay_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.delay_value_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.delayed_data_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.delayed_reference_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.delayed_statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.description_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.DFA135 - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.DFA158 - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.DFA232 - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.DFA240 - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.DFA242 - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.DFA61 - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.DFA94 - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.disable_statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.discrete_assignment_statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.drive_strength_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.edge_control_specifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.edge_descriptor_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.edge_indicator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.edge_symbol_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.end_edge_offset_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.equality_operator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.event_array_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.event_based_flag_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.event_control_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.event_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.event_expression_1_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.event_expression_2_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.event_expression_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.event_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.event_trigger_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_0_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_10_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_11_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_12_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_13_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_14_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_1_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_2_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_3_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_4_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_5_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_6_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_7_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_8_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_9_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.expression_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.fork_block_statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.fullskew_timing_check_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.function_call_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.function_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.function_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.function_item_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.function_return_type_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.gate_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.generate_block_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.generate_block_or_null_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.generate_block_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.generate_region_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.genvar_assignment_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.genvar_decl_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.genvar_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.genvar_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.hierarchical_event_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.hierarchical_function_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.hierarchical_identifier_item_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.hierarchical_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.hierarchical_parameter_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.hierarchical_task_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.hold_timing_check_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.if_generate_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.if_statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.initial_construct_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.level_symbol_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.list_of_expressions_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.list_of_mintypmax_expressions_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.list_of_parameter_assignments_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.list_of_port_connections_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.list_of_port_declarations_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.list_of_port_references_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.list_of_ports_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.localparam_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.logical_and_operator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.logical_or_operator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.loop_generate_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.loop_statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.lvalue_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.mintypmax_expression_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.module_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.module_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.module_instance_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.module_instance_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.module_instantiation_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.module_or_generate_item_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.module_parameter_list_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.multiplicative_operator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.net_assignment_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.net_decl_assignment_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.net_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.net_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.net_type_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.nochange_timing_check_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.notifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.null_statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.number_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.pair_of_level_symbols_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.param_assignment_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.parameter_assignment_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.parameter_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.parameter_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.parameter_override_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.parameter_type_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.path_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.path_delay_value_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.path_description_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.period_timing_check_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.port_connection_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.port_decl_assignment_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.port_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.port_expression_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.port_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.port_reference_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.port_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.port_type_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.power_operator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.primary_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.procedural_timing_control_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.pulsestyle_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.range_expression_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.range_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.recovery_timing_check_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.recrem_timing_check_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.reference_event_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.reference_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.reg_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.remain_active_flag_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.removal_timing_check_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.repeat_event_control_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.replication_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.setup_timing_check_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.setuphold_timing_check_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.shift_operator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.showcancelled_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.skew_timing_check_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.source_code_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.specify_block_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.specify_item_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.specify_terminal_descriptor_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.specparam_assignment_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.specparam_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.specparam_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.stamptime_condition_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.start_edge_offset_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.startRule_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.state_dependent_path_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.state_independent_path_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.strength_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.strength_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.string_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.system_function_call_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.system_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.system_task_enable_statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.system_timing_check_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.table_entry_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.task_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.task_enable_statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.task_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.task_item_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.terminal_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.ternary_operator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.threshold_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.timeskew_timing_check_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.timing_check_condition_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.timing_check_event_control_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.timing_check_event_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.timing_check_limit_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.udp_declaration_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.udp_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.udp_item_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.udp_table_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.unary_operator_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.variable_assignment_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.variable_deassignment_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.variable_decl_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.variable_identifier_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.wait_statement_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogParser.width_timing_check_return - Class in ru.ispras.verilog.parser.grammar
-
- VerilogPath - Class in ru.ispras.verilog.parser.model.basis
-
- VerilogPath() - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogPath
-
Creates an empty path.
- VerilogPath(VerilogPathItem) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogPath
-
Creates a path consisting of one path item.
- VerilogPath(VerilogPath) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogPath
-
Creates a copy of the path.
- VerilogPathDeclaration - Class in ru.ispras.verilog.parser.model
-
- VerilogPathDeclaration(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Creates a path declaration.
- VerilogPathDeclaration(VerilogPathDeclaration, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogPathDeclaration
-
Creates a copy of path declaration.
- VerilogPathDeclaration.Type - Enum in ru.ispras.verilog.parser.model
-
- VerilogPathDescription - Class in ru.ispras.verilog.parser.model.basis
-
- VerilogPathDescription() - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Creates a path description.
- VerilogPathDescription(VerilogPathDescription) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogPathDescription
-
Creates a copy of the path description.
- VerilogPathDescription.Polarity - Enum in ru.ispras.verilog.parser.model.basis
-
- VerilogPathDescription.Type - Enum in ru.ispras.verilog.parser.model.basis
-
- VerilogPathItem - Class in ru.ispras.verilog.parser.model.basis
-
- VerilogPathItem() - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogPathItem
-
Creates a path item with no name.
- VerilogPathItem(String) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogPathItem
-
Creates a path item with the given instance name.
- VerilogPathItem(String, VerilogExpression) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogPathItem
-
Creates a path item with the given name and index.
- VerilogPathItem(VerilogPathItem) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogPathItem
-
Creates a copy of the path item.
- VerilogPort - Class in ru.ispras.verilog.parser.model
-
- VerilogPort(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogPort
-
Creates a port.
- VerilogPort(VerilogPort, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogPort
-
Creates a copy of the port.
- VerilogPortConnection - Class in ru.ispras.verilog.parser.model
-
- VerilogPortConnection(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogPortConnection
-
Creates a port connection.
- VerilogPortConnection(VerilogPortConnection, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogPortConnection
-
Creates a copy of the port connection.
- VerilogPrinter - Class in ru.ispras.verilog.parser.sample
-
- VerilogPrinter() - Constructor for class ru.ispras.verilog.parser.sample.VerilogPrinter
-
- VerilogProcedure - Class in ru.ispras.verilog.parser.model
-
- VerilogProcedure(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogProcedure
-
Creates a procedure.
- VerilogProcedure(VerilogProcedure, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogProcedure
-
Creates a copy of the procedure.
- VerilogProcedure.Type - Enum in ru.ispras.verilog.parser.model
-
- VerilogProcess - Class in ru.ispras.verilog.parser.elaborator
-
- VerilogProcess(VerilogProcess.Type, VerilogStatement) - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogProcess
-
- VerilogProcess.Type - Enum in ru.ispras.verilog.parser.elaborator
-
- VerilogPulseStyle - Class in ru.ispras.verilog.parser.model
-
- VerilogPulseStyle(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogPulseStyle
-
Creates a pulse style specification.
- VerilogPulseStyle(VerilogPulseStyle, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogPulseStyle
-
Creates a copy of the pulse style specification.
- VerilogPulseStyle.Type - Enum in ru.ispras.verilog.parser.model
-
- VerilogRange - Class in ru.ispras.verilog.parser.model.basis
-
- VerilogRange() - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Creates an range.
- VerilogRange(VerilogRange) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogRange
-
Creates a copy of the range.
- VerilogRange.Type - Enum in ru.ispras.verilog.parser.model.basis
-
- VerilogReference - Class in ru.ispras.verilog.parser.model.basis
-
- VerilogReference() - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogReference
-
Creates a reference.
- VerilogReference(VerilogReference) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogReference
-
Creates a copy of the reference.
- VerilogRepeatEvents - Class in ru.ispras.verilog.parser.model.basis
-
- VerilogRepeatEvents() - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogRepeatEvents
-
Creates a repeat-event construct.
- VerilogRepeatEvents(VerilogRepeatEvents) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogRepeatEvents
-
Creates a copy of the repeat-event construct.
- VerilogShowCancelled - Class in ru.ispras.verilog.parser.model
-
- VerilogShowCancelled(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogShowCancelled
-
Creates a show-cancelled construct.
- VerilogShowCancelled(VerilogShowCancelled, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogShowCancelled
-
Creates a copy of the show-cancelled construct.
- VerilogShowCancelled.Type - Enum in ru.ispras.verilog.parser.model
-
- VerilogSpecify - Class in ru.ispras.verilog.parser.model
-
VerilogSpecify
represents the abstract syntax of the specify construct.
- VerilogSpecify(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogSpecify
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Creates a specify construct.
- VerilogSpecify(VerilogSpecify, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogSpecify
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Creates a copy of the specify construct.
- VerilogStandard - Enum in ru.ispras.verilog.parser
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- VerilogStatement - Class in ru.ispras.verilog.parser.model
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- VerilogStatement(VerilogNode.Tag, EnumSet<VerilogNode.Tag>, AbstractNode.NodeKind, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogStatement
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Creates a statement.
- VerilogStatement(VerilogNode.Tag, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogStatement
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Creates a statement with no children.
- VerilogStatement(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogStatement
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Creates a null statement.
- VerilogStatement(VerilogStatement, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogStatement
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Creates a copy of the statement.
- VerilogStaticChecker - Class in ru.ispras.verilog.parser.backends.syntax.checker
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- VerilogStaticChecker() - Constructor for class ru.ispras.verilog.parser.backends.syntax.checker.VerilogStaticChecker
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- VerilogStrength - Class in ru.ispras.verilog.parser.model.basis
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- VerilogStrength() - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogStrength
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Creates a signal strength.
- VerilogStrength(VerilogStrength) - Constructor for class ru.ispras.verilog.parser.model.basis.VerilogStrength
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Creates a copy of the signal strength.
- VerilogStrength.Type - Enum in ru.ispras.verilog.parser.model.basis
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- VerilogSyntaxBackend - Class in ru.ispras.verilog.parser
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- VerilogSyntaxBackend(String) - Constructor for class ru.ispras.verilog.parser.VerilogSyntaxBackend
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Creates an abstract back-end.
- VerilogSyntaxBackend(String, VerilogNodeVisitor) - Constructor for class ru.ispras.verilog.parser.VerilogSyntaxBackend
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Creates a visitor-based back-end.
- VerilogSyntaxBackends - Class in ru.ispras.verilog.parser
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- VerilogSyntaxBackends() - Constructor for class ru.ispras.verilog.parser.VerilogSyntaxBackends
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- VerilogTable - Class in ru.ispras.verilog.parser.model
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- VerilogTable(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogTable
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Creates a UDP table.
- VerilogTable(VerilogTable, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogTable
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Creates a copy of the UDP table.
- VerilogTableEntry - Class in ru.ispras.verilog.parser.model
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- VerilogTableEntry(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogTableEntry
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Creates a UDP table entry.
- VerilogTableEntry(VerilogTableEntry, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogTableEntry
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Creates a copy of the UDP table entry.
- VerilogTaskStatement - Class in ru.ispras.verilog.parser.model
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- VerilogTaskStatement(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogTaskStatement
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Creates a task statement.
- VerilogTaskStatement(VerilogTaskStatement, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogTaskStatement
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- VerilogTransformer - Class in ru.ispras.verilog.parser.transformer
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- VerilogTransformer() - Constructor for class ru.ispras.verilog.parser.transformer.VerilogTransformer
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- VerilogTransformerBvconcat - Class in ru.ispras.verilog.parser.transformer
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- VerilogTransformerBvconcat() - Constructor for class ru.ispras.verilog.parser.transformer.VerilogTransformerBvconcat
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- VerilogTransformerComposite - Class in ru.ispras.verilog.parser.transformer
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- VerilogTransformerComposite() - Constructor for class ru.ispras.verilog.parser.transformer.VerilogTransformerComposite
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- VerilogTransformerComposite(VerilogTransformer...) - Constructor for class ru.ispras.verilog.parser.transformer.VerilogTransformerComposite
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- VerilogTransformerOperation - Class in ru.ispras.verilog.parser.transformer
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- VerilogTransformerOperation() - Constructor for class ru.ispras.verilog.parser.transformer.VerilogTransformerOperation
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- VerilogTransformerVariableRename - Class in ru.ispras.verilog.parser.transformer
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- VerilogTransformerVariableRename() - Constructor for class ru.ispras.verilog.parser.transformer.VerilogTransformerVariableRename
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- VerilogTransformerVariableSubstitute - Class in ru.ispras.verilog.parser.transformer
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- VerilogTransformerVariableSubstitute(Map<String, VerilogDescriptor>, VerilogContext, Map<String, VerilogParameter>) - Constructor for class ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute
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- VerilogTranslator - Class in ru.ispras.verilog.parser
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- VerilogTranslator() - Constructor for class ru.ispras.verilog.parser.VerilogTranslator
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Constructs a Verilog translator.
- VerilogTreeBuilder - Class in ru.ispras.verilog.parser.grammar
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- VerilogTreeBuilder(TreeNodeStream) - Constructor for class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
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- VerilogTreeBuilder(TreeNodeStream, RecognizerSharedState) - Constructor for class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
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- VerilogTreeBuilder(CommonTreeNodeStream, VerilogFrontend) - Constructor for class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
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Constructs the Verilog tree builder.
- VerilogTreeBuilder.DFA47 - Class in ru.ispras.verilog.parser.grammar
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- VerilogTreeWalker - Class in ru.ispras.verilog.parser.walker
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- VerilogTreeWalker(VerilogNode, VerilogNodeVisitor) - Constructor for class ru.ispras.verilog.parser.walker.VerilogTreeWalker
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Creates a Verilog tree walker.
- VerilogTriggerStatement - Class in ru.ispras.verilog.parser.model
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- VerilogTriggerStatement(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogTriggerStatement
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Creates a trigger statement.
- VerilogTriggerStatement(VerilogTriggerStatement, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogTriggerStatement
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Creates a copy of the trigger statement.
- VerilogTypeCaster - Class in ru.ispras.verilog.parser.backends.design.typecast
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- VerilogTypeCaster(String) - Constructor for class ru.ispras.verilog.parser.backends.design.typecast.VerilogTypeCaster
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Creates a back-end.
- VerilogVariable - Class in ru.ispras.verilog.parser.elaborator
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- VerilogVariable(VerilogVariable.Type, NodeVariable, NodeVariable) - Constructor for class ru.ispras.verilog.parser.elaborator.VerilogVariable
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- VerilogVariable.Type - Enum in ru.ispras.verilog.parser.elaborator
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- VerilogWaitStatement - Class in ru.ispras.verilog.parser.model
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- VerilogWaitStatement(VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogWaitStatement
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Creates a wait statement.
- VerilogWaitStatement(VerilogWaitStatement, VerilogNode) - Constructor for class ru.ispras.verilog.parser.model.VerilogWaitStatement
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Creates a copy of the wait statement.
- VERSION - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
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- VERSION - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
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- VERSION - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
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- VERSION - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
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- VOCAB - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer
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- VOCAB - Static variable in class ru.ispras.verilog.parser.grammar.VerilogLexer_VerilogPreprocessor
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- VOCAB - Static variable in class ru.ispras.verilog.parser.grammar.VerilogParser
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- VOCAB - Static variable in class ru.ispras.verilog.parser.grammar.VerilogTreeBuilder
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