public final class VerilogCaseStatementItem extends VerilogNode
VerilogCaseStatementItem
represents case statement items.VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogCaseStatementItem(VerilogCaseStatementItem other,
VerilogNode parent)
Creates a copy of the case item.
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VerilogCaseStatementItem(VerilogNode parent)
Creates a case item.
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Modifier and Type | Method and Description |
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void |
addExpression(VerilogExpression expression)
Adds the expression to the case.
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void |
addExpressions(java.util.List<VerilogExpression> list)
Adds all the expressions to the case.
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VerilogCaseStatementItem |
clone()
Clones the symbol table.
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VerilogExpression |
getExpression()
Returns the condition associated with the case.
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java.util.List<VerilogExpression> |
getExpressions()
Returns the expressions of the case.
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VerilogStatement |
getStatement()
Returns the statement of the case.
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void |
removeExpressions()
Removes all the expressions of the case.
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void |
setStatement(VerilogStatement statement)
Sets the statement of the case.
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getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogCaseStatementItem(VerilogNode parent)
parent
- the parent node.public VerilogCaseStatementItem(VerilogCaseStatementItem other, VerilogNode parent)
other
- the case item to be copied.parent
- the parent node.public java.util.List<VerilogExpression> getExpressions()
public void addExpression(VerilogExpression expression)
expression
- the expression to be added.public void addExpressions(java.util.List<VerilogExpression> list)
list
- The list of expressions.public void removeExpressions()
public VerilogStatement getStatement()
public void setStatement(VerilogStatement statement)
statement
- the statement to be set.public VerilogExpression getExpression()
public VerilogCaseStatementItem clone()
AbstractSymbolTable
clone
in class VerilogNode