public static final class VerilogDesign.Builder
extends java.lang.Object
Constructor and Description |
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Builder() |
Modifier and Type | Method and Description |
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void |
addParameter(VerilogParameter.Type type,
java.lang.String name,
ru.ispras.fortress.data.Data data) |
void |
addProcess(VerilogInstantiator instantiator) |
void |
addVariable(VerilogVariable variable,
VerilogInstantiator instantiator) |
VerilogDesign |
build()
Calculates the variables' bit sizes and modifies the expressions.
|
java.util.Map<java.lang.String,VerilogParameter> |
getParameters() |
void |
setName(java.lang.String name) |
public void setName(java.lang.String name)
public java.util.Map<java.lang.String,VerilogParameter> getParameters()
public void addParameter(VerilogParameter.Type type, java.lang.String name, ru.ispras.fortress.data.Data data)
public void addVariable(VerilogVariable variable, VerilogInstantiator instantiator)
public void addProcess(VerilogInstantiator instantiator)
public VerilogDesign build()