public final class VerilogCaseGenerateItem extends VerilogNode
VerilogCaseGenerateItem
represents generate case items.VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
---|---|
static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
---|
VerilogCaseGenerateItem(VerilogCaseGenerateItem other,
VerilogNode parent)
Creates a copy of the generate case item.
|
VerilogCaseGenerateItem(VerilogNode parent)
Creates a generate case item.
|
Modifier and Type | Method and Description |
---|---|
void |
addExpression(VerilogExpression expression)
Adds the expression to the case.
|
VerilogCaseGenerateItem |
clone()
Clones the symbol table.
|
VerilogExpression |
getExpression()
Returns the condition associated with the case.
|
java.util.List<VerilogExpression> |
getExpressions()
Returns the expressions of the case.
|
VerilogBlockGenerate |
getGenerate()
Returns the generate block of the case.
|
void |
setGenerate(VerilogBlockGenerate generate)
Sets the generate block of the case.
|
getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogCaseGenerateItem(VerilogNode parent)
parent
- the parent node.public VerilogCaseGenerateItem(VerilogCaseGenerateItem other, VerilogNode parent)
other
- the generate case item to be copied.parent
- the parent node.public java.util.List<VerilogExpression> getExpressions()
public void addExpression(VerilogExpression expression)
expression
- the expression to be added.public VerilogBlockGenerate getGenerate()
public void setGenerate(VerilogBlockGenerate generate)
generate
- the generate block to be set.public VerilogExpression getExpression()
public VerilogCaseGenerateItem clone()
AbstractSymbolTable
clone
in class VerilogNode