public final class VerilogCaseStatement extends VerilogStatement
VerilogCaseStatement
represents case statements.
There are the following process types:
case
(ordinary case statement);casex
(X-don't-care case statement);casez
(Z-don't-care case statement).Modifier and Type | Class and Description |
---|---|
static class |
VerilogCaseStatement.Type
VerilogCaseStatement.Type contains the case statement types. |
VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
---|---|
static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
TAGS
Constructor and Description |
---|
VerilogCaseStatement(VerilogCaseStatement other,
VerilogNode parent)
Creates a copy of the case statement.
|
VerilogCaseStatement(VerilogNode parent)
Creates a case statement.
|
Modifier and Type | Method and Description |
---|---|
void |
addCase(VerilogCaseStatementItem item)
Adds the case to the case selection construct.
|
VerilogCaseStatement |
clone()
Clones the symbol table.
|
java.util.List<VerilogCaseStatementItem> |
getCases()
Returns the cases.
|
VerilogExpression |
getExpression()
Returns the case selection expression.
|
VerilogCaseStatement.Type |
getType()
Returns the case statement type.
|
boolean |
isCase()
Checks whether the statement is
CASE . |
boolean |
isCaseX()
Checks whether the statement is
CASEX . |
boolean |
isCaseZ()
Checks whether the statement is
CASEZ . |
void |
setCase()
Sets the type of the statement to
CASE . |
void |
setCaseX()
Sets the type of the statement to
CASEX . |
void |
setCaseZ()
Sets the type of the statement to
CASEZ . |
void |
setExpression(VerilogExpression expression)
Sets the case selection expression.
|
void |
setType(VerilogCaseStatement.Type type)
Sets the case statement type.
|
getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogCaseStatement(VerilogNode parent)
parent
- the parent node.public VerilogCaseStatement(VerilogCaseStatement other, VerilogNode parent)
other
- the case statement to be copied.parent
- the parent node.public VerilogCaseStatement.Type getType()
public void setType(VerilogCaseStatement.Type type)
type
- the type to be set.public boolean isCase()
CASE
.true
iff the statement is CASE
.public boolean isCaseX()
CASEX
.true
iff the statement is CASEX
.public boolean isCaseZ()
CASEZ
.true
iff the statement is CASEZ
.public void setCase()
CASE
.public void setCaseX()
CASEX
.public void setCaseZ()
CASEZ
.public VerilogExpression getExpression()
public void setExpression(VerilogExpression expression)
expression
- the expression to be set.public java.util.List<VerilogCaseStatementItem> getCases()
public void addCase(VerilogCaseStatementItem item)
item
- the case to be added.public VerilogCaseStatement clone()
AbstractSymbolTable
clone
in class VerilogStatement