public final class VerilogInstantiation extends VerilogNode
VerilogInstantiation
represents module instantiations.VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogInstantiation(VerilogInstantiation other,
VerilogNode parent)
Creates a copy of the instantiation.
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VerilogInstantiation(VerilogNode parent)
Creates an instantiation.
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Modifier and Type | Method and Description |
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void |
addConnection(VerilogPortConnection connection)
Adds a port connection to the instance.
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void |
addParameter(VerilogAssignment assignment)
Adds the parameter definition to the instance.
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VerilogInstantiation |
clone()
Clones the symbol table.
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VerilogModule |
getDeclaration()
Returns the module declaration.
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VerilogDelay |
getDelay()
Returns the delay of the instance's port connections.
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java.lang.String |
getModuleName()
Returns the module name of the instance.
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VerilogRange |
getRange()
Returns the range of the instantiation array.
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VerilogStrength |
getStrength()
Returns the strength of the instance's port connections.
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void |
setDeclaration(VerilogModule declaration)
Sets the module declaration.
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void |
setDelay(VerilogDelay delay)
Sets the delay of the instance's port connections.
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void |
setModuleName(java.lang.String module) |
void |
setRange(VerilogRange range)
Sets the range of the instantiation array.
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void |
setStrength(VerilogStrength strength)
Sets the strength of the instance's port connections.
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getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogInstantiation(VerilogNode parent)
parent
- the parent node.public VerilogInstantiation(VerilogInstantiation other, VerilogNode parent)
other
- the instantiation to be copied.parent
- the parent node.public java.lang.String getModuleName()
public void setModuleName(java.lang.String module)
public VerilogDelay getDelay()
public void setDelay(VerilogDelay delay)
delay
- the delay to be set.public VerilogStrength getStrength()
public void setStrength(VerilogStrength strength)
strength
- the strength to be set.public VerilogRange getRange()
public void setRange(VerilogRange range)
range
- the range to be set.public void addParameter(VerilogAssignment assignment)
assignment
- the parameter definition.public void addConnection(VerilogPortConnection connection)
connection
- the port connection.public VerilogModule getDeclaration()
public void setDeclaration(VerilogModule declaration)
declaration
- the module declaration to be set.public VerilogInstantiation clone()
AbstractSymbolTable
clone
in class VerilogNode