public final class VerilogCode extends VerilogNode
VerilogCode
represents source code.VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogCode()
Creates a source code node.
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VerilogCode(VerilogCode other)
Creates a copy of the source code node.
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Modifier and Type | Method and Description |
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VerilogCode |
clone()
Clones the symbol table.
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java.lang.String |
getFileName()
Returns the name of the source code file.
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void |
setFileName(java.lang.String fileName)
Sets the name of the source code file.
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getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogCode()
public VerilogCode(VerilogCode other)
other
- the source code entity to be copied.public java.lang.String getFileName()
public void setFileName(java.lang.String fileName)
fileName
- the file name.public VerilogCode clone()
AbstractSymbolTable
clone
in class VerilogNode