public final class VerilogPortConnection extends VerilogNode
VerilogPortConnection
represents port connections.VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogPortConnection(VerilogNode parent)
Creates a port connection.
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VerilogPortConnection(VerilogPortConnection other,
VerilogNode parent)
Creates a copy of the port connection.
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Modifier and Type | Method and Description |
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VerilogPortConnection |
clone()
Clones the symbol table.
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VerilogExpression |
getExpression()
Returns the expression connected to the port.
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void |
setExpression(VerilogExpression expression)
Sets the expression connected to the port.
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getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogPortConnection(VerilogNode parent)
parent
- the parent node.public VerilogPortConnection(VerilogPortConnection other, VerilogNode parent)
other
- the port connection to be copied.parent
- the parent node.public VerilogExpression getExpression()
public void setExpression(VerilogExpression expression)
expression
- the expression to be set.public VerilogPortConnection clone()
AbstractSymbolTable
clone
in class VerilogNode