public final class VerilogDeclaration extends VerilogNode
VerilogDeclaration
represents declarations.
There are the following types of declarations:
input
;output
;inout
;event
;parameter
;specparam
;localparam
;genvar
;variable
.Modifier and Type | Class and Description |
---|---|
static class |
VerilogDeclaration.Type
VerilogDeclaration.Type contains the declaration types. |
VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
---|---|
static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
---|
VerilogDeclaration(VerilogDeclaration other,
VerilogNode parent)
Creates a copy of the declaration.
|
VerilogDeclaration(VerilogNode parent)
Creates a declaration.
|
Modifier and Type | Method and Description |
---|---|
void |
addDeclaration(VerilogDeclaration declaration)
Merges this declaration with the given one.
|
void |
addDimension(VerilogRange range)
Extends the dimension of the declared element.
|
VerilogDeclaration |
clone()
Clones the symbol table.
|
java.util.List<VerilogRange> |
getDimensions()
Returns the dimensions of the declared element.
|
VerilogElementType |
getElementType()
Returns the type of the declared element.
|
VerilogMinTypMax |
getExpression()
Returns the expression representing the initial value.
|
VerilogDeclaration.Type |
getType()
Returns the declaration type.
|
boolean |
isEvent()
Checks whether the declaration is
EVENT . |
boolean |
isGenvar()
Checks whether the declaration is
GENVAR . |
boolean |
isInout()
Checks whether the declaration is
INOUT . |
boolean |
isInput()
Checks whether the declaration is
INPUT . |
boolean |
isLocalparam()
Checks whether the declaration is
LOCALPARAM . |
boolean |
isOutput()
Checks whether the declaration is
OUTPUT . |
boolean |
isParam()
Checks whether the declaration is a parameter
(
PARAMETER , SPECPARAM , or LOCALPARAM ). |
boolean |
isParameter()
Checks whether the declaration is
PARAMETER . |
boolean |
isPort()
Checks whether the declaration is a port (
INPUT , OUTPUT , or INOUT ). |
boolean |
isSpecparam()
Checks whether the declaration is
SPECPARAMETER . |
boolean |
isVariable()
Checks whether the declaration is
VARIABLE . |
void |
setElementType(VerilogElementType elementType)
Sets the type of the declared element.
|
void |
setEvent()
Sets the type of the statement to
EVENT . |
void |
setExpression(VerilogMinTypMax expression)
Sets the expression representing the initial value.
|
void |
setGenvar()
Sets the type of the statement to
GENVAR . |
void |
setInout()
Sets the type of the statement to
INOUT . |
void |
setInput()
Sets the type of the statement to
INPUT . |
void |
setLocalparam()
Sets the type of the statement to
LOCALPARAM . |
void |
setOutput()
Sets the type of the statement to
OUTPUT . |
void |
setParameter()
Sets the type of the statement to
PARAMETER . |
void |
setSpecparam()
Sets the type of the statement to
SPECPARAM . |
void |
setType(VerilogDeclaration.Type type)
Sets the declaration type.
|
void |
setVariable()
Sets the type of the statement to
VARIABLE . |
getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogDeclaration(VerilogNode parent)
parent
- the parent node.public VerilogDeclaration(VerilogDeclaration other, VerilogNode parent)
other
- the declaration to be copied.parent
- the parent node.public VerilogDeclaration.Type getType()
public void setType(VerilogDeclaration.Type type)
type
- the type to be set.public boolean isInput()
INPUT
.true
iff the declaration is INPUT
.public boolean isOutput()
OUTPUT
.true
iff the declaration is OUTPUT
.public boolean isInout()
INOUT
.true
iff the declaration is INOUT
.public boolean isPort()
INPUT
, OUTPUT
, or INOUT
).isPort
in class VerilogNode
true
iff the declaration is a port.public boolean isEvent()
EVENT
.true
iff the declaration is EVENT
.public boolean isParameter()
PARAMETER
.true
iff the declaration is PARAMETER
.public boolean isSpecparam()
SPECPARAMETER
.true
iff the declaration is SPECPARAMETER
.public boolean isLocalparam()
LOCALPARAM
.true
iff the declaration is LOCALPARAM
.public boolean isParam()
PARAMETER
, SPECPARAM
, or LOCALPARAM
).true
iff the declaration is a port.public boolean isGenvar()
GENVAR
.true
iff the declaration is GENVAR
.public boolean isVariable()
VARIABLE
.true
iff the declaration is VARIABLE
.public void setInput()
INPUT
.public void setOutput()
OUTPUT
.public void setInout()
INOUT
.public void setEvent()
EVENT
.public void setParameter()
PARAMETER
.public void setSpecparam()
SPECPARAM
.public void setLocalparam()
LOCALPARAM
.public void setGenvar()
GENVAR
.public void setVariable()
VARIABLE
.public VerilogElementType getElementType()
public void setElementType(VerilogElementType elementType)
elementType
- the type to be set.public java.util.List<VerilogRange> getDimensions()
public void addDimension(VerilogRange range)
range
- the new dimension.public VerilogMinTypMax getExpression()
public void setExpression(VerilogMinTypMax expression)
expression
- the expression to be set.public void addDeclaration(VerilogDeclaration declaration)
[IEEE Std 1364-2005] 12.3.3 Port declarations If a port declaration does not include a net or variable type, then the port can be again declared in a net or variable declaration. If the net or variable is declared as a vector, the range specification between the two declarations of a port shall be identical. Once a name is used in a port declaration, it shall not be declared again in another port declaration or in a data type declaration.
declaration
- the declaration to be merged with this one.public VerilogDeclaration clone()
AbstractSymbolTable
clone
in class VerilogNode