public final class VerilogBlockStatement extends VerilogStatement
VerilogBlockStatement
represents block statements.
There are the following block types:
begin
(sequential block);fork
(parallel block).Modifier and Type | Class and Description |
---|---|
static class |
VerilogBlockStatement.Type
VerilogBlockStatement.Type contains the block statement types. |
VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
---|---|
static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_ELEMENTS |
TAGS
Constructor and Description |
---|
VerilogBlockStatement(VerilogBlockStatement other,
VerilogNode parent)
Creates a copy of the block statement.
|
VerilogBlockStatement(VerilogNode parent)
Creates a block statement.
|
Modifier and Type | Method and Description |
---|---|
VerilogBlockStatement |
clone()
Clones the symbol table.
|
VerilogBlockStatement.Type |
getType()
Returns the type of the block statement (
BEGIN or FORK ). |
boolean |
isBegin()
Checks whether the statement
BEGIN . |
boolean |
isFork()
Checks whether the statement
FORK . |
void |
setBegin()
Sets the type of the statement to
BEGIN . |
void |
setFork()
Sets the type of the statement to
FORK . |
void |
setType(VerilogBlockStatement.Type type)
Sets the type of the block statement.
|
getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_ELEMENTS
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogBlockStatement(VerilogNode parent)
parent
- the parent node.public VerilogBlockStatement(VerilogBlockStatement other, VerilogNode parent)
other
- the block statement to be copied.parent
- the parent node.public VerilogBlockStatement.Type getType()
BEGIN
or FORK
).public void setType(VerilogBlockStatement.Type type)
type
- the type to be set.public boolean isBegin()
BEGIN
.true
iff the statement is BEGIN
.public boolean isFork()
FORK
.true
iff the statement is FORK
.public void setBegin()
BEGIN
.public void setFork()
FORK
.public VerilogBlockStatement clone()
AbstractSymbolTable
clone
in class VerilogStatement