public final class VerilogIfGenerate extends VerilogNode
VerilogIfGenerate
represents if-then-else generate constructs.VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogIfGenerate(VerilogIfGenerate other,
VerilogNode parent)
Creates a if-then-else generate construct.
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VerilogIfGenerate(VerilogNode parent)
Creates a if-then-else generate construct.
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Modifier and Type | Method and Description |
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VerilogIfGenerate |
clone()
Clones the symbol table.
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VerilogBlockGenerate |
getElseGenerate()
Returns the generate block related to the branch
else . |
VerilogExpression |
getExpression()
Returns the condition.
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VerilogBlockGenerate |
getThenGenerate()
Returns the generate block related to the branch
then . |
void |
setElseGenerate(VerilogBlockGenerate elseGenerate)
Sets the generate block related to the else branch.
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void |
setExpression(VerilogExpression expression)
Sets the condition.
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void |
setThenGenerate(VerilogBlockGenerate thenGenerate)
Sets the generate block related to the branch
then . |
getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogIfGenerate(VerilogNode parent)
parent
- the parent node.public VerilogIfGenerate(VerilogIfGenerate other, VerilogNode parent)
other
- the if-then-else generate construct to be copied.parent
- the parent node.public VerilogExpression getExpression()
public void setExpression(VerilogExpression expression)
expression
- the condition.public VerilogBlockGenerate getThenGenerate()
then
.then
's generate block.public void setThenGenerate(VerilogBlockGenerate thenGenerate)
then
.thenGenerate
- the generate block to be set.public VerilogBlockGenerate getElseGenerate()
else
.else
's generate block.public void setElseGenerate(VerilogBlockGenerate elseGenerate)
elseGenerate
- the generate block to be set.public VerilogIfGenerate clone()
AbstractSymbolTable
clone
in class VerilogNode