public final class VerilogIfStatementBranch extends VerilogNode
VerilogIfStatementBranch
represents if-then-else statement branches (then and else).Modifier and Type | Class and Description |
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static class |
VerilogIfStatementBranch.Type
VerilogIfStatementBranch.Type contains the branch types. |
VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogIfStatementBranch(VerilogIfStatementBranch.Type type,
VerilogStatement statement,
VerilogNode parent)
Create an if-then-else statement branch.
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VerilogIfStatementBranch(VerilogIfStatementBranch other,
VerilogNode parent) |
VerilogIfStatementBranch(VerilogNode parent)
Creates an if-then-else statement branch.
|
Modifier and Type | Method and Description |
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VerilogIfStatementBranch |
clone()
Clones the symbol table.
|
VerilogExpression |
getExpression()
Returns the condition associated with the branch.
|
VerilogStatement |
getStatement()
Returns the branch body.
|
VerilogIfStatementBranch.Type |
getType()
Returns the branch type (
THEN or ELSE ). |
boolean |
isElse()
Checks whether the branch is
ELSE . |
boolean |
isThen()
Checks whether the branch is
THEN . |
void |
setElse()
Sets the branch type to
ELSE . |
void |
setStatement(VerilogStatement statement)
Sets the branch body.
|
void |
setThen()
Sets the branch type to
THEN . |
void |
setType(VerilogIfStatementBranch.Type type)
Sets the branch type.
|
getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogIfStatementBranch(VerilogNode parent)
parent
- the parent node.public VerilogIfStatementBranch(VerilogIfStatementBranch.Type type, VerilogStatement statement, VerilogNode parent)
type
- the branch type.statement
- the branch body.parent
- the parent node.public VerilogIfStatementBranch(VerilogIfStatementBranch other, VerilogNode parent)
public VerilogIfStatementBranch.Type getType()
THEN
or ELSE
).public void setType(VerilogIfStatementBranch.Type type)
type
- the branch type.public boolean isThen()
THEN
.true
iff the branch is THEN
.public boolean isElse()
ELSE
.true
iff the branch is ELSE
.public void setThen()
THEN
.public void setElse()
ELSE
.public VerilogStatement getStatement()
public void setStatement(VerilogStatement statement)
statement
- the branch body.public VerilogExpression getExpression()
public VerilogIfStatementBranch clone()
AbstractSymbolTable
clone
in class VerilogNode