public final class VerilogIfGenerateBranch extends VerilogNode
VerilogIfGenerateBranch
represents if-then-else generate branches (then and else).Modifier and Type | Class and Description |
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static class |
VerilogIfGenerateBranch.Type
VerilogIfGenerateBranch.Type contains the branch types. |
VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogIfGenerateBranch(VerilogIfGenerateBranch.Type type,
VerilogBlockGenerate generate,
VerilogNode parent)
Creates an if generate branch.
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VerilogIfGenerateBranch(VerilogIfGenerateBranch other,
VerilogNode parent)
Creates a copy of the if generate branch.
|
VerilogIfGenerateBranch(VerilogNode parent)
Creates an if generate branch.
|
Modifier and Type | Method and Description |
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VerilogIfGenerateBranch |
clone()
Clones the symbol table.
|
VerilogExpression |
getExpression()
Returns the condition associated with the branch.
|
VerilogBlockGenerate |
getGenerate()
Returns the branch body.
|
VerilogIfGenerateBranch.Type |
getType()
Returns the branch type (
THEN or ELSE ). |
boolean |
isElse()
Checks whether the branch is
ELSE . |
boolean |
isThen()
Checks whether the branch is
THEN . |
void |
setElse()
Sets the branch type to
ELSE . |
void |
setGenerate(VerilogBlockGenerate generate)
Sets the branch body.
|
void |
setThen()
Sets the branch type to
THEN . |
void |
setType(VerilogIfGenerateBranch.Type type)
Sets the branch type.
|
getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogIfGenerateBranch(VerilogNode parent)
parent
- the node parent.public VerilogIfGenerateBranch(VerilogIfGenerateBranch.Type type, VerilogBlockGenerate generate, VerilogNode parent)
type
- the branch type.generate
- the branch body.parent
- the parent node.public VerilogIfGenerateBranch(VerilogIfGenerateBranch other, VerilogNode parent)
other
- the if generate branch to be copied.parent
- the parent node.public VerilogIfGenerateBranch.Type getType()
THEN
or ELSE
).public void setType(VerilogIfGenerateBranch.Type type)
type
- the branch type.public boolean isThen()
THEN
.true
iff the branch is THEN
.public boolean isElse()
ELSE
.true
iff the branch is ELSE
.public void setThen()
THEN
.public void setElse()
ELSE
.public VerilogBlockGenerate getGenerate()
public void setGenerate(VerilogBlockGenerate generate)
generate
- the branch body.public VerilogExpression getExpression()
public VerilogIfGenerateBranch clone()
AbstractSymbolTable
clone
in class VerilogNode