public abstract class VerilogTransformer extends VerilogEmptyVisitor
VerilogTransformer
implements an engine that transforms expressions.NodeVisitor.Result
Constructor and Description |
---|
VerilogTransformer() |
Modifier and Type | Method and Description |
---|---|
NodeVisitor.Result |
onAssignBegin(VerilogAssign node) |
NodeVisitor.Result |
onAssignStatementBegin(VerilogAssignStatement node) |
NodeVisitor.Result |
onCaseStatementBegin(VerilogCaseStatement node) |
NodeVisitor.Result |
onCaseStatementItemBegin(VerilogCaseStatementItem node) |
NodeVisitor.Result |
onDeclarationBegin(VerilogDeclaration node) |
NodeVisitor.Result |
onDelayedStatementBegin(VerilogDelayedStatement node) |
NodeVisitor.Result |
onIfStatementBegin(VerilogIfStatement node) |
NodeVisitor.Result |
onLoopStatementBegin(VerilogLoopStatement node) |
NodeVisitor.Result |
onTaskStatementBegin(VerilogTaskStatement node) |
NodeVisitor.Result |
onWaitStatementBegin(VerilogWaitStatement node) |
void |
run(VerilogNode node) |
abstract ru.ispras.fortress.expression.Node |
transform(ru.ispras.fortress.expression.Node node) |
onActivityBegin, onActivityEnd, onAssignEnd, onAssignmentBegin, onAssignmentEnd, onAssignStatementEnd, onAttributeBegin, onAttributeEnd, onBlockGenerateBegin, onBlockGenerateEnd, onBlockStatementBegin, onBlockStatementEnd, onCaseGenerateBegin, onCaseGenerateEnd, onCaseGenerateItemBegin, onCaseGenerateItemEnd, onCaseStatementEnd, onCaseStatementItemEnd, onCodeBegin, onCodeEnd, onDeclarationEnd, onDefineParameterBegin, onDefineParameterEnd, onDelayedStatementEnd, onDisableStatementBegin, onDisableStatementEnd, onGenerateBegin, onGenerateEnd, onIfGenerateBegin, onIfGenerateBranchBegin, onIfGenerateBranchEnd, onIfGenerateEnd, onIfStatementBranchBegin, onIfStatementBranchEnd, onIfStatementEnd, onInstantiationBegin, onInstantiationEnd, onLoopGenerateBegin, onLoopGenerateEnd, onLoopStatementEnd, onModuleBegin, onModuleEnd, onNullStatementBegin, onNullStatementEnd, onPathDeclarationBegin, onPathDeclarationEnd, onPortBegin, onPortConnectionBegin, onPortConnectionEnd, onPortEnd, onProcedureBegin, onProcedureEnd, onPulseStyleBegin, onPulseStyleEnd, onShowCancelledBegin, onShowCancelledEnd, onSpecifyBegin, onSpecifyEnd, onTableBegin, onTableEnd, onTableEntryBegin, onTableEntryEnd, onTaskStatementEnd, onTriggerStatementBegin, onTriggerStatementEnd, onWaitStatementEnd
onBegin, onEnd
public final void run(VerilogNode node)
public NodeVisitor.Result onDeclarationBegin(VerilogDeclaration node)
onDeclarationBegin
in class VerilogEmptyVisitor
public NodeVisitor.Result onAssignBegin(VerilogAssign node)
onAssignBegin
in class VerilogEmptyVisitor
public NodeVisitor.Result onAssignStatementBegin(VerilogAssignStatement node)
onAssignStatementBegin
in class VerilogEmptyVisitor
public NodeVisitor.Result onCaseStatementBegin(VerilogCaseStatement node)
onCaseStatementBegin
in class VerilogEmptyVisitor
public NodeVisitor.Result onCaseStatementItemBegin(VerilogCaseStatementItem node)
onCaseStatementItemBegin
in class VerilogEmptyVisitor
public NodeVisitor.Result onDelayedStatementBegin(VerilogDelayedStatement node)
onDelayedStatementBegin
in class VerilogEmptyVisitor
public NodeVisitor.Result onIfStatementBegin(VerilogIfStatement node)
onIfStatementBegin
in class VerilogEmptyVisitor
public NodeVisitor.Result onLoopStatementBegin(VerilogLoopStatement node)
onLoopStatementBegin
in class VerilogEmptyVisitor
public NodeVisitor.Result onTaskStatementBegin(VerilogTaskStatement node)
onTaskStatementBegin
in class VerilogEmptyVisitor
public NodeVisitor.Result onWaitStatementBegin(VerilogWaitStatement node)
onWaitStatementBegin
in class VerilogEmptyVisitor
public abstract ru.ispras.fortress.expression.Node transform(ru.ispras.fortress.expression.Node node)