public final class VerilogAttribute extends VerilogNode
VerilogAttribute
represents attributes.VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogAttribute(VerilogAttribute other,
VerilogNode parent)
Creates a copy of the attribute.
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VerilogAttribute(VerilogNode parent)
Creates an attribute.
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Modifier and Type | Method and Description |
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VerilogAttribute |
clone()
Clones the symbol table.
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VerilogExpression |
getExpression()
Returns the expression of the attribute.
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void |
setExpression(VerilogExpression expression)
Sets the expression of the attribute.
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getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogAttribute(VerilogNode parent)
parent
- the node parent.public VerilogAttribute(VerilogAttribute other, VerilogNode parent)
other
- the attribute to be copied.parent
- the parent node.public VerilogExpression getExpression()
public void setExpression(VerilogExpression expression)
expression
- the expression to be set.public VerilogAttribute clone()
AbstractSymbolTable
clone
in class VerilogNode