LCOV - code coverage report
Current view: top level - drivers/usb/host - ehci.h (source / functions) Hit Total Coverage
Test: coverage.info Lines: 38 38 100.0 %
Date: 2017-01-25 Functions: 12 12 100.0 %

          Line data    Source code
       1             : /*
       2             :  * Copyright (c) 2001-2002 by David Brownell
       3             :  *
       4             :  * This program is free software; you can redistribute it and/or modify it
       5             :  * under the terms of the GNU General Public License as published by the
       6             :  * Free Software Foundation; either version 2 of the License, or (at your
       7             :  * option) any later version.
       8             :  *
       9             :  * This program is distributed in the hope that it will be useful, but
      10             :  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
      11             :  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
      12             :  * for more details.
      13             :  *
      14             :  * You should have received a copy of the GNU General Public License
      15             :  * along with this program; if not, write to the Free Software Foundation,
      16             :  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
      17             :  */
      18             : 
      19             : #ifndef __LINUX_EHCI_HCD_H
      20             : #define __LINUX_EHCI_HCD_H
      21             : 
      22             : /* definitions used for the EHCI driver */
      23             : 
      24             : /*
      25             :  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
      26             :  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
      27             :  * the host controller implementation.
      28             :  *
      29             :  * To facilitate the strongest possible byte-order checking from "sparse"
      30             :  * and so on, we use __leXX unless that's not practical.
      31             :  */
      32             : #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
      33             : typedef __u32 __bitwise __hc32;
      34             : typedef __u16 __bitwise __hc16;
      35             : #else
      36             : #define __hc32  __le32
      37             : #define __hc16  __le16
      38             : #endif
      39             : 
      40             : /* statistics can be kept for tuning/monitoring */
      41             : struct ehci_stats {
      42             :         /* irq usage */
      43             :         unsigned long           normal;
      44             :         unsigned long           error;
      45             :         unsigned long           reclaim;
      46             :         unsigned long           lost_iaa;
      47             : 
      48             :         /* termination of urbs from core */
      49             :         unsigned long           complete;
      50             :         unsigned long           unlink;
      51             : };
      52           6 : 
      53             : /* ehci_hcd->lock guards shared data against other CPUs:
      54             :  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
      55             :  *   usb_host_endpoint: hcpriv
      56             :  *   ehci_qh:   qh_next, qtd_list
      57             :  *   ehci_qtd:  qtd_list
      58             :  *
      59             :  * Also, hold this lock when talking to HC registers or
      60             :  * when updating hw_* fields in shared qh/qtd/... structures.
      61             :  */
      62             : 
      63             : #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
      64             : 
      65             : struct ehci_hcd {                       /* one per controller */
      66             :         /* glue to PCI and HCD framework */
      67             :         struct ehci_caps __iomem *caps;
      68             :         struct ehci_regs __iomem *regs;
      69             :         struct ehci_dbg_port __iomem *debug;
      70             : 
      71             :         __u32                   hcs_params;     /* cached register copy */
      72             :         spinlock_t              lock;
      73             : 
      74             :         /* async schedule support */
      75             :         struct ehci_qh          *async;
      76             :         struct ehci_qh          *reclaim;
      77             :         unsigned                scanning : 1;
      78             : 
      79             :         /* periodic schedule support */
      80             : #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
      81             :         unsigned                periodic_size;
      82             :         __hc32                  *periodic;      /* hw periodic table */
      83             :         dma_addr_t              periodic_dma;
      84             :         unsigned                i_thresh;       /* uframes HC might cache */
      85             : 
      86             :         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
      87             :         int                     next_uframe;    /* scan periodic, start here */
      88             :         unsigned                periodic_sched; /* periodic activity count */
      89             : 
      90             :         /* list of itds & sitds completed while clock_frame was still active */
      91             :         struct list_head        cached_itd_list;
      92             :         struct list_head        cached_sitd_list;
      93             :         unsigned                clock_frame;
      94             : 
      95             :         /* per root hub port */
      96             :         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
      97             : 
      98             :         /* bit vectors (one bit per port) */
      99             :         unsigned long           bus_suspended;          /* which ports were
     100             :                         already suspended at the start of a bus suspend */
     101             :         unsigned long           companion_ports;        /* which ports are
     102             :                         dedicated to the companion controller */
     103             :         unsigned long           owned_ports;            /* which ports are
     104             :                         owned by the companion during a bus suspend */
     105             :         unsigned long           port_c_suspend;         /* which ports have
     106             :                         the change-suspend feature turned on */
     107             :         unsigned long           suspended_ports;        /* which ports are
     108             :                         suspended */
     109             : 
     110             :         /* per-HC memory pools (could be per-bus, but ...) */
     111             :         struct dma_pool         *qh_pool;       /* qh per active urb */
     112             :         struct dma_pool         *qtd_pool;      /* one or more per qh */
     113             :         struct dma_pool         *itd_pool;      /* itd per iso urb */
     114             :         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
     115             : 
     116             :         struct timer_list       iaa_watchdog;
     117             :         struct timer_list       watchdog;
     118             :         unsigned long           actions;
     119             :         unsigned                stamp;
     120             :         unsigned                random_frame;
     121             :         unsigned long           next_statechange;
     122             :         ktime_t                 last_periodic_enable;
     123             :         u32                     command;
     124             : 
     125             :         /* SILICON QUIRKS */
     126             :         unsigned                no_selective_suspend:1;
     127             :         unsigned                has_fsl_port_bug:1; /* FreeScale */
     128             :         unsigned                big_endian_mmio:1;
     129             :         unsigned                big_endian_desc:1;
     130             :         unsigned                has_amcc_usb23:1;
     131             :         unsigned                need_io_watchdog:1;
     132             :         unsigned                broken_periodic:1;
     133             : 
     134             :         /* required for usb32 quirk */
     135             :         #define OHCI_CTRL_HCFS          (3 << 6)
     136             :         #define OHCI_USB_OPER           (2 << 6)
     137             :         #define OHCI_USB_SUSPEND        (3 << 6)
     138             : 
     139             :         #define OHCI_HCCTRL_OFFSET      0x4
     140             :         #define OHCI_HCCTRL_LEN         0x4
     141             :         __hc32                  *ohci_hcctrl_reg;
     142             :         unsigned                has_hostpc:1;
     143             : 
     144             :         u8                      sbrn;           /* packed release number */
     145             : 
     146             :         /* irq statistics */
     147             : #ifdef EHCI_STATS
     148             :         struct ehci_stats       stats;
     149             : #       define COUNT(x) do { (x)++; } while (0)
     150             : #else
     151             : #       define COUNT(x) do {} while (0)
     152             : #endif
     153             : 
     154             :         /* debug files */
     155             : #ifdef DEBUG
     156             :         struct dentry           *debug_dir;
     157             :         struct dentry           *debug_async;
     158             :         struct dentry           *debug_periodic;
     159             :         struct dentry           *debug_registers;
     160             : #endif
     161             : };
     162             : 
     163             : /* convert between an HCD pointer and the corresponding EHCI_HCD */
     164             : static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
     165             : {
     166          21 :         return (struct ehci_hcd *) (hcd->hcd_priv);
     167             : }
     168             : static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
     169             : {
     170        4110 :         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
     171             : }
     172             : 
     173             : 
     174             : static inline void
     175             : iaa_watchdog_start(struct ehci_hcd *ehci)
     176             : {
     177         264 :         WARN_ON(timer_pending(&ehci->iaa_watchdog));
     178          96 :         mod_timer(&ehci->iaa_watchdog,
     179          24 :                         jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
     180          48 : }
     181             : 
     182             : static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
     183             : {
     184          24 :         del_timer(&ehci->iaa_watchdog);
     185          24 : }
     186           1 : 
     187             : enum ehci_timer_action {
     188             :         TIMER_IO_WATCHDOG,
     189             :         TIMER_ASYNC_SHRINK,
     190             :         TIMER_ASYNC_OFF,
     191             : };
     192             : 
     193             : static inline void
     194             : timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
     195             : {
     196         112 :         clear_bit (action, &ehci->actions);
     197          56 : }
     198             : 
     199             : static void free_cached_lists(struct ehci_hcd *ehci);
     200           1 : 
     201             : /*-------------------------------------------------------------------------*/
     202             : 
     203             : #include <linux/usb/ehci_def.h>
     204             : 
     205             : /*-------------------------------------------------------------------------*/
     206             : 
     207             : #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
     208             : 
     209             : /*
     210             :  * EHCI Specification 0.95 Section 3.5
     211             :  * QTD: describe data transfer components (buffer, direction, ...)
     212             :  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
     213             :  *
     214             :  * These are associated only with "QH" (Queue Head) structures,
     215             :  * used with control, bulk, and interrupt transfers.
     216             :  */
     217             : struct ehci_qtd {
     218             :         /* first part defined by EHCI spec */
     219             :         __hc32                  hw_next;        /* see EHCI 3.5.1 */
     220             :         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
     221             :         __hc32                  hw_token;       /* see EHCI 3.5.3 */
     222             : #define QTD_TOGGLE      (1 << 31) /* data toggle */
     223             : #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
     224             : #define QTD_IOC         (1 << 15) /* interrupt on complete */
     225             : #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
     226             : #define QTD_PID(tok)    (((tok)>>8) & 0x3)
     227             : #define QTD_STS_ACTIVE  (1 << 7)  /* HC may execute this */
     228             : #define QTD_STS_HALT    (1 << 6)  /* halted on error */
     229             : #define QTD_STS_DBE     (1 << 5)  /* data buffer error (in HC) */
     230             : #define QTD_STS_BABBLE  (1 << 4)  /* device was babbling (qtd halted) */
     231             : #define QTD_STS_XACT    (1 << 3)  /* device gave illegal response */
     232             : #define QTD_STS_MMF     (1 << 2)  /* incomplete split transaction */
     233             : #define QTD_STS_STS     (1 << 1)  /* split transaction state */
     234             : #define QTD_STS_PING    (1 << 0)  /* issue PING? */
     235             : 
     236             : #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
     237             : #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
     238             : #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
     239             : 
     240             :         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
     241             :         __hc32                  hw_buf_hi [5];        /* Appendix B */
     242             : 
     243             :         /* the rest is HCD-private */
     244             :         dma_addr_t              qtd_dma;                /* qtd address */
     245             :         struct list_head        qtd_list;               /* sw qtd list */
     246             :         struct urb              *urb;                   /* qtd's urb */
     247             :         size_t                  length;                 /* length of buffer */
     248             : } __attribute__ ((aligned (32)));
     249           4 : 
     250             : /* mask NakCnt+T in qh->hw_alt_next */
     251             : #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
     252             : 
     253             : #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
     254             : 
     255             : /*-------------------------------------------------------------------------*/
     256             : 
     257             : /* type tag from {qh,itd,sitd,fstn}->hw_next */
     258             : #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
     259             : 
     260             : /*
     261             :  * Now the following defines are not converted using the
     262             :  * cpu_to_le32() macro anymore, since we have to support
     263             :  * "dynamic" switching between be and le support, so that the driver
     264             :  * can be used on one system with SoC EHCI controller using big-endian
     265             :  * descriptors as well as a normal little-endian PCI EHCI controller.
     266             :  */
     267             : /* values for that type tag */
     268             : #define Q_TYPE_ITD      (0 << 1)
     269             : #define Q_TYPE_QH       (1 << 1)
     270             : #define Q_TYPE_SITD     (2 << 1)
     271             : #define Q_TYPE_FSTN     (3 << 1)
     272             : 
     273             : /* next async queue entry, or pointer to interrupt/periodic QH */
     274             : #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
     275             : 
     276             : /* for periodic/async schedules and qtd lists, mark end of list */
     277             : #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
     278             : 
     279             : /*
     280             :  * Entries in periodic shadow table are pointers to one of four kinds
     281             :  * of data structure.  That's dictated by the hardware; a type tag is
     282             :  * encoded in the low bits of the hardware's periodic schedule.  Use
     283             :  * Q_NEXT_TYPE to get the tag.
     284             :  *
     285             :  * For entries in the async schedule, the type tag always says "qh".
     286             :  */
     287             : union ehci_shadow {
     288             :         struct ehci_qh          *qh;            /* Q_TYPE_QH */
     289             :         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
     290             :         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
     291             :         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
     292             :         __hc32                  *hw_next;       /* (all types) */
     293             :         void                    *ptr;
     294             : };
     295           1 : 
     296             : /*-------------------------------------------------------------------------*/
     297             : 
     298             : /*
     299             :  * EHCI Specification 0.95 Section 3.6
     300             :  * QH: describes control/bulk/interrupt endpoints
     301             :  * See Fig 3-7 "Queue Head Structure Layout".
     302             :  *
     303             :  * These appear in both the async and (for interrupt) periodic schedules.
     304             :  */
     305             : 
     306             : /* first part defined by EHCI spec */
     307             : struct ehci_qh_hw {
     308             :         __hc32                  hw_next;        /* see EHCI 3.6.1 */
     309             :         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
     310             : #define QH_HEAD         0x00008000
     311             :         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
     312             : #define QH_SMASK        0x000000ff
     313             : #define QH_CMASK        0x0000ff00
     314             : #define QH_HUBADDR      0x007f0000
     315             : #define QH_HUBPORT      0x3f800000
     316             : #define QH_MULT         0xc0000000
     317             :         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
     318             : 
     319             :         /* qtd overlay (hardware parts of a struct ehci_qtd) */
     320             :         __hc32                  hw_qtd_next;
     321             :         __hc32                  hw_alt_next;
     322             :         __hc32                  hw_token;
     323             :         __hc32                  hw_buf [5];
     324             :         __hc32                  hw_buf_hi [5];
     325             : } __attribute__ ((aligned(32)));
     326           1 : 
     327             : struct ehci_qh {
     328             :         struct ehci_qh_hw       *hw;
     329             :         /* the rest is HCD-private */
     330             :         dma_addr_t              qh_dma;         /* address of qh */
     331             :         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
     332             :         struct list_head        qtd_list;       /* sw qtd list */
     333             :         struct ehci_qtd         *dummy;
     334             :         struct ehci_qh          *reclaim;       /* next to reclaim */
     335             : 
     336             :         struct ehci_hcd         *ehci;
     337             : 
     338             :         /*
     339             :          * Do NOT use atomic operations for QH refcounting. On some CPUs
     340             :          * (PPC7448 for example), atomic operations cannot be performed on
     341             :          * memory that is cache-inhibited (i.e. being used for DMA).
     342             :          * Spinlocks are used to protect all QH fields.
     343             :          */
     344             :         u32                     refcount;
     345             :         unsigned                stamp;
     346             : 
     347             :         u8                      needs_rescan;   /* Dequeue during giveback */
     348             :         u8                      qh_state;
     349             : #define QH_STATE_LINKED         1               /* HC sees this */
     350             : #define QH_STATE_UNLINK         2               /* HC may still see this */
     351             : #define QH_STATE_IDLE           3               /* HC doesn't see this */
     352             : #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
     353             : #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
     354             : 
     355             :         u8                      xacterrs;       /* XactErr retry counter */
     356             : #define QH_XACTERR_MAX          32              /* XactErr retry limit */
     357             : 
     358             :         /* periodic schedule info */
     359             :         u8                      usecs;          /* intr bandwidth */
     360             :         u8                      gap_uf;         /* uframes split/csplit gap */
     361             :         u8                      c_usecs;        /* ... split completion bw */
     362             :         u16                     tt_usecs;       /* tt downstream bandwidth */
     363             :         unsigned short          period;         /* polling interval */
     364             :         unsigned short          start;          /* where polling starts */
     365             : #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
     366             : 
     367             :         struct usb_device       *dev;           /* access to TT */
     368             :         unsigned                is_out:1;       /* bulk or intr OUT */
     369             :         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
     370             : };
     371           1 : 
     372             : /*-------------------------------------------------------------------------*/
     373             : 
     374             : /* description of one iso transaction (up to 3 KB data if highspeed) */
     375             : struct ehci_iso_packet {
     376             :         /* These will be copied to iTD when scheduling */
     377             :         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
     378             :         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
     379             :         u8                      cross;          /* buf crosses pages */
     380             :         /* for full speed OUT splits */
     381             :         u32                     buf1;
     382             : };
     383           1 : 
     384             : /* temporary schedule data for packets from iso urbs (both speeds)
     385             :  * each packet is one logical usb transaction to the device (not TT),
     386             :  * beginning at stream->next_uframe
     387             :  */
     388             : struct ehci_iso_sched {
     389             :         struct list_head        td_list;
     390             :         unsigned                span;
     391             :         struct ehci_iso_packet  packet [0];
     392             : };
     393           1 : 
     394             : /*
     395             :  * ehci_iso_stream - groups all (s)itds for this endpoint.
     396             :  * acts like a qh would, if EHCI had them for ISO.
     397             :  */
     398             : struct ehci_iso_stream {
     399             :         /* first field matches ehci_hq, but is NULL */
     400             :         struct ehci_qh_hw       *hw;
     401             : 
     402             :         u32                     refcount;
     403             :         u8                      bEndpointAddress;
     404             :         u8                      highspeed;
     405             :         u16                     depth;          /* depth in uframes */
     406             :         struct list_head        td_list;        /* queued itds/sitds */
     407             :         struct list_head        free_list;      /* list of unused itds/sitds */
     408             :         struct usb_device       *udev;
     409             :         struct usb_host_endpoint *ep;
     410             : 
     411             :         /* output of (re)scheduling */
     412             :         unsigned long           start;          /* jiffies */
     413             :         unsigned long           rescheduled;
     414             :         int                     next_uframe;
     415             :         __hc32                  splits;
     416             : 
     417             :         /* the rest is derived from the endpoint descriptor,
     418             :          * trusting urb->interval == f(epdesc->bInterval) and
     419             :          * including the extra info for hw_bufp[0..2]
     420             :          */
     421             :         u8                      usecs, c_usecs;
     422             :         u16                     interval;
     423             :         u16                     tt_usecs;
     424             :         u16                     maxp;
     425             :         u16                     raw_mask;
     426             :         unsigned                bandwidth;
     427             : 
     428             :         /* This is used to initialize iTD's hw_bufp fields */
     429             :         __hc32                  buf0;
     430             :         __hc32                  buf1;
     431             :         __hc32                  buf2;
     432             : 
     433             :         /* this is used to initialize sITD's tt info */
     434             :         __hc32                  address;
     435             : };
     436           1 : 
     437             : /*-------------------------------------------------------------------------*/
     438             : 
     439             : /*
     440             :  * EHCI Specification 0.95 Section 3.3
     441             :  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
     442             :  *
     443             :  * Schedule records for high speed iso xfers
     444             :  */
     445             : struct ehci_itd {
     446             :         /* first part defined by EHCI spec */
     447             :         __hc32                  hw_next;           /* see EHCI 3.3.1 */
     448             :         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
     449             : #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
     450             : #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
     451             : #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
     452             : #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
     453             : #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
     454             : #define EHCI_ITD_IOC            (1 << 15) /* interrupt on complete */
     455             : 
     456             : #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
     457             : 
     458             :         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
     459             :         __hc32                  hw_bufp_hi [7]; /* Appendix B */
     460             : 
     461             :         /* the rest is HCD-private */
     462             :         dma_addr_t              itd_dma;        /* for this itd */
     463             :         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
     464             : 
     465             :         struct urb              *urb;
     466             :         struct ehci_iso_stream  *stream;        /* endpoint's queue */
     467             :         struct list_head        itd_list;       /* list of stream's itds */
     468             : 
     469             :         /* any/all hw_transactions here may be used by that urb */
     470             :         unsigned                frame;          /* where scheduled */
     471             :         unsigned                pg;
     472             :         unsigned                index[8];       /* in urb->iso_frame_desc */
     473             : } __attribute__ ((aligned (32)));
     474           1 : 
     475             : /*-------------------------------------------------------------------------*/
     476             : 
     477             : /*
     478             :  * EHCI Specification 0.95 Section 3.4
     479             :  * siTD, aka split-transaction isochronous Transfer Descriptor
     480             :  *       ... describe full speed iso xfers through TT in hubs
     481             :  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
     482             :  */
     483             : struct ehci_sitd {
     484             :         /* first part defined by EHCI spec */
     485             :         __hc32                  hw_next;
     486             : /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
     487             :         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
     488             :         __hc32                  hw_uframe;              /* EHCI table 3-10 */
     489             :         __hc32                  hw_results;             /* EHCI table 3-11 */
     490             : #define SITD_IOC        (1 << 31) /* interrupt on completion */
     491             : #define SITD_PAGE       (1 << 30) /* buffer 0/1 */
     492             : #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
     493             : #define SITD_STS_ACTIVE (1 << 7)  /* HC may execute this */
     494             : #define SITD_STS_ERR    (1 << 6)  /* error from TT */
     495             : #define SITD_STS_DBE    (1 << 5)  /* data buffer error (in HC) */
     496             : #define SITD_STS_BABBLE (1 << 4)  /* device was babbling */
     497             : #define SITD_STS_XACT   (1 << 3)  /* illegal IN response */
     498             : #define SITD_STS_MMF    (1 << 2)  /* incomplete split transaction */
     499             : #define SITD_STS_STS    (1 << 1)  /* split transaction state */
     500             : 
     501             : #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
     502             : 
     503             :         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
     504             :         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
     505             :         __hc32                  hw_buf_hi [2];          /* Appendix B */
     506             : 
     507             :         /* the rest is HCD-private */
     508             :         dma_addr_t              sitd_dma;
     509             :         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
     510             : 
     511             :         struct urb              *urb;
     512             :         struct ehci_iso_stream  *stream;        /* endpoint's queue */
     513             :         struct list_head        sitd_list;      /* list of stream's sitds */
     514             :         unsigned                frame;
     515             :         unsigned                index;
     516             : } __attribute__ ((aligned (32)));
     517           1 : 
     518             : /*-------------------------------------------------------------------------*/
     519             : 
     520             : /*
     521             :  * EHCI Specification 0.96 Section 3.7
     522             :  * Periodic Frame Span Traversal Node (FSTN)
     523             :  *
     524             :  * Manages split interrupt transactions (using TT) that span frame boundaries
     525             :  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
     526             :  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
     527             :  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
     528             :  */
     529             : struct ehci_fstn {
     530             :         __hc32                  hw_next;        /* any periodic q entry */
     531             :         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
     532             : 
     533             :         /* the rest is HCD-private */
     534             :         dma_addr_t              fstn_dma;
     535             :         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
     536             : } __attribute__ ((aligned (32)));
     537             : 
     538             : /*-------------------------------------------------------------------------*/
     539             : 
     540             : #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
     541             : 
     542             : /*
     543             :  * Some EHCI controllers have a Transaction Translator built into the
     544             :  * root hub. This is a non-standard feature.  Each controller will need
     545             :  * to add code to the following inline functions, and call them as
     546             :  * needed (mostly in root hub code).
     547             :  */
     548             : 
     549             : #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
     550             : 
     551             : /* Returns the speed of a device attached to a port on the root hub. */
     552             : static inline unsigned int
     553             : ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
     554             : {
     555         160 :         if (ehci_is_TDI(ehci)) {
     556             :                 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
     557         256 :                 case 0:
     558          32 :                         return 0;
     559         288 :                 case 1:
     560          32 :                         return (1<<USB_PORT_FEAT_LOWSPEED);
     561         192 :                 case 2:
     562             :                 default:
     563          64 :                         return (1<<USB_PORT_FEAT_HIGHSPEED);
     564             :                 }
     565             :         }
     566          32 :         return (1<<USB_PORT_FEAT_HIGHSPEED);
     567             : }
     568             : 
     569             : #else
     570             : 
     571             : #define ehci_is_TDI(e)                  (0)
     572             : 
     573             : #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
     574             : #endif
     575             : 
     576             : /*-------------------------------------------------------------------------*/
     577             : 
     578             : #ifdef CONFIG_PPC_83xx
     579             : /* Some Freescale processors have an erratum in which the TT
     580             :  * port number in the queue head was 0..N-1 instead of 1..N.
     581             :  */
     582             : #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
     583             : #else
     584             : #define ehci_has_fsl_portno_bug(e)              (0)
     585             : #endif
     586             : 
     587             : /*
     588             :  * While most USB host controllers implement their registers in
     589             :  * little-endian format, a minority (celleb companion chip) implement
     590             :  * them in big endian format.
     591             :  *
     592             :  * This attempts to support either format at compile time without a
     593             :  * runtime penalty, or both formats with the additional overhead
     594             :  * of checking a flag bit.
     595             :  */
     596             : 
     597             : #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
     598             : #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
     599             : #else
     600             : #define ehci_big_endian_mmio(e)         0
     601             : #endif
     602             : 
     603             : /*
     604             :  * Big-endian read/write functions are arch-specific.
     605             :  * Other arches can be added if/when they're needed.
     606             :  */
     607             : #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
     608             : #define readl_be(addr)          __raw_readl((__force unsigned *)addr)
     609             : #define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
     610             : #endif
     611             : 
     612             : static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
     613             :                 __u32 __iomem * regs)
     614         736 : {
     615             : #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
     616             :         return ehci_big_endian_mmio(ehci) ?
     617             :                 readl_be(regs) :
     618             :                 readl(regs);
     619             : #else
     620        2208 :         return readl(regs);
     621             : #endif
     622             : }
     623             : 
     624             : static inline void ehci_writel(const struct ehci_hcd *ehci,
     625             :                 const unsigned int val, __u32 __iomem *regs)
     626             : {
     627             : #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
     628             :         ehci_big_endian_mmio(ehci) ?
     629             :                 writel_be(val, regs) :
     630             :                 writel(val, regs);
     631             : #else
     632         916 :         writel(val, regs);
     633         458 : #endif
     634             : }
     635             : 
     636             : /*
     637             :  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
     638             :  * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
     639             :  * Other common bits are dependant on has_amcc_usb23 quirk flag.
     640             :  */
     641             : #ifdef CONFIG_44x
     642             : static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
     643             : {
     644             :         u32 hc_control;
     645             : 
     646             :         hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
     647             :         if (operational)
     648             :                 hc_control |= OHCI_USB_OPER;
     649             :         else
     650             :                 hc_control |= OHCI_USB_SUSPEND;
     651             : 
     652             :         writel_be(hc_control, ehci->ohci_hcctrl_reg);
     653             :         (void) readl_be(ehci->ohci_hcctrl_reg);
     654             : }
     655             : #else
     656             : static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
     657             : { }
     658           8 : #endif
     659             : 
     660             : /*-------------------------------------------------------------------------*/
     661             : 
     662             : /*
     663             :  * The AMCC 440EPx not only implements its EHCI registers in big-endian
     664             :  * format, but also its DMA data structures (descriptors).
     665             :  *
     666             :  * EHCI controllers accessed through PCI work normally (little-endian
     667             :  * everywhere), so we won't bother supporting a BE-only mode for now.
     668             :  */
     669             : #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
     670             : #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
     671             : 
     672             : /* cpu to ehci */
     673             : static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
     674             : {
     675             :         return ehci_big_endian_desc(ehci)
     676             :                 ? (__force __hc32)cpu_to_be32(x)
     677             :                 : (__force __hc32)cpu_to_le32(x);
     678             : }
     679             : 
     680             : /* ehci to cpu */
     681             : static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
     682             : {
     683             :         return ehci_big_endian_desc(ehci)
     684             :                 ? be32_to_cpu((__force __be32)x)
     685             :                 : le32_to_cpu((__force __le32)x);
     686             : }
     687             : 
     688             : static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
     689             : {
     690             :         return ehci_big_endian_desc(ehci)
     691             :                 ? be32_to_cpup((__force __be32 *)x)
     692             :                 : le32_to_cpup((__force __le32 *)x);
     693             : }
     694             : 
     695             : #else
     696             : 
     697             : /* cpu to ehci */
     698             : static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
     699             : {
     700        5360 :         return cpu_to_le32(x);
     701             : }
     702             : 
     703             : /* ehci to cpu */
     704             : static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
     705             : {
     706         565 :         return le32_to_cpu(x);
     707             : }
     708             : 
     709             : static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
     710             : {
     711        1428 :         return le32_to_cpup(x);
     712             : }
     713             : 
     714             : #endif
     715             : 
     716             : /*-------------------------------------------------------------------------*/
     717             : 
     718             : #ifndef DEBUG
     719             : #define STUB_DEBUG_FILES
     720             : #endif  /* DEBUG */
     721             : 
     722             : /*-------------------------------------------------------------------------*/
     723             : 
     724             : #endif /* __LINUX_EHCI_HCD_H */

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