LCOV - code coverage report
Current view: top level - arch/x86/include/asm - processor.h (source / functions) Hit Total Coverage
Test: coverage.info Lines: 11 11 100.0 %
Date: 2017-01-25 Functions: 0 0 -

          Line data    Source code
       1             : #ifndef _ASM_X86_PROCESSOR_H
       2             : #define _ASM_X86_PROCESSOR_H
       3             : 
       4             : #include <asm/processor-flags.h>
       5             : 
       6             : /* Forward declaration, a strange C thing */
       7             : struct task_struct;
       8             : struct mm_struct;
       9             : 
      10             : #include <asm/vm86.h>
      11             : #include <asm/math_emu.h>
      12             : #include <asm/segment.h>
      13             : #include <asm/types.h>
      14             : #include <asm/sigcontext.h>
      15             : #include <asm/current.h>
      16             : #include <asm/cpufeature.h>
      17             : #include <asm/system.h>
      18             : #include <asm/page.h>
      19             : #include <asm/pgtable_types.h>
      20             : #include <asm/percpu.h>
      21             : #include <asm/msr.h>
      22             : #include <asm/desc_defs.h>
      23             : #include <asm/nops.h>
      24             : #include <asm/ds.h>
      25             : 
      26             : #include <linux/personality.h>
      27             : #include <linux/cpumask.h>
      28             : #include <linux/cache.h>
      29             : #include <linux/threads.h>
      30             : #include <linux/math64.h>
      31             : #include <linux/init.h>
      32             : 
      33             : #define HBP_NUM 4
      34             : /*
      35             :  * Default implementation of macro that returns current
      36             :  * instruction pointer ("program counter").
      37             :  */
      38             : static inline void *current_text_addr(void)
      39             : {
      40             :         void *pc;
      41             : 
      42             :         asm volatile("mov $1f, %0; 1:":"=r" (pc));
      43             : 
      44             :         return pc;
      45             : }
      46             : 
      47             : #ifdef CONFIG_X86_VSMP
      48             : # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
      49             : # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
      50             : #else
      51             : # define ARCH_MIN_TASKALIGN             16
      52             : # define ARCH_MIN_MMSTRUCT_ALIGN        0
      53             : #endif
      54             : 
      55             : /*
      56             :  *  CPU type and hardware bug flags. Kept separately for each CPU.
      57             :  *  Members of this structure are referenced in head.S, so think twice
      58             :  *  before touching them. [mj]
      59             :  */
      60             : 
      61             : struct cpuinfo_x86 {
      62             :         __u8                    x86;            /* CPU family */
      63             :         __u8                    x86_vendor;     /* CPU vendor */
      64             :         __u8                    x86_model;
      65             :         __u8                    x86_mask;
      66             : #ifdef CONFIG_X86_32
      67             :         char                    wp_works_ok;    /* It doesn't on 386's */
      68             : 
      69             :         /* Problems on some 486Dx4's and old 386's: */
      70             :         char                    hlt_works_ok;
      71             :         char                    hard_math;
      72             :         char                    rfu;
      73             :         char                    fdiv_bug;
      74             :         char                    f00f_bug;
      75             :         char                    coma_bug;
      76             :         char                    pad0;
      77             : #else
      78             :         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
      79             :         int                     x86_tlbsize;
      80             : #endif
      81             :         __u8                    x86_virt_bits;
      82             :         __u8                    x86_phys_bits;
      83             :         /* CPUID returned core id bits: */
      84             :         __u8                    x86_coreid_bits;
      85             :         /* Max extended CPUID function supported: */
      86             :         __u32                   extended_cpuid_level;
      87             :         /* Maximum supported CPUID level, -1=no CPUID: */
      88             :         int                     cpuid_level;
      89             :         __u32                   x86_capability[NCAPINTS];
      90             :         char                    x86_vendor_id[16];
      91             :         char                    x86_model_id[64];
      92             :         /* in KB - valid for CPUS which support this call: */
      93             :         int                     x86_cache_size;
      94             :         int                     x86_cache_alignment;    /* In bytes */
      95             :         int                     x86_power;
      96             :         unsigned long           loops_per_jiffy;
      97             : #ifdef CONFIG_SMP
      98             :         /* cpus sharing the last level cache: */
      99             :         cpumask_var_t           llc_shared_map;
     100             : #endif
     101             :         /* cpuid returned max cores value: */
     102             :         u16                      x86_max_cores;
     103             :         u16                     apicid;
     104             :         u16                     initial_apicid;
     105             :         u16                     x86_clflush_size;
     106             : #ifdef CONFIG_SMP
     107             :         /* number of cores as seen by the OS: */
     108             :         u16                     booted_cores;
     109             :         /* Physical processor id: */
     110             :         u16                     phys_proc_id;
     111             :         /* Core id: */
     112             :         u16                     cpu_core_id;
     113             :         /* Index into per_cpu list: */
     114             :         u16                     cpu_index;
     115             : #endif
     116             :         unsigned int            x86_hyper_vendor;
     117             : } __attribute__((__aligned__(SMP_CACHE_BYTES)));
     118             : 
     119             : #define X86_VENDOR_INTEL        0
     120             : #define X86_VENDOR_CYRIX        1
     121             : #define X86_VENDOR_AMD          2
     122             : #define X86_VENDOR_UMC          3
     123             : #define X86_VENDOR_CENTAUR      5
     124             : #define X86_VENDOR_TRANSMETA    7
     125             : #define X86_VENDOR_NSC          8
     126             : #define X86_VENDOR_NUM          9
     127             : 
     128             : #define X86_VENDOR_UNKNOWN      0xff
     129             : 
     130             : #define X86_HYPER_VENDOR_NONE  0
     131             : #define X86_HYPER_VENDOR_VMWARE 1
     132             : 
     133             : /*
     134             :  * capabilities of CPUs
     135             :  */
     136             : extern struct cpuinfo_x86       boot_cpu_data;
     137             : extern struct cpuinfo_x86       new_cpu_data;
     138             : 
     139             : extern struct tss_struct        doublefault_tss;
     140             : extern __u32                    cpu_caps_cleared[NCAPINTS];
     141             : extern __u32                    cpu_caps_set[NCAPINTS];
     142             : 
     143             : #ifdef CONFIG_SMP
     144             : DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
     145             : #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
     146             : #define current_cpu_data        __get_cpu_var(cpu_info)
     147             : #else
     148             : #define cpu_data(cpu)           boot_cpu_data
     149             : #define current_cpu_data        boot_cpu_data
     150             : #endif
     151             : 
     152             : extern const struct seq_operations cpuinfo_op;
     153             : 
     154             : static inline int hlt_works(int cpu)
     155             : {
     156             : #ifdef CONFIG_X86_32
     157             :         return cpu_data(cpu).hlt_works_ok;
     158             : #else
     159             :         return 1;
     160             : #endif
     161             : }
     162             : 
     163             : #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
     164             : 
     165             : extern void cpu_detect(struct cpuinfo_x86 *c);
     166             : 
     167             : extern struct pt_regs *idle_regs(struct pt_regs *);
     168             : 
     169             : extern void early_cpu_init(void);
     170             : extern void identify_boot_cpu(void);
     171             : extern void identify_secondary_cpu(struct cpuinfo_x86 *);
     172             : extern void print_cpu_info(struct cpuinfo_x86 *);
     173             : extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
     174             : extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
     175             : extern unsigned short num_cache_leaves;
     176             : 
     177             : extern void detect_extended_topology(struct cpuinfo_x86 *c);
     178             : extern void detect_ht(struct cpuinfo_x86 *c);
     179             : 
     180             : static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
     181             :                                 unsigned int *ecx, unsigned int *edx)
     182             : {
     183             :         /* ecx is often an input as well as an output. */
     184             :         asm volatile("cpuid"
     185             :             : "=a" (*eax),
     186             :               "=b" (*ebx),
     187             :               "=c" (*ecx),
     188             :               "=d" (*edx)
     189             :             : "0" (*eax), "2" (*ecx));
     190             : }
     191             : 
     192             : static inline void load_cr3(pgd_t *pgdir)
     193             : {
     194             :         write_cr3(__pa(pgdir));
     195             : }
     196             : 
     197             : #ifdef CONFIG_X86_32
     198             : /* This is the TSS defined by the hardware. */
     199             : struct x86_hw_tss {
     200             :         unsigned short          back_link, __blh;
     201             :         unsigned long           sp0;
     202             :         unsigned short          ss0, __ss0h;
     203             :         unsigned long           sp1;
     204             :         /* ss1 caches MSR_IA32_SYSENTER_CS: */
     205             :         unsigned short          ss1, __ss1h;
     206             :         unsigned long           sp2;
     207             :         unsigned short          ss2, __ss2h;
     208             :         unsigned long           __cr3;
     209             :         unsigned long           ip;
     210             :         unsigned long           flags;
     211             :         unsigned long           ax;
     212             :         unsigned long           cx;
     213             :         unsigned long           dx;
     214             :         unsigned long           bx;
     215             :         unsigned long           sp;
     216             :         unsigned long           bp;
     217             :         unsigned long           si;
     218             :         unsigned long           di;
     219             :         unsigned short          es, __esh;
     220             :         unsigned short          cs, __csh;
     221             :         unsigned short          ss, __ssh;
     222             :         unsigned short          ds, __dsh;
     223             :         unsigned short          fs, __fsh;
     224             :         unsigned short          gs, __gsh;
     225             :         unsigned short          ldt, __ldth;
     226             :         unsigned short          trace;
     227             :         unsigned short          io_bitmap_base;
     228             : 
     229             : } __attribute__((packed));
     230             : #else
     231             : struct x86_hw_tss {
     232             :         u32                     reserved1;
     233             :         u64                     sp0;
     234             :         u64                     sp1;
     235             :         u64                     sp2;
     236             :         u64                     reserved2;
     237             :         u64                     ist[7];
     238             :         u32                     reserved3;
     239             :         u32                     reserved4;
     240             :         u16                     reserved5;
     241             :         u16                     io_bitmap_base;
     242             : 
     243             : } __attribute__((packed)) ____cacheline_aligned;
     244             : #endif
     245             : 
     246             : /*
     247             :  * IO-bitmap sizes:
     248             :  */
     249             : #define IO_BITMAP_BITS                  65536
     250             : #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
     251             : #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
     252             : #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
     253             : #define INVALID_IO_BITMAP_OFFSET        0x8000
     254             : 
     255             : struct tss_struct {
     256             :         /*
     257             :          * The hardware state:
     258             :          */
     259             :         struct x86_hw_tss       x86_tss;
     260             : 
     261             :         /*
     262             :          * The extra 1 is there because the CPU will access an
     263             :          * additional byte beyond the end of the IO permission
     264             :          * bitmap. The extra byte must be all 1 bits, and must
     265             :          * be within the limit.
     266             :          */
     267             :         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
     268             : 
     269             :         /*
     270             :          * .. and then another 0x100 bytes for the emergency kernel stack:
     271             :          */
     272             :         unsigned long           stack[64];
     273             : 
     274             : } ____cacheline_aligned;
     275             : 
     276             : DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
     277             : 
     278             : /*
     279             :  * Save the original ist values for checking stack pointers during debugging
     280             :  */
     281             : struct orig_ist {
     282             :         unsigned long           ist[7];
     283             : };
     284           1 : 
     285             : #define MXCSR_DEFAULT           0x1f80
     286             : 
     287             : struct i387_fsave_struct {
     288             :         u32                     cwd;    /* FPU Control Word             */
     289             :         u32                     swd;    /* FPU Status Word              */
     290             :         u32                     twd;    /* FPU Tag Word                 */
     291             :         u32                     fip;    /* FPU IP Offset                */
     292             :         u32                     fcs;    /* FPU IP Selector              */
     293             :         u32                     foo;    /* FPU Operand Pointer Offset   */
     294             :         u32                     fos;    /* FPU Operand Pointer Selector */
     295             : 
     296             :         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
     297             :         u32                     st_space[20];
     298             : 
     299             :         /* Software status information [not touched by FSAVE ]:         */
     300             :         u32                     status;
     301             : };
     302           5 : 
     303             : struct i387_fxsave_struct {
     304             :         u16                     cwd; /* Control Word                    */
     305             :         u16                     swd; /* Status Word                     */
     306             :         u16                     twd; /* Tag Word                        */
     307             :         u16                     fop; /* Last Instruction Opcode         */
     308             :         union {
     309             :                 struct {
     310             :                         u64     rip; /* Instruction Pointer             */
     311             :                         u64     rdp; /* Data Pointer                    */
     312             :                 };
     313             :                 struct {
     314             :                         u32     fip; /* FPU IP Offset                   */
     315             :                         u32     fcs; /* FPU IP Selector                 */
     316             :                         u32     foo; /* FPU Operand Offset              */
     317             :                         u32     fos; /* FPU Operand Selector            */
     318             :                 };
     319             :         };
     320             :         u32                     mxcsr;          /* MXCSR Register State */
     321             :         u32                     mxcsr_mask;     /* MXCSR Mask           */
     322             : 
     323             :         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
     324             :         u32                     st_space[32];
     325             : 
     326             :         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
     327             :         u32                     xmm_space[64];
     328             : 
     329             :         u32                     padding[12];
     330             : 
     331             :         union {
     332             :                 u32             padding1[12];
     333             :                 u32             sw_reserved[12];
     334             :         };
     335             : 
     336           1 : } __attribute__((aligned(16)));
     337             : 
     338             : struct i387_soft_struct {
     339             :         u32                     cwd;
     340             :         u32                     swd;
     341             :         u32                     twd;
     342             :         u32                     fip;
     343             :         u32                     fcs;
     344             :         u32                     foo;
     345             :         u32                     fos;
     346             :         /* 8*10 bytes for each FP-reg = 80 bytes: */
     347             :         u32                     st_space[20];
     348             :         u8                      ftop;
     349             :         u8                      changed;
     350             :         u8                      lookahead;
     351             :         u8                      no_update;
     352             :         u8                      rm;
     353             :         u8                      alimit;
     354             :         struct math_emu_info    *info;
     355             :         u32                     entry_eip;
     356             : };
     357           1 : 
     358             : struct ymmh_struct {
     359             :         /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
     360             :         u32 ymmh_space[64];
     361             : };
     362           1 : 
     363             : struct xsave_hdr_struct {
     364             :         u64 xstate_bv;
     365             :         u64 reserved1[2];
     366             :         u64 reserved2[5];
     367             : } __attribute__((packed));
     368           1 : 
     369             : struct xsave_struct {
     370             :         struct i387_fxsave_struct i387;
     371             :         struct xsave_hdr_struct xsave_hdr;
     372             :         struct ymmh_struct ymmh;
     373             :         /* new processor state extensions will go here */
     374           1 : } __attribute__ ((packed, aligned (64)));
     375             : 
     376             : union thread_xstate {
     377             :         struct i387_fsave_struct        fsave;
     378             :         struct i387_fxsave_struct       fxsave;
     379             :         struct i387_soft_struct         soft;
     380             :         struct xsave_struct             xsave;
     381             : };
     382             : 
     383             : #ifdef CONFIG_X86_64
     384             : DECLARE_PER_CPU(struct orig_ist, orig_ist);
     385             : 
     386             : union irq_stack_union {
     387             :         char irq_stack[IRQ_STACK_SIZE];
     388             :         /*
     389             :          * GCC hardcodes the stack canary as %gs:40.  Since the
     390             :          * irq_stack is the object at %gs:0, we reserve the bottom
     391             :          * 48 bytes of the irq stack for the canary.
     392             :          */
     393             :         struct {
     394             :                 char gs_base[40];
     395             :                 unsigned long stack_canary;
     396             :         };
     397             : };
     398             : 
     399             : DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
     400             : DECLARE_INIT_PER_CPU(irq_stack_union);
     401             : 
     402             : DECLARE_PER_CPU(char *, irq_stack_ptr);
     403             : DECLARE_PER_CPU(unsigned int, irq_count);
     404             : extern unsigned long kernel_eflags;
     405             : extern asmlinkage void ignore_sysret(void);
     406             : #else   /* X86_64 */
     407             : #ifdef CONFIG_CC_STACKPROTECTOR
     408             : /*
     409             :  * Make sure stack canary segment base is cached-aligned:
     410             :  *   "For Intel Atom processors, avoid non zero segment base address
     411             :  *    that is not aligned to cache line boundary at all cost."
     412             :  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
     413             :  */
     414             : struct stack_canary {
     415             :         char __pad[20];         /* canary at %gs:20 */
     416             :         unsigned long canary;
     417             : };
     418             : DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
     419             : #endif
     420             : #endif  /* X86_64 */
     421             : 
     422             : extern unsigned int xstate_size;
     423             : extern void free_thread_xstate(struct task_struct *);
     424           1 : extern struct kmem_cache *task_xstate_cachep;
     425           1 : 
     426           2 : struct perf_event;
     427             : 
     428             : struct thread_struct {
     429             :         /* Cached TLS descriptors: */
     430             :         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
     431             :         unsigned long           sp0;
     432             :         unsigned long           sp;
     433             : #ifdef CONFIG_X86_32
     434             :         unsigned long           sysenter_cs;
     435             : #else
     436             :         unsigned long           usersp; /* Copy from PDA */
     437             :         unsigned short          es;
     438             :         unsigned short          ds;
     439             :         unsigned short          fsindex;
     440             :         unsigned short          gsindex;
     441             : #endif
     442             : #ifdef CONFIG_X86_32
     443             :         unsigned long           ip;
     444             : #endif
     445             : #ifdef CONFIG_X86_64
     446             :         unsigned long           fs;
     447             : #endif
     448             :         unsigned long           gs;
     449             :         /* Save middle states of ptrace breakpoints */
     450             :         struct perf_event       *ptrace_bps[HBP_NUM];
     451             :         /* Debug status used for traps, single steps, etc... */
     452             :         unsigned long           debugreg6;
     453             :         /* Keep track of the exact dr7 value set by the user */
     454             :         unsigned long           ptrace_dr7;
     455             :         /* Fault info: */
     456             :         unsigned long           cr2;
     457             :         unsigned long           trap_no;
     458             :         unsigned long           error_code;
     459             :         /* floating point and extended processor state */
     460             :         union thread_xstate     *xstate;
     461             : #ifdef CONFIG_X86_32
     462             :         /* Virtual 86 mode info */
     463             :         struct vm86_struct __user *vm86_info;
     464             :         unsigned long           screen_bitmap;
     465             :         unsigned long           v86flags;
     466             :         unsigned long           v86mask;
     467             :         unsigned long           saved_sp0;
     468             :         unsigned int            saved_fs;
     469             :         unsigned int            saved_gs;
     470             : #endif
     471             :         /* IO permissions: */
     472             :         unsigned long           *io_bitmap_ptr;
     473             :         unsigned long           iopl;
     474             :         /* Max allowed port in the bitmap, in bytes: */
     475             :         unsigned                io_bitmap_max;
     476             : /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
     477             :         unsigned long   debugctlmsr;
     478             :         /* Debug Store context; see asm/ds.h */
     479             :         struct ds_context       *ds_ctx;
     480             : };
     481             : 
     482             : static inline unsigned long native_get_debugreg(int regno)
     483             : {
     484             :         unsigned long val = 0;  /* Damn you, gcc! */
     485             : 
     486             :         switch (regno) {
     487             :         case 0:
     488             :                 asm("mov %%db0, %0" :"=r" (val));
     489             :                 break;
     490             :         case 1:
     491             :                 asm("mov %%db1, %0" :"=r" (val));
     492             :                 break;
     493             :         case 2:
     494             :                 asm("mov %%db2, %0" :"=r" (val));
     495             :                 break;
     496             :         case 3:
     497             :                 asm("mov %%db3, %0" :"=r" (val));
     498             :                 break;
     499             :         case 6:
     500             :                 asm("mov %%db6, %0" :"=r" (val));
     501             :                 break;
     502             :         case 7:
     503             :                 asm("mov %%db7, %0" :"=r" (val));
     504             :                 break;
     505             :         default:
     506             :                 BUG();
     507             :         }
     508             :         return val;
     509             : }
     510             : 
     511             : static inline void native_set_debugreg(int regno, unsigned long value)
     512             : {
     513             :         switch (regno) {
     514             :         case 0:
     515             :                 asm("mov %0, %%db0"   ::"r" (value));
     516             :                 break;
     517             :         case 1:
     518             :                 asm("mov %0, %%db1"   ::"r" (value));
     519             :                 break;
     520             :         case 2:
     521             :                 asm("mov %0, %%db2"   ::"r" (value));
     522             :                 break;
     523             :         case 3:
     524             :                 asm("mov %0, %%db3"   ::"r" (value));
     525             :                 break;
     526             :         case 6:
     527             :                 asm("mov %0, %%db6"   ::"r" (value));
     528             :                 break;
     529             :         case 7:
     530             :                 asm("mov %0, %%db7"   ::"r" (value));
     531             :                 break;
     532             :         default:
     533             :                 BUG();
     534             :         }
     535             : }
     536             : 
     537             : /*
     538             :  * Set IOPL bits in EFLAGS from given mask
     539             :  */
     540             : static inline void native_set_iopl_mask(unsigned mask)
     541             : {
     542             : #ifdef CONFIG_X86_32
     543             :         unsigned int reg;
     544             : 
     545             :         asm volatile ("pushfl;"
     546             :                       "popl %0;"
     547             :                       "andl %1, %0;"
     548             :                       "orl %2, %0;"
     549             :                       "pushl %0;"
     550             :                       "popfl"
     551             :                       : "=&r" (reg)
     552             :                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
     553             : #endif
     554             : }
     555             : 
     556             : static inline void
     557             : native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
     558             : {
     559             :         tss->x86_tss.sp0 = thread->sp0;
     560             : #ifdef CONFIG_X86_32
     561             :         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
     562             :         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
     563             :                 tss->x86_tss.ss1 = thread->sysenter_cs;
     564             :                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
     565             :         }
     566             : #endif
     567             : }
     568             : 
     569             : static inline void native_swapgs(void)
     570             : {
     571             : #ifdef CONFIG_X86_64
     572             :         asm volatile("swapgs" ::: "memory");
     573             : #endif
     574             : }
     575             : 
     576             : #ifdef CONFIG_PARAVIRT
     577             : #include <asm/paravirt.h>
     578             : #else
     579             : #define __cpuid                 native_cpuid
     580             : #define paravirt_enabled()      0
     581             : 
     582             : /*
     583             :  * These special macros can be used to get or set a debugging register
     584             :  */
     585             : #define get_debugreg(var, register)                             \
     586             :         (var) = native_get_debugreg(register)
     587             : #define set_debugreg(value, register)                           \
     588             :         native_set_debugreg(register, value)
     589             : 
     590             : static inline void load_sp0(struct tss_struct *tss,
     591             :                             struct thread_struct *thread)
     592             : {
     593             :         native_load_sp0(tss, thread);
     594             : }
     595             : 
     596             : #define set_iopl_mask native_set_iopl_mask
     597             : #endif /* CONFIG_PARAVIRT */
     598             : 
     599             : /*
     600             :  * Save the cr4 feature set we're using (ie
     601             :  * Pentium 4MB enable and PPro Global page
     602             :  * enable), so that any CPU's that boot up
     603             :  * after us can get the correct flags.
     604             :  */
     605             : extern unsigned long            mmu_cr4_features;
     606             : 
     607             : static inline void set_in_cr4(unsigned long mask)
     608             : {
     609             :         unsigned cr4;
     610             : 
     611             :         mmu_cr4_features |= mask;
     612             :         cr4 = read_cr4();
     613             :         cr4 |= mask;
     614             :         write_cr4(cr4);
     615             : }
     616             : 
     617             : static inline void clear_in_cr4(unsigned long mask)
     618             : {
     619             :         unsigned cr4;
     620             : 
     621             :         mmu_cr4_features &= ~mask;
     622             :         cr4 = read_cr4();
     623             :         cr4 &= ~mask;
     624             :         write_cr4(cr4);
     625             : }
     626             : 
     627             : typedef struct {
     628             :         unsigned long           seg;
     629           2 : } mm_segment_t;
     630             : 
     631             : 
     632             : /*
     633             :  * create a kernel thread without removing it from tasklists
     634             :  */
     635             : extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
     636             : 
     637             : /* Free all resources held by a thread. */
     638             : extern void release_thread(struct task_struct *);
     639             : 
     640             : /* Prepare to copy thread state - unlazy all lazy state */
     641             : extern void prepare_to_copy(struct task_struct *tsk);
     642             : 
     643             : unsigned long get_wchan(struct task_struct *p);
     644             : 
     645             : /*
     646             :  * Generic CPUID function
     647             :  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
     648             :  * resulting in stale register contents being returned.
     649             :  */
     650             : static inline void cpuid(unsigned int op,
     651             :                          unsigned int *eax, unsigned int *ebx,
     652             :                          unsigned int *ecx, unsigned int *edx)
     653             : {
     654             :         *eax = op;
     655             :         *ecx = 0;
     656             :         __cpuid(eax, ebx, ecx, edx);
     657             : }
     658             : 
     659             : /* Some CPUID calls want 'count' to be placed in ecx */
     660             : static inline void cpuid_count(unsigned int op, int count,
     661             :                                unsigned int *eax, unsigned int *ebx,
     662             :                                unsigned int *ecx, unsigned int *edx)
     663             : {
     664             :         *eax = op;
     665             :         *ecx = count;
     666             :         __cpuid(eax, ebx, ecx, edx);
     667             : }
     668             : 
     669             : /*
     670             :  * CPUID functions returning a single datum
     671             :  */
     672             : static inline unsigned int cpuid_eax(unsigned int op)
     673             : {
     674             :         unsigned int eax, ebx, ecx, edx;
     675             : 
     676             :         cpuid(op, &eax, &ebx, &ecx, &edx);
     677             : 
     678             :         return eax;
     679             : }
     680             : 
     681             : static inline unsigned int cpuid_ebx(unsigned int op)
     682             : {
     683             :         unsigned int eax, ebx, ecx, edx;
     684             : 
     685             :         cpuid(op, &eax, &ebx, &ecx, &edx);
     686             : 
     687             :         return ebx;
     688             : }
     689             : 
     690             : static inline unsigned int cpuid_ecx(unsigned int op)
     691             : {
     692             :         unsigned int eax, ebx, ecx, edx;
     693             : 
     694             :         cpuid(op, &eax, &ebx, &ecx, &edx);
     695             : 
     696             :         return ecx;
     697             : }
     698             : 
     699             : static inline unsigned int cpuid_edx(unsigned int op)
     700             : {
     701             :         unsigned int eax, ebx, ecx, edx;
     702             : 
     703             :         cpuid(op, &eax, &ebx, &ecx, &edx);
     704             : 
     705             :         return edx;
     706             : }
     707             : 
     708             : /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
     709             : static inline void rep_nop(void)
     710             : {
     711             :         asm volatile("rep; nop" ::: "memory");
     712             : }
     713             : 
     714             : static inline void cpu_relax(void)
     715             : {
     716             :         rep_nop();
     717             : }
     718             : 
     719             : /* Stop speculative execution and prefetching of modified code. */
     720             : static inline void sync_core(void)
     721             : {
     722             :         int tmp;
     723             : 
     724             : #if defined(CONFIG_M386) || defined(CONFIG_M486)
     725             :         if (boot_cpu_data.x86 < 5)
     726             :                 /* There is no speculative execution.
     727             :                  * jmp is a barrier to prefetching. */
     728             :                 asm volatile("jmp 1f\n1:\n" ::: "memory");
     729             :         else
     730             : #endif
     731             :                 /* cpuid is a barrier to speculative execution.
     732             :                  * Prefetched instructions are automatically
     733             :                  * invalidated when modified. */
     734             :                 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
     735             :                              : "ebx", "ecx", "edx", "memory");
     736             : }
     737             : 
     738             : static inline void __monitor(const void *eax, unsigned long ecx,
     739             :                              unsigned long edx)
     740             : {
     741             :         /* "monitor %eax, %ecx, %edx;" */
     742             :         asm volatile(".byte 0x0f, 0x01, 0xc8;"
     743             :                      :: "a" (eax), "c" (ecx), "d"(edx));
     744             : }
     745             : 
     746             : static inline void __mwait(unsigned long eax, unsigned long ecx)
     747             : {
     748             :         /* "mwait %eax, %ecx;" */
     749             :         asm volatile(".byte 0x0f, 0x01, 0xc9;"
     750             :                      :: "a" (eax), "c" (ecx));
     751             : }
     752             : 
     753             : static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
     754             : {
     755             :         trace_hardirqs_on();
     756             :         /* "mwait %eax, %ecx;" */
     757             :         asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
     758             :                      :: "a" (eax), "c" (ecx));
     759             : }
     760             : 
     761             : extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
     762             : 
     763             : extern void select_idle_routine(const struct cpuinfo_x86 *c);
     764             : extern void init_c1e_mask(void);
     765             : 
     766             : extern unsigned long            boot_option_idle_override;
     767             : extern unsigned long            idle_halt;
     768             : extern unsigned long            idle_nomwait;
     769             : 
     770             : /*
     771             :  * on systems with caches, caches must be flashed as the absolute
     772             :  * last instruction before going into a suspended halt.  Otherwise,
     773             :  * dirty data can linger in the cache and become stale on resume,
     774             :  * leading to strange errors.
     775             :  *
     776             :  * perform a variety of operations to guarantee that the compiler
     777             :  * will not reorder instructions.  wbinvd itself is serializing
     778             :  * so the processor will not reorder.
     779             :  *
     780             :  * Systems without cache can just go into halt.
     781             :  */
     782             : static inline void wbinvd_halt(void)
     783             : {
     784             :         mb();
     785             :         /* check for clflush to determine if wbinvd is legal */
     786             :         if (cpu_has_clflush)
     787             :                 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
     788             :         else
     789             :                 while (1)
     790             :                         halt();
     791             : }
     792             : 
     793             : extern void enable_sep_cpu(void);
     794             : extern int sysenter_setup(void);
     795             : 
     796             : /* Defined in head.S */
     797             : extern struct desc_ptr          early_gdt_descr;
     798             : 
     799             : extern void cpu_set_gdt(int);
     800             : extern void switch_to_new_gdt(int);
     801             : extern void load_percpu_segment(int);
     802             : extern void cpu_init(void);
     803             : 
     804             : static inline unsigned long get_debugctlmsr(void)
     805             : {
     806             :     unsigned long debugctlmsr = 0;
     807             : 
     808             : #ifndef CONFIG_X86_DEBUGCTLMSR
     809             :         if (boot_cpu_data.x86 < 6)
     810             :                 return 0;
     811             : #endif
     812             :         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
     813             : 
     814             :     return debugctlmsr;
     815             : }
     816             : 
     817             : static inline unsigned long get_debugctlmsr_on_cpu(int cpu)
     818             : {
     819             :         u64 debugctlmsr = 0;
     820             :         u32 val1, val2;
     821             : 
     822             : #ifndef CONFIG_X86_DEBUGCTLMSR
     823             :         if (boot_cpu_data.x86 < 6)
     824             :                 return 0;
     825             : #endif
     826             :         rdmsr_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, &val1, &val2);
     827             :         debugctlmsr = val1 | ((u64)val2 << 32);
     828             : 
     829             :         return debugctlmsr;
     830             : }
     831             : 
     832             : static inline void update_debugctlmsr(unsigned long debugctlmsr)
     833             : {
     834             : #ifndef CONFIG_X86_DEBUGCTLMSR
     835             :         if (boot_cpu_data.x86 < 6)
     836             :                 return;
     837             : #endif
     838             :         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
     839             : }
     840             : 
     841             : static inline void update_debugctlmsr_on_cpu(int cpu,
     842             :                                              unsigned long debugctlmsr)
     843             : {
     844             : #ifndef CONFIG_X86_DEBUGCTLMSR
     845             :         if (boot_cpu_data.x86 < 6)
     846             :                 return;
     847             : #endif
     848             :         wrmsr_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR,
     849             :                      (u32)((u64)debugctlmsr),
     850             :                      (u32)((u64)debugctlmsr >> 32));
     851             : }
     852             : 
     853             : /*
     854             :  * from system description table in BIOS. Mostly for MCA use, but
     855             :  * others may find it useful:
     856             :  */
     857             : extern unsigned int             machine_id;
     858             : extern unsigned int             machine_submodel_id;
     859             : extern unsigned int             BIOS_revision;
     860             : 
     861             : /* Boot loader type from the setup header: */
     862             : extern int                      bootloader_type;
     863             : extern int                      bootloader_version;
     864             : 
     865             : extern char                     ignore_fpu_irq;
     866             : 
     867             : #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
     868             : #define ARCH_HAS_PREFETCHW
     869             : #define ARCH_HAS_SPINLOCK_PREFETCH
     870             : 
     871             : #ifdef CONFIG_X86_32
     872             : # define BASE_PREFETCH          ASM_NOP4
     873             : # define ARCH_HAS_PREFETCH
     874             : #else
     875             : # define BASE_PREFETCH          "prefetcht0 (%1)"
     876             : #endif
     877             : 
     878             : /*
     879             :  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
     880             :  *
     881             :  * It's not worth to care about 3dnow prefetches for the K6
     882             :  * because they are microcoded there and very slow.
     883             :  */
     884             : static inline void prefetch(const void *x)
     885             : {
     886             :         alternative_input(BASE_PREFETCH,
     887             :                           "prefetchnta (%1)",
     888             :                           X86_FEATURE_XMM,
     889             :                           "r" (x));
     890             : }
     891             : 
     892             : /*
     893             :  * 3dnow prefetch to get an exclusive cache line.
     894             :  * Useful for spinlocks to avoid one state transition in the
     895             :  * cache coherency protocol:
     896             :  */
     897             : static inline void prefetchw(const void *x)
     898             : {
     899             :         alternative_input(BASE_PREFETCH,
     900             :                           "prefetchw (%1)",
     901             :                           X86_FEATURE_3DNOW,
     902             :                           "r" (x));
     903             : }
     904             : 
     905             : static inline void spin_lock_prefetch(const void *x)
     906             : {
     907             :         prefetchw(x);
     908             : }
     909             : 
     910             : #ifdef CONFIG_X86_32
     911             : /*
     912             :  * User space process size: 3GB (default).
     913             :  */
     914             : #define TASK_SIZE               PAGE_OFFSET
     915             : #define TASK_SIZE_MAX           TASK_SIZE
     916             : #define STACK_TOP               TASK_SIZE
     917             : #define STACK_TOP_MAX           STACK_TOP
     918             : 
     919             : #define INIT_THREAD  {                                                    \
     920             :         .sp0                    = sizeof(init_stack) + (long)&init_stack, \
     921             :         .vm86_info              = NULL,                                   \
     922             :         .sysenter_cs            = __KERNEL_CS,                            \
     923             :         .io_bitmap_ptr          = NULL,                                   \
     924             : }
     925             : 
     926             : /*
     927             :  * Note that the .io_bitmap member must be extra-big. This is because
     928             :  * the CPU will access an additional byte beyond the end of the IO
     929             :  * permission bitmap. The extra byte must be all 1 bits, and must
     930             :  * be within the limit.
     931             :  */
     932             : #define INIT_TSS  {                                                       \
     933             :         .x86_tss = {                                                      \
     934             :                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
     935             :                 .ss0            = __KERNEL_DS,                            \
     936             :                 .ss1            = __KERNEL_CS,                            \
     937             :                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,               \
     938             :          },                                                               \
     939             :         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },       \
     940             : }
     941             : 
     942             : extern unsigned long thread_saved_pc(struct task_struct *tsk);
     943             : 
     944             : #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
     945             : #define KSTK_TOP(info)                                                 \
     946             : ({                                                                     \
     947             :        unsigned long *__ptr = (unsigned long *)(info);                 \
     948             :        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
     949             : })
     950             : 
     951             : /*
     952             :  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
     953             :  * This is necessary to guarantee that the entire "struct pt_regs"
     954             :  * is accessable even if the CPU haven't stored the SS/ESP registers
     955             :  * on the stack (interrupt gate does not save these registers
     956             :  * when switching to the same priv ring).
     957             :  * Therefore beware: accessing the ss/esp fields of the
     958             :  * "struct pt_regs" is possible, but they may contain the
     959             :  * completely wrong values.
     960             :  */
     961             : #define task_pt_regs(task)                                             \
     962             : ({                                                                     \
     963             :        struct pt_regs *__regs__;                                       \
     964             :        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
     965             :        __regs__ - 1;                                                   \
     966             : })
     967             : 
     968             : #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
     969             : 
     970             : #else
     971             : /*
     972             :  * User space process size. 47bits minus one guard page.
     973             :  */
     974             : #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
     975             : 
     976             : /* This decides where the kernel will search for a free chunk of vm
     977             :  * space during mmap's.
     978             :  */
     979             : #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
     980             :                                         0xc0000000 : 0xFFFFe000)
     981             : 
     982             : #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? \
     983             :                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
     984             : #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? \
     985             :                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
     986             : 
     987             : #define STACK_TOP               TASK_SIZE
     988             : #define STACK_TOP_MAX           TASK_SIZE_MAX
     989             : 
     990             : #define INIT_THREAD  { \
     991             :         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
     992             : }
     993             : 
     994             : #define INIT_TSS  { \
     995             :         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
     996             : }
     997             : 
     998             : /*
     999             :  * Return saved PC of a blocked thread.
    1000             :  * What is this good for? it will be always the scheduler or ret_from_fork.
    1001             :  */
    1002             : #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
    1003             : 
    1004             : #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
    1005             : extern unsigned long KSTK_ESP(struct task_struct *task);
    1006             : #endif /* CONFIG_X86_64 */
    1007             : 
    1008             : extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
    1009             :                                                unsigned long new_sp);
    1010             : 
    1011             : /*
    1012             :  * This decides where the kernel will search for a free chunk of vm
    1013             :  * space during mmap's.
    1014             :  */
    1015             : #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
    1016             : 
    1017             : #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
    1018             : 
    1019             : /* Get/set a process' ability to use the timestamp counter instruction */
    1020             : #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
    1021             : #define SET_TSC_CTL(val)        set_tsc_mode((val))
    1022             : 
    1023             : extern int get_tsc_mode(unsigned long adr);
    1024             : extern int set_tsc_mode(unsigned int val);
    1025             : 
    1026             : extern int amd_get_nb_id(int cpu);
    1027             : 
    1028             : struct aperfmperf {
    1029             :         u64 aperf, mperf;
    1030             : };
    1031             : 
    1032             : static inline void get_aperfmperf(struct aperfmperf *am)
    1033             : {
    1034             :         WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
    1035             : 
    1036             :         rdmsrl(MSR_IA32_APERF, am->aperf);
    1037             :         rdmsrl(MSR_IA32_MPERF, am->mperf);
    1038             : }
    1039             : 
    1040             : #define APERFMPERF_SHIFT 10
    1041             : 
    1042             : static inline
    1043             : unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
    1044             :                                     struct aperfmperf *new)
    1045             : {
    1046             :         u64 aperf = new->aperf - old->aperf;
    1047             :         u64 mperf = new->mperf - old->mperf;
    1048             :         unsigned long ratio = aperf;
    1049             : 
    1050             :         mperf >>= APERFMPERF_SHIFT;
    1051             :         if (mperf)
    1052             :                 ratio = div64_u64(aperf, mperf);
    1053             : 
    1054             :         return ratio;
    1055             : }
    1056             : 
    1057             : /*
    1058             :  * AMD errata checking
    1059             :  */
    1060             : #ifdef CONFIG_CPU_SUP_AMD
    1061             : extern const int amd_erratum_400[];
    1062             : extern bool cpu_has_amd_erratum(const int *);
    1063             : 
    1064             : #define AMD_LEGACY_ERRATUM(...)         { -1, __VA_ARGS__, 0 }
    1065             : #define AMD_OSVW_ERRATUM(osvw_id, ...)  { osvw_id, __VA_ARGS__, 0 }
    1066             : #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
    1067             :         ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
    1068             : #define AMD_MODEL_RANGE_FAMILY(range)   (((range) >> 24) & 0xff)
    1069             : #define AMD_MODEL_RANGE_START(range)    (((range) >> 12) & 0xfff)
    1070             : #define AMD_MODEL_RANGE_END(range)      ((range) & 0xfff)
    1071             : 
    1072             : #else
    1073             : #define cpu_has_amd_erratum(x)  (false)
    1074             : #endif /* CONFIG_CPU_SUP_AMD */
    1075             : 
    1076             : #endif /* _ASM_X86_PROCESSOR_H */

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