LCOV - code coverage report
Current view: top level - drivers/usb/host - ohci-q.c (source / functions) Hit Total Coverage
Test: coverage.info Lines: 601 601 100.0 %
Date: 2017-01-25 Functions: 17 17 100.0 %

          Line data    Source code
       1             : /*
       2             :  * OHCI HCD (Host Controller Driver) for USB.
       3             :  *
       4             :  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
       5             :  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
       6             :  *
       7             :  * This file is licenced under the GPL.
       8             :  */
       9             : 
      10             : #include <linux/irq.h>
      11             : 
      12             : static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
      13             : {
      14          27 :         int             last = urb_priv->length - 1;
      15           9 : 
      16          27 :         if (last >= 0) {
      17             :                 int             i;
      18             :                 struct td       *td;
      19             : 
      20          54 :                 for (i = 0; i <= last; i++) {
      21          36 :                         td = urb_priv->td [i];
      22          27 :                         if (td)
      23          27 :                                 td_free (hc, td);
      24             :                 }
      25             :         }
      26             : 
      27          36 :         list_del (&urb_priv->pending);
      28           9 :         kfree (urb_priv);
      29           9 : }
      30             : 
      31             : /*-------------------------------------------------------------------------*/
      32             : 
      33             : /*
      34             :  * URB goes back to driver, and isn't reissued.
      35             :  * It's completely gone from HC data structures.
      36             :  * PRECONDITION:  ohci lock held, irqs blocked.
      37             :  */
      38             : static void
      39             : finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
      40             : __releases(ohci->lock)
      41           5 : __acquires(ohci->lock)
      42           5 : {
      43           5 :         // ASSERT (urb->hcpriv != 0);
      44           5 : 
      45          20 :         urb_free_priv (ohci, urb->hcpriv);
      46          25 :         if (likely(status == -EINPROGRESS))
      47          10 :                 status = 0;
      48           5 : 
      49          10 :         switch (usb_pipetype (urb->pipe)) {
      50          25 :         case PIPE_ISOCHRONOUS:
      51          15 :                 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
      52          20 :                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
      53          20 :                         if (quirk_amdiso(ohci))
      54          15 :                                 quirk_amd_pll(1);
      55          30 :                         if (quirk_amdprefetch(ohci))
      56          15 :                                 sb800_prefetch(ohci, 0);
      57             :                 }
      58          15 :                 break;
      59          20 :         case PIPE_INTERRUPT:
      60          15 :                 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
      61           5 :                 break;
      62           5 :         }
      63             : 
      64           5 : #ifdef OHCI_VERBOSE_DEBUG
      65             :         urb_print(urb, "RET", usb_pipeout (urb->pipe), status);
      66             : #endif
      67             : 
      68             :         /* urb->complete() can reenter this HCD */
      69          55 :         usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
      70          10 :         spin_unlock (&ohci->lock);
      71          15 :         usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status);
      72          10 :         spin_lock (&ohci->lock);
      73             : 
      74             :         /* stop periodic dma if it's not needed */
      75          40 :         if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
      76             :                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
      77           5 :                 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
      78          10 :                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
      79             :         }
      80          15 : }
      81             : 
      82             : 
      83             : /*-------------------------------------------------------------------------*
      84             :  * ED handling functions
      85             :  *-------------------------------------------------------------------------*/
      86             : 
      87             : /* search for the right schedule branch to use for a periodic ed.
      88             :  * does some load balancing; returns the branch, or negative errno.
      89             :  */
      90             : static int balance (struct ohci_hcd *ohci, int interval, int load)
      91             : {
      92          12 :         int     i, branch = -ENOSPC;
      93           6 : 
      94           6 :         /* iso periods can be huge; iso tds specify frame numbers */
      95          12 :         if (interval > NUM_INTS)
      96           6 :                 interval = NUM_INTS;
      97             : 
      98             :         /* search for the least loaded schedule branch of that period
      99             :          * that has enough bandwidth left unreserved.
     100             :          */
     101          36 :         for (i = 0; i < interval ; i++) {
     102          42 :                 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
     103           6 :                         int     j;
     104             : 
     105             :                         /* usb 1.1 says 90% of one frame */
     106          30 :                         for (j = i; j < NUM_INTS; j += interval) {
     107          24 :                                 if ((ohci->load [j] + load) > 900)
     108          12 :                                         break;
     109             :                         }
     110          12 :                         if (j < NUM_INTS)
     111           6 :                                 continue;
     112          12 :                         branch = i;
     113             :                 }
     114             :         }
     115           6 :         return branch;
     116          12 : }
     117             : 
     118             : /*-------------------------------------------------------------------------*/
     119             : 
     120             : /* both iso and interrupt requests have periods; this routine puts them
     121             :  * into the schedule tree in the apppropriate place.  most iso devices use
     122             :  * 1msec periods, but that's not required.
     123             :  */
     124             : static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
     125             : {
     126           3 :         unsigned        i;
     127           3 : 
     128           3 :         ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
     129           3 :                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
     130           3 :                 ed, ed->branch, ed->load, ed->interval);
     131             : 
     132          27 :         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
     133          12 :                 struct ed       **prev = &ohci->periodic [i];
     134           6 :                 __hc32          *prev_p = &ohci->hcca->int_table [i];
     135           3 :                 struct ed       *here = *prev;
     136             : 
     137             :                 /* sorting each branch by period (slow before fast)
     138             :                  * lets us share the faster parts of the tree.
     139             :                  * (plus maybe: put interrupt eds before iso)
     140             :                  */
     141          15 :                 while (here && ed != here) {
     142          15 :                         if (ed->interval > here->interval)
     143           6 :                                 break;
     144           3 :                         prev = &here->ed_next;
     145           3 :                         prev_p = &here->hwNextED;
     146           3 :                         here = *prev;
     147           6 :                 }
     148           6 :                 if (ed != here) {
     149           3 :                         ed->ed_next = here;
     150           6 :                         if (here)
     151           3 :                                 ed->hwNextED = *prev_p;
     152           3 :                         wmb ();
     153           3 :                         *prev = ed;
     154           9 :                         *prev_p = cpu_to_hc32(ohci, ed->dma);
     155           3 :                         wmb();
     156             :                 }
     157          12 :                 ohci->load [i] += ed->load;
     158             :         }
     159          15 :         ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
     160           3 : }
     161             : 
     162             : /* link an ed into one of the HC chains */
     163             : 
     164             : static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
     165             : {
     166           3 :         int     branch;
     167           3 : 
     168           6 :         ed->state = ED_OPER;
     169           6 :         ed->ed_prev = NULL;
     170           6 :         ed->ed_next = NULL;
     171           6 :         ed->hwNextED = 0;
     172          36 :         if (quirk_zfmicro(ohci)
     173           3 :                         && (ed->type == PIPE_INTERRUPT)
     174             :                         && !(ohci->eds_scheduled++))
     175           9 :                 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
     176           6 :         wmb ();
     177             : 
     178             :         /* we care about rm_list when setting CLE/BLE in case the HC was at
     179             :          * work on some TD when CLE/BLE was turned off, and isn't quiesced
     180             :          * yet.  finish_unlinks() restarts as needed, some upcoming INTR_SF.
     181             :          *
     182             :          * control and bulk EDs are doubly linked (ed_next, ed_prev), but
     183             :          * periodic ones are singly linked (ed_next). that's because the
     184             :          * periodic schedule encodes a tree like figure 3-5 in the ohci
     185             :          * spec:  each qh can have several "previous" nodes, and the tree
     186             :          * doesn't have unused/idle descriptors.
     187             :          */
     188             :         switch (ed->type) {
     189          24 :         case PIPE_CONTROL:
     190          18 :                 if (ohci->ed_controltail == NULL) {
     191          33 :                         WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
     192           9 :                         ohci_writel (ohci, ed->dma,
     193             :                                         &ohci->regs->ed_controlhead);
     194             :                 } else {
     195           6 :                         ohci->ed_controltail->ed_next = ed;
     196          18 :                         ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
     197             :                                                                 ed->dma);
     198             :                 }
     199           6 :                 ed->ed_prev = ohci->ed_controltail;
     200          36 :                 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
     201           6 :                         wmb();
     202           6 :                         ohci->hc_control |= OHCI_CTRL_CLE;
     203          12 :                         ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
     204           6 :                         ohci_writel (ohci, ohci->hc_control,
     205             :                                         &ohci->regs->control);
     206             :                 }
     207           9 :                 ohci->ed_controltail = ed;
     208           9 :                 break;
     209           6 : 
     210          24 :         case PIPE_BULK:
     211          18 :                 if (ohci->ed_bulktail == NULL) {
     212          33 :                         WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
     213           9 :                         ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
     214             :                 } else {
     215           6 :                         ohci->ed_bulktail->ed_next = ed;
     216          18 :                         ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
     217             :                                                                 ed->dma);
     218             :                 }
     219           6 :                 ed->ed_prev = ohci->ed_bulktail;
     220          36 :                 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
     221           6 :                         wmb();
     222           6 :                         ohci->hc_control |= OHCI_CTRL_BLE;
     223          12 :                         ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
     224           6 :                         ohci_writel (ohci, ohci->hc_control,
     225             :                                         &ohci->regs->control);
     226             :                 }
     227           9 :                 ohci->ed_bulktail = ed;
     228           9 :                 break;
     229           6 : 
     230             :         // case PIPE_INTERRUPT:
     231             :         // case PIPE_ISOCHRONOUS:
     232           6 :         default:
     233          30 :                 branch = balance (ohci, ed->interval, ed->load);
     234           6 :                 if (branch < 0) {
     235             :                         ohci_dbg (ohci,
     236             :                                 "ERR %d, interval %d msecs, load %d\n",
     237             :                                 branch, ed->interval, ed->load);
     238             :                         // FIXME if there are TDs queued, fail them!
     239           3 :                         return branch;
     240             :                 }
     241           3 :                 ed->branch = branch;
     242           6 :                 periodic_link (ohci, ed);
     243             :         }
     244           3 : 
     245             :         /* the HC may not see the schedule updates yet, but if it does
     246           3 :          * then they'll be properly ordered.
     247             :          */
     248          21 :         return 0;
     249             : }
     250             : 
     251             : /*-------------------------------------------------------------------------*/
     252             : 
     253             : /* scan the periodic table to find and unlink this ED */
     254             : static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
     255             : {
     256           3 :         int     i;
     257           3 : 
     258          24 :         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
     259           9 :                 struct ed       *temp;
     260           9 :                 struct ed       **prev = &ohci->periodic [i];
     261           3 :                 __hc32          *prev_p = &ohci->hcca->int_table [i];
     262             : 
     263          18 :                 while (*prev && (temp = *prev) != ed) {
     264           6 :                         prev_p = &temp->hwNextED;
     265           6 :                         prev = &temp->ed_next;
     266           3 :                 }
     267           6 :                 if (*prev) {
     268           6 :                         *prev_p = ed->hwNextED;
     269           3 :                         *prev = ed->ed_next;
     270             :                 }
     271           6 :                 ohci->load [i] -= ed->load;
     272             :         }
     273          18 :         ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
     274           3 : 
     275             :         ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
     276             :                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
     277             :                 ed, ed->branch, ed->load, ed->interval);
     278             : }
     279             : 
     280             : /* unlink an ed from one of the HC chains.
     281             :  * just the link to the ed is unlinked.
     282             :  * the link from the ed still points to another operational ed or 0
     283             :  * so the HC can eventually finish the processing of the unlinked ed
     284             :  * (assuming it already started that, which needn't be true).
     285             :  *
     286             :  * ED_UNLINK is a transient state: the HC may still see this ED, but soon
     287             :  * it won't.  ED_SKIP means the HC will finish its current transaction,
     288             :  * but won't start anything new.  The TD queue may still grow; device
     289             :  * drivers don't know about this HCD-internal state.
     290             :  *
     291             :  * When the HC can't see the ED, something changes ED_UNLINK to one of:
     292             :  *
     293             :  *  - ED_OPER: when there's any request queued, the ED gets rescheduled
     294             :  *    immediately.  HC should be working on them.
     295             :  *
     296             :  *  - ED_IDLE:  when there's no TD queue. there's no reason for the HC
     297             :  *    to care about this ED; safe to disable the endpoint.
     298             :  *
     299             :  * When finish_unlinks() runs later, after SOF interrupt, it will often
     300             :  * complete one or more URB unlinks before making that state change.
     301             :  */
     302             : static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
     303             : {
     304          12 :         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
     305           6 :         wmb ();
     306           6 :         ed->state = ED_UNLINK;
     307             : 
     308             :         /* To deschedule something from the control or bulk list, just
     309             :          * clear CLE/BLE and wait.  There's no safe way to scrub out list
     310             :          * head/current registers until later, and "later" isn't very
     311             :          * tightly specified.  Figure 6-5 and Section 6.4.2.2 show how
     312             :          * the HC is reading the ED queues (while we modify them).
     313             :          *
     314             :          * For now, ed_schedule() is "later".  It might be good paranoia
     315             :          * to scrub those registers in finish_unlinks(), in case of bugs
     316             :          * that make the HC try to use them.
     317             :          */
     318             :         switch (ed->type) {
     319          12 :         case PIPE_CONTROL:
     320             :                 /* remove ED from the HC's list: */
     321           9 :                 if (ed->ed_prev == NULL) {
     322           6 :                         if (!ed->hwNextED) {
     323           3 :                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
     324           6 :                                 ohci_writel (ohci, ohci->hc_control,
     325             :                                                 &ohci->regs->control);
     326             :                                 // a ohci_readl() later syncs CLE with the HC
     327             :                         } else
     328          12 :                                 ohci_writel (ohci,
     329             :                                         hc32_to_cpup (ohci, &ed->hwNextED),
     330             :                                         &ohci->regs->ed_controlhead);
     331             :                 } else {
     332           3 :                         ed->ed_prev->ed_next = ed->ed_next;
     333           3 :                         ed->ed_prev->hwNextED = ed->hwNextED;
     334             :                 }
     335             :                 /* remove ED from the HCD's list: */
     336          27 :                 if (ohci->ed_controltail == ed) {
     337           9 :                         ohci->ed_controltail = ed->ed_prev;
     338          27 :                         if (ohci->ed_controltail)
     339           9 :                                 ohci->ed_controltail->ed_next = NULL;
     340          27 :                 } else if (ed->ed_next) {
     341           9 :                         ed->ed_next->ed_prev = ed->ed_prev;
     342             :                 }
     343           9 :                 break;
     344           3 : 
     345          12 :         case PIPE_BULK:
     346             :                 /* remove ED from the HC's list: */
     347           9 :                 if (ed->ed_prev == NULL) {
     348           6 :                         if (!ed->hwNextED) {
     349           3 :                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
     350           6 :                                 ohci_writel (ohci, ohci->hc_control,
     351             :                                                 &ohci->regs->control);
     352             :                                 // a ohci_readl() later syncs BLE with the HC
     353             :                         } else
     354          12 :                                 ohci_writel (ohci,
     355             :                                         hc32_to_cpup (ohci, &ed->hwNextED),
     356             :                                         &ohci->regs->ed_bulkhead);
     357             :                 } else {
     358           3 :                         ed->ed_prev->ed_next = ed->ed_next;
     359           3 :                         ed->ed_prev->hwNextED = ed->hwNextED;
     360             :                 }
     361             :                 /* remove ED from the HCD's list: */
     362          27 :                 if (ohci->ed_bulktail == ed) {
     363           9 :                         ohci->ed_bulktail = ed->ed_prev;
     364          27 :                         if (ohci->ed_bulktail)
     365           9 :                                 ohci->ed_bulktail->ed_next = NULL;
     366          27 :                 } else if (ed->ed_next) {
     367           9 :                         ed->ed_next->ed_prev = ed->ed_prev;
     368             :                 }
     369           9 :                 break;
     370           3 : 
     371             :         // case PIPE_INTERRUPT:
     372             :         // case PIPE_ISOCHRONOUS:
     373           3 :         default:
     374           9 :                 periodic_unlink (ohci, ed);
     375           3 :                 break;
     376             :         }
     377             : }
     378          18 : 
     379             : 
     380             : /*-------------------------------------------------------------------------*/
     381             : 
     382             : /* get and maybe (re)init an endpoint. init _should_ be done only as part
     383             :  * of enumeration, usb_set_configuration() or usb_set_interface().
     384             :  */
     385             : static struct ed *ed_get (
     386             :         struct ohci_hcd         *ohci,
     387             :         struct usb_host_endpoint *ep,
     388           1 :         struct usb_device       *udev,
     389           1 :         unsigned int            pipe,
     390           1 :         int                     interval
     391           1 : ) {
     392           1 :         struct ed               *ed;
     393           1 :         unsigned long           flags;
     394           1 : 
     395           3 :         spin_lock_irqsave (&ohci->lock, flags);
     396             : 
     397           4 :         if (!(ed = ep->hcpriv)) {
     398             :                 struct td       *td;
     399             :                 int             is_out;
     400             :                 u32             info;
     401             : 
     402           3 :                 ed = ed_alloc (ohci, GFP_ATOMIC);
     403           2 :                 if (!ed) {
     404             :                         /* out of memory */
     405           1 :                         goto done;
     406             :                 }
     407             : 
     408             :                 /* dummy td; end of td list for ed */
     409           3 :                 td = td_alloc (ohci, GFP_ATOMIC);
     410           2 :                 if (!td) {
     411             :                         /* out of memory */
     412           2 :                         ed_free (ohci, ed);
     413           1 :                         ed = NULL;
     414           1 :                         goto done;
     415             :                 }
     416           1 :                 ed->dummy = td;
     417           3 :                 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
     418           1 :                 ed->hwHeadP = ed->hwTailP;        /* ED_C, ED_H zeroed */
     419           1 :                 ed->state = ED_IDLE;
     420             : 
     421           1 :                 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
     422             : 
     423             :                 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
     424             :                  * succeeds ... otherwise we wouldn't need "pipe".
     425             :                  */
     426           1 :                 info = usb_pipedevice (pipe);
     427           1 :                 ed->type = usb_pipetype(pipe);
     428             : 
     429           1 :                 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
     430           1 :                 info |= le16_to_cpu(ep->desc.wMaxPacketSize) << 16;
     431           3 :                 if (udev->speed == USB_SPEED_LOW)
     432           1 :                         info |= ED_LOWSPEED;
     433             :                 /* only control transfers store pids in tds */
     434           3 :                 if (ed->type != PIPE_CONTROL) {
     435           6 :                         info |= is_out ? ED_OUT : ED_IN;
     436           3 :                         if (ed->type != PIPE_BULK) {
     437             :                                 /* periodic transfers... */
     438           3 :                                 if (ed->type == PIPE_ISOCHRONOUS)
     439           1 :                                         info |= ED_ISO;
     440           2 :                                 else if (interval > 32)      /* iso can be bigger */
     441           1 :                                         interval = 32;
     442           1 :                                 ed->interval = interval;
     443           4 :                                 ed->load = usb_calc_bus_time (
     444             :                                         udev->speed, !is_out,
     445             :                                         ed->type == PIPE_ISOCHRONOUS,
     446             :                                         le16_to_cpu(ep->desc.wMaxPacketSize))
     447             :                                                 / 1000;
     448             :                         }
     449             :                 }
     450           2 :                 ed->hwINFO = cpu_to_hc32(ohci, info);
     451             : 
     452           1 :                 ep->hcpriv = ed;
     453             :         }
     454             : 
     455             : done:
     456           8 :         spin_unlock_irqrestore (&ohci->lock, flags);
     457           3 :         return ed;
     458             : }
     459             : 
     460             : /*-------------------------------------------------------------------------*/
     461             : 
     462             : /* request unlinking of an endpoint from an operational HC.
     463             :  * put the ep on the rm_list
     464             :  * real work is done at the next start frame (SF) hardware interrupt
     465             :  * caller guarantees HCD is running, so hardware access is safe,
     466             :  * and that ed->state is ED_OPER
     467             :  */
     468             : static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
     469             : {
     470          12 :         ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
     471          24 :         ed_deschedule (ohci, ed);
     472             : 
     473             :         /* rm_list is just singly linked, for simplicity */
     474           3 :         ed->ed_next = ohci->ed_rm_list;
     475           3 :         ed->ed_prev = NULL;
     476           3 :         ohci->ed_rm_list = ed;
     477             : 
     478             :         /* enable SOF interrupt */
     479           6 :         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
     480           6 :         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
     481             :         // flush those writes, and get latest HCCA contents
     482           6 :         (void) ohci_readl (ohci, &ohci->regs->control);
     483             : 
     484             :         /* SF interrupt might get delayed; record the frame counter value that
     485             :          * indicates when the HC isn't looking at it, so concurrent unlinks
     486             :          * behave.  frame_no wraps every 2^16 msec, and changes right before
     487             :          * SF is triggered.
     488             :          */
     489           9 :         ed->tick = ohci_frame_no(ohci) + 1;
     490           3 : 
     491             : }
     492             : 
     493             : /*-------------------------------------------------------------------------*
     494             :  * TD handling functions
     495             :  *-------------------------------------------------------------------------*/
     496             : 
     497             : /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
     498             : 
     499             : static void
     500             : td_fill (struct ohci_hcd *ohci, u32 info,
     501             :         dma_addr_t data, int len,
     502             :         struct urb *urb, int index)
     503          24 : {
     504          24 :         struct td               *td, *td_pt;
     505          72 :         struct urb_priv         *urb_priv = urb->hcpriv;
     506          48 :         int                     is_iso = info & TD_ISO;
     507          24 :         int                     hash;
     508          24 : 
     509          24 :         // ASSERT (index < urb_priv->length);
     510             : 
     511             :         /* aim for only one interrupt per urb.  mostly applies to control
     512             :          * and iso; other urbs rarely need more than one TD per urb.
     513             :          * this way, only final tds (or ones with an error) cause IRQs.
     514             :          * at least immediately; use DI=6 in case any control request is
     515             :          * tempted to die part way through.  (and to force the hc to flush
     516             :          * its donelist soonish, even on unlink paths.)
     517             :          *
     518             :          * NOTE: could delay interrupts even for the last TD, and get fewer
     519             :          * interrupts ... increasing per-urb latency by sharing interrupts.
     520             :          * Drivers that queue bulk urbs may request that behavior.
     521             :          */
     522         120 :         if (index != (urb_priv->length - 1)
     523             :                         || (urb->transfer_flags & URB_NO_INTERRUPT))
     524          24 :                 info |= TD_DI_SET (6);
     525             : 
     526             :         /* use this td as the next dummy */
     527          24 :         td_pt = urb_priv->td [index];
     528             : 
     529             :         /* fill the old dummy TD */
     530          72 :         td = urb_priv->td [index] = urb_priv->ed->dummy;
     531          24 :         urb_priv->ed->dummy = td_pt;
     532             : 
     533          24 :         td->ed = urb_priv->ed;
     534          24 :         td->next_dl_td = NULL;
     535          24 :         td->index = index;
     536          24 :         td->urb = urb;
     537          24 :         td->data_dma = data;
     538          48 :         if (!len)
     539          24 :                 data = 0;
     540             : 
     541          48 :         td->hwINFO = cpu_to_hc32 (ohci, info);
     542          48 :         if (is_iso) {
     543          48 :                 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
     544          96 :                 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
     545             :                                                 (data & 0x0FFF) | 0xE000);
     546          24 :                 td->ed->last_iso = info & 0xffff;
     547             :         } else {
     548          48 :                 td->hwCBP = cpu_to_hc32 (ohci, data);
     549             :         }
     550          96 :         if (data)
     551          96 :                 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
     552             :         else
     553          48 :                 td->hwBE = 0;
     554         216 :         td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
     555             : 
     556             :         /* append to queue */
     557          48 :         list_add_tail (&td->td_list, &td->ed->td_list);
     558             : 
     559             :         /* hash it for later reverse mapping */
     560          48 :         hash = TD_HASH_FUNC (td->td_dma);
     561          24 :         td->td_hash = ohci->td_hash [hash];
     562          24 :         ohci->td_hash [hash] = td;
     563             : 
     564             :         /* HC might read the TD (or cachelines) right away ... */
     565          24 :         wmb ();
     566          24 :         td->ed->hwTailP = td->hwNextTD;
     567          24 : }
     568             : 
     569             : /*-------------------------------------------------------------------------*/
     570             : 
     571             : /* Prepare all TDs of a transfer, and queue them onto the ED.
     572             :  * Caller guarantees HC is active.
     573             :  * Usually the ED is already on the schedule, so TDs might be
     574             :  * processed as soon as they're queued.
     575             :  */
     576             : static void td_submit_urb (
     577             :         struct ohci_hcd *ohci,
     578           3 :         struct urb      *urb
     579           3 : ) {
     580           9 :         struct urb_priv *urb_priv = urb->hcpriv;
     581           3 :         dma_addr_t      data;
     582           9 :         int             data_len = urb->transfer_buffer_length;
     583           6 :         int             cnt = 0;
     584           6 :         u32             info = 0;
     585           6 :         int             is_out = usb_pipeout (urb->pipe);
     586           6 :         int             periodic = 0;
     587           3 : 
     588           3 :         /* OHCI handles the bulk/interrupt data toggles itself.  We just
     589           3 :          * use the device toggle bits for resetting, and rely on the fact
     590           3 :          * that resetting toggle is meaningless if the endpoint is active.
     591           3 :          */
     592           9 :         if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
     593           6 :                 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
     594           3 :                         is_out, 1);
     595          12 :                 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
     596           3 :         }
     597           3 : 
     598           9 :         urb_priv->td_cnt = 0;
     599          15 :         list_add (&urb_priv->pending, &ohci->pending);
     600           3 : 
     601           6 :         if (data_len)
     602           3 :                 data = urb->transfer_dma;
     603             :         else
     604           3 :                 data = 0;
     605             : 
     606             :         /* NOTE:  TD_CC is set so we can tell which TDs the HC processed by
     607             :          * using TD_CC_GET, as well as by seeing them on the done list.
     608             :          * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
     609             :          */
     610           3 :         switch (urb_priv->ed->type) {
     611           3 : 
     612             :         /* Bulk and interrupt are identical except for where in the schedule
     613             :          * their EDs live.
     614             :          */
     615          12 :         case PIPE_INTERRUPT:
     616             :                 /* ... and periodic urbs have extra accounting */
     617          45 :                 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
     618           6 :                         && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
     619             :                 /* FALLTHROUGH */
     620          12 :         case PIPE_BULK:
     621          54 :                 info = is_out
     622             :                         ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
     623             :                         : TD_T_TOGGLE | TD_CC | TD_DP_IN;
     624             :                 /* TDs _could_ transfer up to 8K each */
     625          15 :                 while (data_len > 4096) {
     626           9 :                         td_fill (ohci, info, data, 4096, urb, cnt);
     627           6 :                         data += 4096;
     628           3 :                         data_len -= 4096;
     629           3 :                         cnt++;
     630             :                 }
     631           3 :                 /* maybe avoid ED halt on final TD short read */
     632           6 :                 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
     633           3 :                         info |= TD_R;
     634           6 :                 td_fill (ohci, info, data, data_len, urb, cnt);
     635           3 :                 cnt++;
     636          15 :                 if ((urb->transfer_flags & URB_ZERO_PACKET)
     637             :                                 && cnt < urb_priv->length) {
     638           6 :                         td_fill (ohci, info, 0, 0, urb, cnt);
     639           3 :                         cnt++;
     640             :                 }
     641             :                 /* maybe kickstart bulk list */
     642          18 :                 if (urb_priv->ed->type == PIPE_BULK) {
     643           6 :                         wmb ();
     644          12 :                         ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
     645             :                 }
     646           9 :                 break;
     647           3 : 
     648             :         /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
     649             :          * any DATA phase works normally, and the STATUS ack is special.
     650             :          */
     651          12 :         case PIPE_CONTROL:
     652           3 :                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
     653          12 :                 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
     654           6 :                 if (data_len > 0) {
     655           3 :                         info = TD_CC | TD_R | TD_T_DATA1;
     656          18 :                         info |= is_out ? TD_DP_OUT : TD_DP_IN;
     657             :                         /* NOTE:  mishandles transfers >8K, some >4K */
     658          12 :                         td_fill (ohci, info, data, data_len, urb, cnt++);
     659             :                 }
     660          48 :                 info = (is_out || data_len == 0)
     661             :                         ? TD_CC | TD_DP_IN | TD_T_DATA1
     662             :                         : TD_CC | TD_DP_OUT | TD_T_DATA1;
     663          24 :                 td_fill (ohci, info, data, 0, urb, cnt++);
     664             :                 /* maybe kickstart control list */
     665           3 :                 wmb ();
     666           6 :                 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
     667           3 :                 break;
     668           3 : 
     669             :         /* ISO has no retransmit, so no toggle; and it uses special TDs.
     670             :          * Each TD could handle multiple consecutive frames (interval 1);
     671             :          * we could often reduce the number of TDs here.
     672             :          */
     673          12 :         case PIPE_ISOCHRONOUS:
     674          15 :                 for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
     675           6 :                         int     frame = urb->start_frame;
     676           6 : 
     677             :                         // FIXME scheduling should handle frame counter
     678             :                         // roll-around ... exotic case (and OHCI has
     679             :                         // a 2^16 iso range, vs other HCs max of 2^10)
     680           3 :                         frame += cnt * urb->interval;
     681           3 :                         frame &= 0xffff;
     682           6 :                         td_fill (ohci, TD_CC | TD_ISO | frame,
     683             :                                 data + urb->iso_frame_desc [cnt].offset,
     684             :                                 urb->iso_frame_desc [cnt].length, urb, cnt);
     685             :                 }
     686          12 :                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
     687          12 :                         if (quirk_amdiso(ohci))
     688           9 :                                 quirk_amd_pll(0);
     689          18 :                         if (quirk_amdprefetch(ohci))
     690           9 :                                 sb800_prefetch(ohci, 1);
     691             :                 }
     692          57 :                 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
     693             :                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
     694           6 :                 break;
     695           3 :         }
     696             : 
     697           3 :         /* start periodic dma if needed */
     698          42 :         if (periodic) {
     699          21 :                 wmb ();
     700          21 :                 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
     701          42 :                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
     702             :         }
     703          24 : 
     704             :         // ASSERT (urb_priv->length == cnt);
     705             : }
     706             : 
     707             : /*-------------------------------------------------------------------------*
     708             :  * Done List handling functions
     709             :  *-------------------------------------------------------------------------*/
     710             : 
     711             : /* calculate transfer length/status and update the urb */
     712             : static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td)
     713             : {
     714          32 :         u32     tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
     715          16 :         int     cc = 0;
     716          16 :         int     status = -EINPROGRESS;
     717           8 : 
     718          24 :         list_del (&td->td_list);
     719           8 : 
     720           8 :         /* ISO ... drivers see per-TD length/status */
     721          24 :         if (tdINFO & TD_ISO) {
     722          32 :                 u16     tdPSW = ohci_hwPSW(ohci, td, 0);
     723          16 :                 int     dlen = 0;
     724           8 : 
     725             :                 /* NOTE:  assumes FC in tdINFO == 0, and that
     726             :                  * only the first of 0..MAXPSW psws is used.
     727             :                  */
     728             : 
     729           8 :                 cc = (tdPSW >> 12) & 0xF;
     730          16 :                 if (tdINFO & TD_CC) /* hc didn't touch? */
     731           8 :                         return status;
     732             : 
     733          16 :                 if (usb_pipeout (urb->pipe))
     734          16 :                         dlen = urb->iso_frame_desc [td->index].length;
     735             :                 else {
     736             :                         /* short reads are always OK for ISO */
     737          16 :                         if (cc == TD_DATAUNDERRUN)
     738           8 :                                 cc = TD_CC_NOERROR;
     739           8 :                         dlen = tdPSW & 0x3ff;
     740             :                 }
     741           8 :                 urb->actual_length += dlen;
     742          16 :                 urb->iso_frame_desc [td->index].actual_length = dlen;
     743          16 :                 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
     744             : 
     745             :                 if (cc != TD_CC_NOERROR)
     746             :                         ohci_vdbg (ohci,
     747             :                                 "urb %p iso td %p (%d) len %d cc %d\n",
     748             :                                 urb, td, 1 + td->index, dlen, cc);
     749             : 
     750             :         /* BULK, INT, CONTROL ... drivers see aggregate length/status,
     751             :          * except that "setup" bytes aren't counted and "short" transfers
     752             :          * might not be reported as errors.
     753             :          */
     754             :         } else {
     755           8 :                 int     type = usb_pipetype (urb->pipe);
     756          24 :                 u32     tdBE = hc32_to_cpup (ohci, &td->hwBE);
     757             : 
     758           8 :                 cc = TD_CC_GET (tdINFO);
     759             : 
     760             :                 /* update packet status if needed (short is normally ok) */
     761          32 :                 if (cc == TD_DATAUNDERRUN
     762             :                                 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
     763           8 :                         cc = TD_CC_NOERROR;
     764          32 :                 if (cc != TD_CC_NOERROR && cc < 0x0E)
     765           8 :                         status = cc_to_error[cc];
     766             : 
     767             :                 /* count all non-empty packets except control SETUP packet */
     768          56 :                 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
     769          16 :                         if (td->hwCBP == 0)
     770          16 :                                 urb->actual_length += tdBE - td->data_dma + 1;
     771             :                         else
     772          32 :                                 urb->actual_length +=
     773             :                                           hc32_to_cpup (ohci, &td->hwCBP)
     774             :                                         - td->data_dma;
     775             :                 }
     776             : 
     777             :                 if (cc != TD_CC_NOERROR && cc < 0x0E)
     778             :                         ohci_vdbg (ohci,
     779             :                                 "urb %p td %p (%d) cc %d, len=%d/%d\n",
     780             :                                 urb, td, 1 + td->index, cc,
     781             :                                 urb->actual_length,
     782             :                                 urb->transfer_buffer_length);
     783             :         }
     784          24 :         return status;
     785             : }
     786             : 
     787             : /*-------------------------------------------------------------------------*/
     788             : 
     789             : static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc)
     790             : {
     791           2 :         struct urb              *urb = td->urb;
     792           3 :         urb_priv_t              *urb_priv = urb->hcpriv;
     793           2 :         struct ed               *ed = td->ed;
     794           2 :         struct list_head        *tmp = td->td_list.next;
     795           4 :         __hc32                  toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
     796           1 : 
     797           1 :         /* clear ed halt; this is the td that caused it, but keep it inactive
     798           1 :          * until its urb->complete() has a chance to clean up.
     799           1 :          */
     800           4 :         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
     801           1 :         wmb ();
     802           3 :         ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
     803             : 
     804             :         /* Get rid of all later tds from this urb.  We don't have
     805             :          * to be careful: no errors and nothing was transferred.
     806             :          * Also patch the ed so it looks as if those tds completed normally.
     807             :          */
     808           3 :         while (tmp != &ed->td_list) {
     809           1 :                 struct td       *next;
     810           1 : 
     811           2 :                 next = list_entry (tmp, struct td, td_list);
     812           1 :                 tmp = next->td_list.next;
     813             : 
     814           4 :                 if (next->urb != urb)
     815           1 :                         break;
     816             : 
     817             :                 /* NOTE: if multi-td control DATA segments get supported,
     818             :                  * this urb had one of them, this td wasn't the last td
     819             :                  * in that segment (TD_R clear), this ed halted because
     820             :                  * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
     821             :                  * then we need to leave the control STATUS packet queued
     822             :                  * and clear ED_SKIP.
     823             :                  */
     824             : 
     825           2 :                 list_del(&next->td_list);
     826           2 :                 urb_priv->td_cnt++;
     827           1 :                 ed->hwHeadP = next->hwNextTD | toggle;
     828             :         }
     829           1 : 
     830             :         /* help for troubleshooting:  report anything that
     831             :          * looks odd ... that doesn't include protocol stalls
     832             :          * (or maybe some other things)
     833             :          */
     834             :         switch (cc) {
     835           3 :         case TD_DATAUNDERRUN:
     836           2 :                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
     837           1 :                         break;
     838             :                 /* fallthrough */
     839           3 :         case TD_CC_STALL:
     840           2 :                 if (usb_pipecontrol (urb->pipe))
     841           2 :                         break;
     842             :                 /* fallthrough */
     843           1 :         default:
     844           1 :                 ohci_dbg (ohci,
     845           1 :                         "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
     846           1 :                         urb, urb->dev->devpath,
     847             :                         usb_pipeendpoint (urb->pipe),
     848           1 :                         usb_pipein (urb->pipe) ? "in" : "out",
     849             :                         hc32_to_cpu (ohci, td->hwINFO),
     850             :                         cc, cc_to_error [cc]);
     851             :         }
     852             : }
     853           1 : 
     854             : /* replies to the request have to be on a FIFO basis so
     855             :  * we unreverse the hc-reversed done-list
     856             :  */
     857             : static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
     858             : {
     859           1 :         u32             td_dma;
     860           2 :         struct td       *td_rev = NULL;
     861           2 :         struct td       *td = NULL;
     862           1 : 
     863           3 :         td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
     864           2 :         ohci->hcca->done_head = 0;
     865           2 :         wmb();
     866           1 : 
     867           1 :         /* get TD from hc's singly linked list, and
     868           1 :          * prepend to ours.  ed->td_list changes later.
     869           1 :          */
     870           3 :         while (td_dma) {
     871           1 :                 int             cc;
     872           1 : 
     873           2 :                 td = dma_to_td (ohci, td_dma);
     874           2 :                 if (!td) {
     875           8 :                         ohci_err (ohci, "bad entry %8x\n", td_dma);
     876           2 :                         break;
     877             :                 }
     878             : 
     879           3 :                 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
     880           3 :                 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
     881             : 
     882             :                 /* Non-iso endpoints can halt on error; un-halt,
     883             :                  * and dequeue any other TDs from this urb.
     884             :                  * No other TD could have caused the halt.
     885             :                  */
     886           6 :                 if (cc != TD_CC_NOERROR
     887             :                                 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
     888           2 :                         ed_halted(ohci, td, cc);
     889             : 
     890           3 :                 td->next_dl_td = td_rev;
     891           3 :                 td_rev = td;
     892           6 :                 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
     893             :         }
     894           3 :         return td_rev;
     895             : }
     896             : 
     897             : /*-------------------------------------------------------------------------*/
     898             : 
     899             : /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
     900             : static void
     901             : finish_unlinks (struct ohci_hcd *ohci, u16 tick)
     902             : {
     903           2 :         struct ed       *ed, **last;
     904           2 : 
     905           2 : rescan_all:
     906          22 :         for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
     907          14 :                 struct list_head        *entry, *tmp;
     908           4 :                 int                     completed, modified;
     909           2 :                 __hc32                  *prev;
     910           2 : 
     911           2 :                 /* only take off EDs that the HC isn't using, accounting for
     912           2 :                  * frame counter wraps and EDs with partially retired TDs
     913           2 :                  */
     914          16 :                 if (likely (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))) {
     915           8 :                         if (tick_before (tick, ed->tick)) {
     916           4 : skip_ed:
     917           6 :                                 last = &ed->ed_next;
     918           6 :                                 continue;
     919           2 :                         }
     920           2 : 
     921          10 :                         if (!list_empty (&ed->td_list)) {
     922           2 :                                 struct td       *td;
     923           2 :                                 u32             head;
     924           2 : 
     925           6 :                                 td = list_entry (ed->td_list.next, struct td,
     926           2 :                                                         td_list);
     927           8 :                                 head = hc32_to_cpu (ohci, ed->hwHeadP) &
     928           2 :                                                                 TD_MASK;
     929           2 : 
     930           2 :                                 /* INTR_WDH may need to clean up first */
     931           6 :                                 if (td->td_dma != head) {
     932           8 :                                         if (ed == ohci->ed_to_check)
     933           4 :                                                 ohci->ed_to_check = NULL;
     934           2 :                                         else
     935           4 :                                                 goto skip_ed;
     936           2 :                                 }
     937           2 :                         }
     938           2 :                 }
     939           2 : 
     940           2 :                 /* reentrancy:  if we drop the schedule lock, someone might
     941           2 :                  * have modified this list.  normally it's just prepending
     942           2 :                  * entries (which we'd ignore), but paranoia won't hurt.
     943           2 :                  */
     944           8 :                 *last = ed->ed_next;
     945           8 :                 ed->ed_next = NULL;
     946           8 :                 modified = 0;
     947           8 : 
     948             :                 /* unlink urbs as requested, but rescan the list after
     949             :                  * we call a completion since it might have unlinked
     950           2 :                  * another (earlier) urb
     951             :                  *
     952             :                  * When we get here, the HC doesn't see this ed.  But it
     953             :                  * must not be rescheduled until all completed URBs have
     954             :                  * been given back to the driver.
     955             :                  */
     956             : rescan_this:
     957           2 :                 completed = 0;
     958           2 :                 prev = &ed->hwHeadP;
     959          22 :                 list_for_each_safe (entry, tmp, &ed->td_list) {
     960           8 :                         struct td       *td;
     961           2 :                         struct urb      *urb;
     962             :                         urb_priv_t      *urb_priv;
     963             :                         __hc32          savebits;
     964             :                         u32             tdINFO;
     965             : 
     966           4 :                         td = list_entry (entry, struct td, td_list);
     967           2 :                         urb = td->urb;
     968           4 :                         urb_priv = td->urb->hcpriv;
     969             : 
     970           4 :                         if (!urb->unlinked) {
     971           2 :                                 prev = &td->hwNextTD;
     972           2 :                                 continue;
     973             :                         }
     974             : 
     975             :                         /* patch pointer hc uses */
     976           6 :                         savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
     977           2 :                         *prev = td->hwNextTD | savebits;
     978             : 
     979             :                         /* If this was unlinked, the TD may not have been
     980             :                          * retired ... so manually save the data toggle.
     981             :                          * The controller ignores the value we save for
     982             :                          * control and ISO endpoints.
     983             :                          */
     984           4 :                         tdINFO = hc32_to_cpup(ohci, &td->hwINFO);
     985           4 :                         if ((tdINFO & TD_T) == TD_T_DATA0)
     986           6 :                                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C);
     987           4 :                         else if ((tdINFO & TD_T) == TD_T_DATA1)
     988           6 :                                 ed->hwHeadP |= cpu_to_hc32(ohci, ED_C);
     989             : 
     990             :                         /* HC may have partly processed this TD */
     991          24 :                         td_done (ohci, urb, td);
     992           4 :                         urb_priv->td_cnt++;
     993             : 
     994             :                         /* if URB is done, clean up */
     995           8 :                         if (urb_priv->td_cnt == urb_priv->length) {
     996           4 :                                 modified = completed = 1;
     997           8 :                                 finish_urb(ohci, urb, 0);
     998             :                         }
     999             :                 }
    1000          12 :                 if (completed && !list_empty (&ed->td_list))
    1001           2 :                         goto rescan_this;
    1002           4 : 
    1003             :                 /* ED's now officially unlinked, hc doesn't see */
    1004           4 :                 ed->state = ED_IDLE;
    1005          18 :                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
    1006           2 :                         ohci->eds_scheduled--;
    1007           6 :                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
    1008           2 :                 ed->hwNextED = 0;
    1009           2 :                 wmb ();
    1010           6 :                 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
    1011             : 
    1012             :                 /* but if there's work queued, reschedule */
    1013           8 :                 if (!list_empty (&ed->td_list)) {
    1014           8 :                         if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))
    1015          18 :                                 ed_schedule (ohci, ed);
    1016             :                 }
    1017             : 
    1018          12 :                 if (modified)
    1019           6 :                         goto rescan_all;
    1020             :         }
    1021             : 
    1022             :         /* maybe reenable control and bulk lists */
    1023          28 :         if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state)
    1024             :                         && ohci_to_hcd(ohci)->state != HC_STATE_QUIESCING
    1025             :                         && !ohci->ed_rm_list) {
    1026           4 :                 u32     command = 0, control = 0;
    1027             : 
    1028           6 :                 if (ohci->ed_controltail) {
    1029           2 :                         command |= OHCI_CLF;
    1030           8 :                         if (quirk_zfmicro(ohci))
    1031           4 :                                 mdelay(1);
    1032           4 :                         if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
    1033           2 :                                 control |= OHCI_CTRL_CLE;
    1034           4 :                                 ohci_writel (ohci, 0,
    1035             :                                         &ohci->regs->ed_controlcurrent);
    1036             :                         }
    1037             :                 }
    1038          18 :                 if (ohci->ed_bulktail) {
    1039           6 :                         command |= OHCI_BLF;
    1040          16 :                         if (quirk_zfmicro(ohci))
    1041           4 :                                 mdelay(1);
    1042           4 :                         if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
    1043           2 :                                 control |= OHCI_CTRL_BLE;
    1044           4 :                                 ohci_writel (ohci, 0,
    1045             :                                         &ohci->regs->ed_bulkcurrent);
    1046             :                         }
    1047             :                 }
    1048             : 
    1049             :                 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
    1050          20 :                 if (control) {
    1051          10 :                         ohci->hc_control |= control;
    1052          24 :                         if (quirk_zfmicro(ohci))
    1053           4 :                                 mdelay(1);
    1054           4 :                         ohci_writel (ohci, ohci->hc_control,
    1055             :                                         &ohci->regs->control);
    1056             :                 }
    1057          24 :                 if (command) {
    1058          28 :                         if (quirk_zfmicro(ohci))
    1059           4 :                                 mdelay(1);
    1060           4 :                         ohci_writel (ohci, command, &ohci->regs->cmdstatus);
    1061             :                 }
    1062             :         }
    1063          16 : }
    1064             : 
    1065             : 
    1066             : 
    1067             : /*-------------------------------------------------------------------------*/
    1068             : 
    1069             : /*
    1070             :  * Used to take back a TD from the host controller. This would normally be
    1071             :  * called from within dl_done_list, however it may be called directly if the
    1072             :  * HC no longer sees the TD and it has not appeared on the donelist (after
    1073             :  * two frames).  This bug has been observed on ZF Micro systems.
    1074             :  */
    1075             : static void takeback_td(struct ohci_hcd *ohci, struct td *td)
    1076             : {
    1077           4 :         struct urb      *urb = td->urb;
    1078           6 :         urb_priv_t      *urb_priv = urb->hcpriv;
    1079           4 :         struct ed       *ed = td->ed;
    1080           2 :         int             status;
    1081           2 : 
    1082           2 :         /* update URB's length and status from TD */
    1083          10 :         status = td_done(ohci, urb, td);
    1084           6 :         urb_priv->td_cnt++;
    1085           2 : 
    1086           2 :         /* If all this urb's TDs are done, call complete() */
    1087           8 :         if (urb_priv->td_cnt == urb_priv->length)
    1088           8 :                 finish_urb(ohci, urb, status);
    1089             : 
    1090             :         /* clean schedule:  unlink EDs that are no longer busy */
    1091          12 :         if (list_empty(&ed->td_list)) {
    1092           6 :                 if (ed->state == ED_OPER)
    1093           4 :                         start_ed_unlink(ohci, ed);
    1094             : 
    1095             :         /* ... reenabling halted EDs only after fault cleanup */
    1096          12 :         } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
    1097             :                         == cpu_to_hc32(ohci, ED_SKIP)) {
    1098           4 :                 td = list_entry(ed->td_list.next, struct td, td_list);
    1099           8 :                 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
    1100           6 :                         ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
    1101             :                         /* ... hc may need waking-up */
    1102           2 :                         switch (ed->type) {
    1103          10 :                         case PIPE_CONTROL:
    1104           4 :                                 ohci_writel(ohci, OHCI_CLF,
    1105             :                                                 &ohci->regs->cmdstatus);
    1106           2 :                                 break;
    1107          10 :                         case PIPE_BULK:
    1108           4 :                                 ohci_writel(ohci, OHCI_BLF,
    1109             :                                                 &ohci->regs->cmdstatus);
    1110           2 :                                 break;
    1111           2 :                         }
    1112             :                 }
    1113           2 :         }
    1114             : }
    1115          14 : 
    1116             : /*
    1117             :  * Process normal completions (error or success) and clean the schedules.
    1118             :  *
    1119             :  * This is the main path for handing urbs back to drivers.  The only other
    1120             :  * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
    1121             :  * instead of scanning the (re-reversed) donelist as this does.  There's
    1122             :  * an abnormal path too, handling a quirk in some Compaq silicon:  URBs
    1123             :  * with TDs that appear to be orphaned are directly reclaimed.
    1124             :  */
    1125             : static void
    1126             : dl_done_list (struct ohci_hcd *ohci)
    1127             : {
    1128           5 :         struct td       *td = dl_reverse_done_list (ohci);
    1129           1 : 
    1130           4 :         while (td) {
    1131           2 :                 struct td       *td_next = td->next_dl_td;
    1132           9 :                 takeback_td(ohci, td);
    1133           1 :                 td = td_next;
    1134             :         }
    1135           1 : }

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