Line data Source code
1 : /*
2 : * ahci.c - AHCI SATA support
3 : *
4 : * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 : * Please ALWAYS copy linux-ide@vger.kernel.org
6 : * on emails.
7 : *
8 : * Copyright 2004-2005 Red Hat, Inc.
9 : *
10 : *
11 : * This program is free software; you can redistribute it and/or modify
12 : * it under the terms of the GNU General Public License as published by
13 : * the Free Software Foundation; either version 2, or (at your option)
14 : * any later version.
15 : *
16 : * This program is distributed in the hope that it will be useful,
17 : * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 : * GNU General Public License for more details.
20 : *
21 : * You should have received a copy of the GNU General Public License
22 : * along with this program; see the file COPYING. If not, write to
23 : * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 : *
25 : *
26 : * libata documentation is available via 'make {ps|pdf}docs',
27 : * as Documentation/DocBook/libata.*
28 : *
29 : * AHCI hardware documentation:
30 : * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 : * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 : *
33 : */
34 :
35 : #include <linux/kernel.h>
36 : #include <linux/module.h>
37 : #include <linux/pci.h>
38 : #include <linux/init.h>
39 : #include <linux/blkdev.h>
40 : #include <linux/delay.h>
41 : #include <linux/interrupt.h>
42 : #include <linux/dma-mapping.h>
43 : #include <linux/device.h>
44 : #include <linux/dmi.h>
45 : #include <scsi/scsi_host.h>
46 : #include <scsi/scsi_cmnd.h>
47 : #include <linux/libata.h>
48 :
49 : #define DRV_NAME "ahci"
50 : #define DRV_VERSION "3.0"
51 :
52 : /* Enclosure Management Control */
53 : #define EM_CTRL_MSG_TYPE 0x000f0000
54 :
55 : /* Enclosure Management LED Message Type */
56 : #define EM_MSG_LED_HBA_PORT 0x0000000f
57 : #define EM_MSG_LED_PMP_SLOT 0x0000ff00
58 : #define EM_MSG_LED_VALUE 0xffff0000
59 : #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
60 : #define EM_MSG_LED_VALUE_OFF 0xfff80000
61 : #define EM_MSG_LED_VALUE_ON 0x00010000
62 :
63 1 : static int ahci_skip_host_reset;
64 1 : static int ahci_ignore_sss;
65 :
66 : module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
67 : MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
68 :
69 : module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
70 : MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
71 :
72 : static int ahci_enable_alpm(struct ata_port *ap,
73 : enum link_pm policy);
74 : static void ahci_disable_alpm(struct ata_port *ap);
75 : static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
76 : static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
77 : size_t size);
78 : static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
79 : ssize_t size);
80 :
81 : enum {
82 : AHCI_PCI_BAR = 5,
83 : AHCI_MAX_PORTS = 32,
84 : AHCI_MAX_SG = 168, /* hardware max is 64K */
85 : AHCI_DMA_BOUNDARY = 0xffffffff,
86 : AHCI_MAX_CMDS = 32,
87 : AHCI_CMD_SZ = 32,
88 : AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
89 : AHCI_RX_FIS_SZ = 256,
90 : AHCI_CMD_TBL_CDB = 0x40,
91 : AHCI_CMD_TBL_HDR_SZ = 0x80,
92 : AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
93 : AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
94 : AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
95 : AHCI_RX_FIS_SZ,
96 : AHCI_IRQ_ON_SG = (1 << 31),
97 : AHCI_CMD_ATAPI = (1 << 5),
98 : AHCI_CMD_WRITE = (1 << 6),
99 : AHCI_CMD_PREFETCH = (1 << 7),
100 : AHCI_CMD_RESET = (1 << 8),
101 : AHCI_CMD_CLR_BUSY = (1 << 10),
102 :
103 : RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
104 : RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
105 : RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
106 :
107 : board_ahci = 0,
108 : board_ahci_vt8251 = 1,
109 : board_ahci_ign_iferr = 2,
110 : board_ahci_sb600 = 3,
111 : board_ahci_mv = 4,
112 : board_ahci_sb700 = 5, /* for SB700 and SB800 */
113 : board_ahci_mcp65 = 6,
114 : board_ahci_nopmp = 7,
115 : board_ahci_yesncq = 8,
116 : board_ahci_nosntf = 9,
117 :
118 : /* global controller registers */
119 : HOST_CAP = 0x00, /* host capabilities */
120 : HOST_CTL = 0x04, /* global host control */
121 : HOST_IRQ_STAT = 0x08, /* interrupt status */
122 : HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
123 : HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
124 : HOST_EM_LOC = 0x1c, /* Enclosure Management location */
125 : HOST_EM_CTL = 0x20, /* Enclosure Management Control */
126 : HOST_CAP2 = 0x24, /* host capabilities, extended */
127 :
128 : /* HOST_CTL bits */
129 : HOST_RESET = (1 << 0), /* reset controller; self-clear */
130 : HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
131 : HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
132 :
133 : /* HOST_CAP bits */
134 : HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
135 : HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
136 : HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
137 : HOST_CAP_PART = (1 << 13), /* Partial state capable */
138 : HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
139 : HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
140 : HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
141 : HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
142 : HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
143 : HOST_CAP_CLO = (1 << 24), /* Command List Override support */
144 : HOST_CAP_LED = (1 << 25), /* Supports activity LED */
145 : HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
146 : HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
147 : HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
148 : HOST_CAP_SNTF = (1 << 29), /* SNotification register */
149 : HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
150 : HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
151 :
152 : /* HOST_CAP2 bits */
153 : HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
154 : HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
155 : HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
156 :
157 : /* registers for each SATA port */
158 : PORT_LST_ADDR = 0x00, /* command list DMA addr */
159 : PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
160 : PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
161 : PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
162 : PORT_IRQ_STAT = 0x10, /* interrupt status */
163 : PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
164 : PORT_CMD = 0x18, /* port command */
165 : PORT_TFDATA = 0x20, /* taskfile data */
166 : PORT_SIG = 0x24, /* device TF signature */
167 : PORT_CMD_ISSUE = 0x38, /* command issue */
168 : PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
169 : PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
170 : PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
171 : PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
172 : PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
173 :
174 : /* PORT_IRQ_{STAT,MASK} bits */
175 : PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
176 : PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
177 : PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
178 : PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
179 : PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
180 : PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
181 : PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
182 : PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
183 :
184 : PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
185 : PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
186 : PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
187 : PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
188 : PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
189 : PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
190 : PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
191 : PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
192 : PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
193 :
194 : PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
195 : PORT_IRQ_IF_ERR |
196 : PORT_IRQ_CONNECT |
197 : PORT_IRQ_PHYRDY |
198 : PORT_IRQ_UNK_FIS |
199 : PORT_IRQ_BAD_PMP,
200 : PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
201 : PORT_IRQ_TF_ERR |
202 : PORT_IRQ_HBUS_DATA_ERR,
203 : DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
204 : PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
205 : PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
206 :
207 : /* PORT_CMD bits */
208 : PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
209 : PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
210 : PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
211 : PORT_CMD_PMP = (1 << 17), /* PMP attached */
212 : PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
213 : PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
214 : PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
215 1 : PORT_CMD_CLO = (1 << 3), /* Command list override */
216 : PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
217 : PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
218 : PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
219 :
220 : PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
221 : PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
222 : PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
223 : PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
224 :
225 : /* hpriv->flags bits */
226 : AHCI_HFLAG_NO_NCQ = (1 << 0),
227 : AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
228 : AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
229 : AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
230 : AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
231 : AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
232 : AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
233 : AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
234 : AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
235 : AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
236 : AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
237 : AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
238 : link offline */
239 : AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
240 :
241 : /* ap->flags bits */
242 :
243 : AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
244 : ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
245 : ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
246 : ATA_FLAG_IPM,
247 :
248 : ICH_MAP = 0x90, /* ICH MAP register */
249 :
250 : /* em constants */
251 : EM_MAX_SLOTS = 8,
252 : EM_MAX_RETRY = 5,
253 :
254 : /* em_ctl bits */
255 : EM_CTL_RST = (1 << 9), /* Reset */
256 : EM_CTL_TM = (1 << 8), /* Transmit Message */
257 : EM_CTL_ALHD = (1 << 26), /* Activity LED */
258 : };
259 :
260 : struct ahci_cmd_hdr {
261 : __le32 opts;
262 : __le32 status;
263 : __le32 tbl_addr;
264 : __le32 tbl_addr_hi;
265 : __le32 reserved[4];
266 : };
267 1 :
268 : struct ahci_sg {
269 : __le32 addr;
270 : __le32 addr_hi;
271 : __le32 reserved;
272 : __le32 flags_size;
273 : };
274 1 :
275 : struct ahci_em_priv {
276 : enum sw_activity blink_policy;
277 : struct timer_list timer;
278 : unsigned long saved_activity;
279 : unsigned long activity;
280 : unsigned long led_state;
281 : };
282 1 :
283 : struct ahci_host_priv {
284 : unsigned int flags; /* AHCI_HFLAG_* */
285 : u32 cap; /* cap to use */
286 : u32 cap2; /* cap2 to use */
287 : u32 port_map; /* port map to use */
288 : u32 saved_cap; /* saved initial cap */
289 : u32 saved_cap2; /* saved initial cap2 */
290 : u32 saved_port_map; /* saved initial port_map */
291 : u32 em_loc; /* enclosure management location */
292 : };
293 1 :
294 : struct ahci_port_priv {
295 : struct ata_link *active_link;
296 : struct ahci_cmd_hdr *cmd_slot;
297 : dma_addr_t cmd_slot_dma;
298 : void *cmd_tbl;
299 : dma_addr_t cmd_tbl_dma;
300 : void *rx_fis;
301 : dma_addr_t rx_fis_dma;
302 : /* for NCQ spurious interrupt analysis */
303 : unsigned int ncq_saw_d2h:1;
304 : unsigned int ncq_saw_dmas:1;
305 : unsigned int ncq_saw_sdb:1;
306 : u32 intr_mask; /* interrupts to enable */
307 : /* enclosure management info per PM slot */
308 : struct ahci_em_priv em_priv[EM_MAX_SLOTS];
309 : };
310 :
311 : static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
312 : static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
313 : static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
314 : static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
315 : static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
316 : static int ahci_port_start(struct ata_port *ap);
317 : static void ahci_port_stop(struct ata_port *ap);
318 : static void ahci_qc_prep(struct ata_queued_cmd *qc);
319 : static void ahci_freeze(struct ata_port *ap);
320 : static void ahci_thaw(struct ata_port *ap);
321 : static void ahci_pmp_attach(struct ata_port *ap);
322 : static void ahci_pmp_detach(struct ata_port *ap);
323 : static int ahci_softreset(struct ata_link *link, unsigned int *class,
324 : unsigned long deadline);
325 : static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
326 : unsigned long deadline);
327 : static int ahci_hardreset(struct ata_link *link, unsigned int *class,
328 : unsigned long deadline);
329 : static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
330 : unsigned long deadline);
331 : static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
332 : unsigned long deadline);
333 : static void ahci_postreset(struct ata_link *link, unsigned int *class);
334 : static void ahci_error_handler(struct ata_port *ap);
335 : static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
336 : static int ahci_port_resume(struct ata_port *ap);
337 : static void ahci_dev_config(struct ata_device *dev);
338 : static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
339 : u32 opts);
340 : #ifdef CONFIG_PM
341 : static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
342 : static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
343 : static int ahci_pci_device_resume(struct pci_dev *pdev);
344 : #endif
345 : static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
346 : static ssize_t ahci_activity_store(struct ata_device *dev,
347 : enum sw_activity val);
348 : static void ahci_init_sw_activity(struct ata_link *link);
349 :
350 : static ssize_t ahci_show_host_caps(struct device *dev,
351 : struct device_attribute *attr, char *buf);
352 : static ssize_t ahci_show_host_cap2(struct device *dev,
353 : struct device_attribute *attr, char *buf);
354 : static ssize_t ahci_show_host_version(struct device *dev,
355 : struct device_attribute *attr, char *buf);
356 : static ssize_t ahci_show_port_cmd(struct device *dev,
357 : struct device_attribute *attr, char *buf);
358 :
359 1 : DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
360 1 : DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
361 1 : DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
362 1 : DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
363 :
364 1 : static struct device_attribute *ahci_shost_attrs[] = {
365 : &dev_attr_link_power_management_policy,
366 : &dev_attr_em_message_type,
367 : &dev_attr_em_message,
368 : &dev_attr_ahci_host_caps,
369 : &dev_attr_ahci_host_cap2,
370 : &dev_attr_ahci_host_version,
371 : &dev_attr_ahci_port_cmd,
372 : NULL
373 : };
374 :
375 1 : static struct device_attribute *ahci_sdev_attrs[] = {
376 : &dev_attr_sw_activity,
377 : &dev_attr_unload_heads,
378 : NULL
379 : };
380 :
381 1 : static struct scsi_host_template ahci_sht = {
382 : ATA_NCQ_SHT(DRV_NAME),
383 : .can_queue = AHCI_MAX_CMDS - 1,
384 : .sg_tablesize = AHCI_MAX_SG,
385 : .dma_boundary = AHCI_DMA_BOUNDARY,
386 : .shost_attrs = ahci_shost_attrs,
387 : .sdev_attrs = ahci_sdev_attrs,
388 : };
389 :
390 1 : static struct ata_port_operations ahci_ops = {
391 : .inherits = &sata_pmp_port_ops,
392 :
393 : .qc_defer = sata_pmp_qc_defer_cmd_switch,
394 : .qc_prep = ahci_qc_prep,
395 : .qc_issue = ahci_qc_issue,
396 : .qc_fill_rtf = ahci_qc_fill_rtf,
397 :
398 : .freeze = ahci_freeze,
399 : .thaw = ahci_thaw,
400 : .softreset = ahci_softreset,
401 : .hardreset = ahci_hardreset,
402 : .postreset = ahci_postreset,
403 : .pmp_softreset = ahci_softreset,
404 : .error_handler = ahci_error_handler,
405 : .post_internal_cmd = ahci_post_internal_cmd,
406 : .dev_config = ahci_dev_config,
407 :
408 : .scr_read = ahci_scr_read,
409 : .scr_write = ahci_scr_write,
410 : .pmp_attach = ahci_pmp_attach,
411 : .pmp_detach = ahci_pmp_detach,
412 :
413 : .enable_pm = ahci_enable_alpm,
414 : .disable_pm = ahci_disable_alpm,
415 : .em_show = ahci_led_show,
416 : .em_store = ahci_led_store,
417 : .sw_activity_show = ahci_activity_show,
418 : .sw_activity_store = ahci_activity_store,
419 : #ifdef CONFIG_PM
420 : .port_suspend = ahci_port_suspend,
421 : .port_resume = ahci_port_resume,
422 : #endif
423 : .port_start = ahci_port_start,
424 : .port_stop = ahci_port_stop,
425 : };
426 :
427 1 : static struct ata_port_operations ahci_vt8251_ops = {
428 : .inherits = &ahci_ops,
429 : .hardreset = ahci_vt8251_hardreset,
430 : };
431 :
432 1 : static struct ata_port_operations ahci_p5wdh_ops = {
433 : .inherits = &ahci_ops,
434 : .hardreset = ahci_p5wdh_hardreset,
435 : };
436 :
437 1 : static struct ata_port_operations ahci_sb600_ops = {
438 : .inherits = &ahci_ops,
439 : .softreset = ahci_sb600_softreset,
440 : .pmp_softreset = ahci_sb600_softreset,
441 : };
442 :
443 : #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
444 :
445 1 : static const struct ata_port_info ahci_port_info[] = {
446 : [board_ahci] =
447 : {
448 : .flags = AHCI_FLAG_COMMON,
449 : .pio_mask = ATA_PIO4,
450 : .udma_mask = ATA_UDMA6,
451 : .port_ops = &ahci_ops,
452 : },
453 : [board_ahci_vt8251] =
454 : {
455 : AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
456 : .flags = AHCI_FLAG_COMMON,
457 : .pio_mask = ATA_PIO4,
458 : .udma_mask = ATA_UDMA6,
459 : .port_ops = &ahci_vt8251_ops,
460 : },
461 : [board_ahci_ign_iferr] =
462 : {
463 : AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
464 : .flags = AHCI_FLAG_COMMON,
465 : .pio_mask = ATA_PIO4,
466 : .udma_mask = ATA_UDMA6,
467 : .port_ops = &ahci_ops,
468 : },
469 : [board_ahci_sb600] =
470 : {
471 : AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
472 : AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
473 : AHCI_HFLAG_32BIT_ONLY),
474 : .flags = AHCI_FLAG_COMMON,
475 : .pio_mask = ATA_PIO4,
476 : .udma_mask = ATA_UDMA6,
477 : .port_ops = &ahci_sb600_ops,
478 : },
479 : [board_ahci_mv] =
480 : {
481 : AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
482 : AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
483 : .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
484 : ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
485 : .pio_mask = ATA_PIO4,
486 : .udma_mask = ATA_UDMA6,
487 : .port_ops = &ahci_ops,
488 : },
489 : [board_ahci_sb700] = /* for SB700 and SB800 */
490 : {
491 : AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
492 : .flags = AHCI_FLAG_COMMON,
493 : .pio_mask = ATA_PIO4,
494 : .udma_mask = ATA_UDMA6,
495 : .port_ops = &ahci_sb600_ops,
496 : },
497 : [board_ahci_mcp65] =
498 : {
499 : AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
500 : .flags = AHCI_FLAG_COMMON,
501 : .pio_mask = ATA_PIO4,
502 : .udma_mask = ATA_UDMA6,
503 : .port_ops = &ahci_ops,
504 : },
505 : [board_ahci_nopmp] =
506 : {
507 : AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
508 : .flags = AHCI_FLAG_COMMON,
509 : .pio_mask = ATA_PIO4,
510 : .udma_mask = ATA_UDMA6,
511 : .port_ops = &ahci_ops,
512 : },
513 : [board_ahci_yesncq] =
514 : {
515 : AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
516 : .flags = AHCI_FLAG_COMMON,
517 : .pio_mask = ATA_PIO4,
518 : .udma_mask = ATA_UDMA6,
519 : .port_ops = &ahci_ops,
520 : },
521 : [board_ahci_nosntf] =
522 : {
523 : AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
524 : .flags = AHCI_FLAG_COMMON,
525 : .pio_mask = ATA_PIO4,
526 : .udma_mask = ATA_UDMA6,
527 : .port_ops = &ahci_ops,
528 : },
529 : };
530 :
531 1 : static const struct pci_device_id ahci_pci_tbl[] = {
532 : /* Intel */
533 : { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
534 : { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
535 : { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
536 : { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
537 : { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
538 : { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
539 : { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
540 : { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
541 : { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
542 : { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
543 : { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
544 : { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
545 : { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
546 : { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
547 : { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
548 : { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
549 : { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
550 : { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
551 : { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
552 : { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
553 : { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
554 : { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
555 : { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
556 : { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
557 : { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
558 : { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
559 : { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
560 : { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
561 : { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
562 : { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
563 : { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
564 : { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
565 : { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
566 : { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
567 : { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
568 : { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
569 : { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
570 : { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
571 : { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
572 : { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
573 : { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
574 : { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
575 : { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
576 : { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
577 : { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
578 : { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
579 : { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
580 : { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
581 : { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
582 : { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
583 : { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
584 :
585 : /* JMicron 360/1/3/5/6, match class to avoid IDE function */
586 : { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
587 : PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
588 :
589 : /* ATI */
590 : { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
591 : { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
592 : { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
593 : { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
594 : { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
595 : { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
596 : { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
597 :
598 : /* AMD */
599 : { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
600 : /* AMD is using RAID class only for ahci controllers */
601 : { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
602 : PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
603 :
604 : /* VIA */
605 : { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
606 : { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
607 :
608 : /* NVIDIA */
609 : { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
610 : { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
611 : { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
612 : { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
613 : { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
614 : { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
615 : { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
616 : { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
617 : { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */
618 : { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */
619 : { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */
620 : { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */
621 : { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */
622 : { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */
623 : { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */
624 : { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */
625 : { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */
626 : { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */
627 : { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */
628 : { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */
629 : { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq }, /* Linux ID */
630 : { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */
631 : { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */
632 : { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */
633 : { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */
634 : { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */
635 : { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */
636 : { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */
637 : { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */
638 : { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */
639 : { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */
640 : { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */
641 : { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */
642 : { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
643 : { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
644 : { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
645 : { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
646 : { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
647 : { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
648 : { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
649 : { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
650 : { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
651 : { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
652 : { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
653 : { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
654 : { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
655 : { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
656 : { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
657 : { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
658 : { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
659 : { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
660 : { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
661 : { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
662 : { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
663 : { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
664 : { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
665 : { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
666 : { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */
667 : { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */
668 : { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */
669 : { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */
670 : { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */
671 : { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */
672 : { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */
673 : { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */
674 : { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */
675 : { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */
676 : { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */
677 : { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */
678 :
679 : /* SiS */
680 : { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
681 : { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
682 : { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
683 :
684 : /* Marvell */
685 : { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
686 : { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
687 :
688 : /* Promise */
689 : { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
690 :
691 : /* Generic, PCI class code for AHCI */
692 : { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
693 : PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
694 :
695 : { } /* terminate list */
696 : };
697 :
698 :
699 1 : static struct pci_driver ahci_pci_driver = {
700 : .name = DRV_NAME,
701 : .id_table = ahci_pci_tbl,
702 : .probe = ahci_init_one,
703 : .remove = ata_pci_remove_one,
704 : #ifdef CONFIG_PM
705 : .suspend = ahci_pci_device_suspend,
706 : .resume = ahci_pci_device_resume,
707 : #endif
708 : };
709 :
710 1 : static int ahci_em_messages = 1;
711 : module_param(ahci_em_messages, int, 0444);
712 : /* add other LED protocol types when they become supported */
713 : MODULE_PARM_DESC(ahci_em_messages,
714 : "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
715 :
716 : #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
717 : static int marvell_enable;
718 : #else
719 1 : static int marvell_enable = 1;
720 : #endif
721 : module_param(marvell_enable, int, 0644);
722 : MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
723 :
724 :
725 : static inline int ahci_nr_ports(u32 cap)
726 : {
727 28 : return (cap & 0x1f) + 1;
728 : }
729 :
730 : static inline void __iomem *__ahci_port_base(struct ata_host *host,
731 : unsigned int port_no)
732 140 : {
733 140 : void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
734 :
735 140 : return mmio + 0x100 + (port_no * 0x80);
736 : }
737 :
738 : static inline void __iomem *ahci_port_base(struct ata_port *ap)
739 : {
740 556 : return __ahci_port_base(ap->host, ap->port_no);
741 : }
742 :
743 : static void ahci_enable_ahci(void __iomem *mmio)
744 : {
745 5 : int i;
746 5 : u32 tmp;
747 5 :
748 5 : /* turn on AHCI_EN */
749 10 : tmp = readl(mmio + HOST_CTL);
750 10 : if (tmp & HOST_AHCI_EN)
751 5 : return;
752 :
753 : /* Some controllers need AHCI_EN to be written multiple times.
754 : * Try a few times before giving up.
755 : */
756 25 : for (i = 0; i < 5; i++) {
757 10 : tmp |= HOST_AHCI_EN;
758 20 : writel(tmp, mmio + HOST_CTL);
759 10 : tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
760 10 : if (tmp & HOST_AHCI_EN)
761 5 : return;
762 5 : msleep(10);
763 : }
764 :
765 40 : WARN_ON(1);
766 : }
767 5 :
768 : static ssize_t ahci_show_host_caps(struct device *dev,
769 : struct device_attribute *attr, char *buf)
770 : {
771 3 : struct Scsi_Host *shost = class_to_shost(dev);
772 4 : struct ata_port *ap = ata_shost_to_port(shost);
773 3 : struct ahci_host_priv *hpriv = ap->host->private_data;
774 1 :
775 3 : return sprintf(buf, "%x\n", hpriv->cap);
776 1 : }
777 :
778 : static ssize_t ahci_show_host_cap2(struct device *dev,
779 : struct device_attribute *attr, char *buf)
780 : {
781 3 : struct Scsi_Host *shost = class_to_shost(dev);
782 4 : struct ata_port *ap = ata_shost_to_port(shost);
783 3 : struct ahci_host_priv *hpriv = ap->host->private_data;
784 1 :
785 3 : return sprintf(buf, "%x\n", hpriv->cap2);
786 1 : }
787 :
788 : static ssize_t ahci_show_host_version(struct device *dev,
789 : struct device_attribute *attr, char *buf)
790 : {
791 3 : struct Scsi_Host *shost = class_to_shost(dev);
792 4 : struct ata_port *ap = ata_shost_to_port(shost);
793 2 : void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
794 1 :
795 5 : return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
796 1 : }
797 1 :
798 : static ssize_t ahci_show_port_cmd(struct device *dev,
799 : struct device_attribute *attr, char *buf)
800 : {
801 3 : struct Scsi_Host *shost = class_to_shost(dev);
802 4 : struct ata_port *ap = ata_shost_to_port(shost);
803 4 : void __iomem *port_mmio = ahci_port_base(ap);
804 1 :
805 5 : return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
806 1 : }
807 1 :
808 1 : /**
809 : * ahci_save_initial_config - Save and fixup initial config values
810 : * @pdev: target PCI device
811 : * @hpriv: host private area to store config values
812 : *
813 : * Some registers containing configuration info might be setup by
814 : * BIOS and might be cleared on reset. This function saves the
815 : * initial values of those registers into @hpriv such that they
816 : * can be restored after controller reset.
817 : *
818 : * If inconsistent, config values are fixed up by this function.
819 : *
820 : * LOCKING:
821 : * None.
822 : */
823 : static void ahci_save_initial_config(struct pci_dev *pdev,
824 : struct ahci_host_priv *hpriv)
825 2 : {
826 6 : void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
827 2 : u32 cap, cap2, vers, port_map;
828 2 : int i;
829 2 : int mv;
830 2 :
831 2 : /* make sure AHCI mode is enabled before accessing CAP */
832 10 : ahci_enable_ahci(mmio);
833 2 :
834 2 : /* Values prefixed with saved_ are written back to host after
835 2 : * reset. Values without are used for driver operation.
836 2 : */
837 8 : hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
838 8 : hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
839 2 :
840 2 : /* CAP2 register is only defined for AHCI 1.2 and later */
841 6 : vers = readl(mmio + HOST_VERSION);
842 14 : if ((vers >> 16) > 1 ||
843 2 : ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
844 8 : hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
845 2 : else
846 6 : hpriv->saved_cap2 = cap2 = 0;
847 2 :
848 2 : /* some chips have errata preventing 64bit use */
849 18 : if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
850 14 : dev_printk(KERN_INFO, &pdev->dev,
851 2 : "controller can't do 64bit DMA, forcing 32bit\n");
852 4 : cap &= ~HOST_CAP_64;
853 2 : }
854 2 :
855 32 : if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
856 18 : dev_printk(KERN_INFO, &pdev->dev,
857 : "controller can't do NCQ, turning off CAP_NCQ\n");
858 2 : cap &= ~HOST_CAP_NCQ;
859 : }
860 :
861 32 : if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
862 20 : dev_printk(KERN_INFO, &pdev->dev,
863 : "controller can do NCQ, turning on CAP_NCQ\n");
864 2 : cap |= HOST_CAP_NCQ;
865 : }
866 :
867 40 : if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
868 24 : dev_printk(KERN_INFO, &pdev->dev,
869 : "controller can't do PMP, turning off CAP_PMP\n");
870 2 : cap &= ~HOST_CAP_PMP;
871 : }
872 :
873 48 : if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
874 28 : dev_printk(KERN_INFO, &pdev->dev,
875 : "controller can't do SNTF, turning off CAP_SNTF\n");
876 2 : cap &= ~HOST_CAP_SNTF;
877 : }
878 :
879 56 : if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
880 : port_map != 1) {
881 32 : dev_printk(KERN_INFO, &pdev->dev,
882 : "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
883 : port_map, 1);
884 2 : port_map = 1;
885 : }
886 :
887 : /*
888 : * Temporary Marvell 6145 hack: PATA port presence
889 : * is asserted through the standard AHCI port
890 : * presence register, as bit 4 (counting from 0)
891 : */
892 32 : if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
893 48 : if (pdev->device == 0x6121)
894 16 : mv = 0x3;
895 : else
896 16 : mv = 0xf;
897 36 : dev_printk(KERN_ERR, &pdev->dev,
898 : "MV_AHCI HACK: port_map %x -> %x\n",
899 : port_map,
900 : port_map & mv);
901 8 : dev_printk(KERN_ERR, &pdev->dev,
902 : "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
903 :
904 2 : port_map &= mv;
905 : }
906 :
907 : /* cross check port_map and cap.n_ports */
908 36 : if (port_map) {
909 18 : int map_ports = 0;
910 :
911 42 : for (i = 0; i < AHCI_MAX_PORTS; i++)
912 8 : if (port_map & (1 << i))
913 4 : map_ports++;
914 :
915 : /* If PI has more ports than n_ports, whine, clear
916 : * port_map and let it be generated from n_ports.
917 : */
918 8 : if (map_ports > ahci_nr_ports(cap)) {
919 12 : dev_printk(KERN_WARNING, &pdev->dev,
920 : "implemented port map (0x%x) contains more "
921 : "ports than nr_ports (%u), using nr_ports\n",
922 : port_map, ahci_nr_ports(cap));
923 2 : port_map = 0;
924 : }
925 : }
926 :
927 : /* fabricate port_map from cap.nr_ports */
928 44 : if (!port_map) {
929 46 : port_map = (1 << ahci_nr_ports(cap)) - 1;
930 8 : dev_printk(KERN_WARNING, &pdev->dev,
931 : "forcing PORTS_IMPL to 0x%x\n", port_map);
932 :
933 : /* write the fixed up value to the PI register */
934 2 : hpriv->saved_port_map = port_map;
935 : }
936 :
937 : /* record values to use during operation */
938 24 : hpriv->cap = cap;
939 24 : hpriv->cap2 = cap2;
940 24 : hpriv->port_map = port_map;
941 24 : }
942 :
943 : /**
944 : * ahci_restore_initial_config - Restore initial config
945 : * @host: target ATA host
946 : *
947 : * Restore initial config stored by ahci_save_initial_config().
948 : *
949 : * LOCKING:
950 : * None.
951 : */
952 : static void ahci_restore_initial_config(struct ata_host *host)
953 : {
954 3 : struct ahci_host_priv *hpriv = host->private_data;
955 2 : void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
956 :
957 2 : writel(hpriv->saved_cap, mmio + HOST_CAP);
958 2 : if (hpriv->saved_cap2)
959 2 : writel(hpriv->saved_cap2, mmio + HOST_CAP2);
960 4 : writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
961 2 : (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
962 1 : }
963 :
964 : static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
965 : {
966 48 : static const int offset[] = {
967 8 : [SCR_STATUS] = PORT_SCR_STAT,
968 : [SCR_CONTROL] = PORT_SCR_CTL,
969 : [SCR_ERROR] = PORT_SCR_ERR,
970 : [SCR_ACTIVE] = PORT_SCR_ACT,
971 : [SCR_NOTIFICATION] = PORT_SCR_NTF,
972 : };
973 16 : struct ahci_host_priv *hpriv = ap->host->private_data;
974 :
975 48 : if (sc_reg < ARRAY_SIZE(offset) &&
976 : (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
977 8 : return offset[sc_reg];
978 8 : return 0;
979 : }
980 :
981 : static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
982 : {
983 8 : void __iomem *port_mmio = ahci_port_base(link->ap);
984 8 : int offset = ahci_scr_offset(link->ap, sc_reg);
985 2 :
986 6 : if (offset) {
987 4 : *val = readl(port_mmio + offset);
988 2 : return 0;
989 : }
990 2 : return -EINVAL;
991 : }
992 :
993 : static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
994 : {
995 24 : void __iomem *port_mmio = ahci_port_base(link->ap);
996 24 : int offset = ahci_scr_offset(link->ap, sc_reg);
997 6 :
998 18 : if (offset) {
999 12 : writel(val, port_mmio + offset);
1000 6 : return 0;
1001 : }
1002 6 : return -EINVAL;
1003 : }
1004 :
1005 : static void ahci_start_engine(struct ata_port *ap)
1006 : {
1007 204 : void __iomem *port_mmio = ahci_port_base(ap);
1008 51 : u32 tmp;
1009 51 :
1010 : /* start DMA */
1011 102 : tmp = readl(port_mmio + PORT_CMD);
1012 51 : tmp |= PORT_CMD_START;
1013 102 : writel(tmp, port_mmio + PORT_CMD);
1014 102 : readl(port_mmio + PORT_CMD); /* flush */
1015 51 : }
1016 :
1017 : static int ahci_stop_engine(struct ata_port *ap)
1018 : {
1019 88 : void __iomem *port_mmio = ahci_port_base(ap);
1020 22 : u32 tmp;
1021 22 :
1022 44 : tmp = readl(port_mmio + PORT_CMD);
1023 :
1024 : /* check if the HBA is idle */
1025 44 : if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
1026 22 : return 0;
1027 :
1028 : /* setting HBA to idle */
1029 22 : tmp &= ~PORT_CMD_START;
1030 44 : writel(tmp, port_mmio + PORT_CMD);
1031 :
1032 : /* wait for engine to stop. This could be as long as 500 msec */
1033 22 : tmp = ata_wait_register(port_mmio + PORT_CMD,
1034 : PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
1035 44 : if (tmp & PORT_CMD_LIST_ON)
1036 22 : return -EIO;
1037 :
1038 22 : return 0;
1039 : }
1040 :
1041 : static void ahci_start_fis_rx(struct ata_port *ap)
1042 : {
1043 8 : void __iomem *port_mmio = ahci_port_base(ap);
1044 6 : struct ahci_host_priv *hpriv = ap->host->private_data;
1045 6 : struct ahci_port_priv *pp = ap->private_data;
1046 2 : u32 tmp;
1047 2 :
1048 : /* set FIS registers */
1049 6 : if (hpriv->cap & HOST_CAP_64)
1050 4 : writel((pp->cmd_slot_dma >> 16) >> 16,
1051 : port_mmio + PORT_LST_ADDR_HI);
1052 12 : writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
1053 :
1054 6 : if (hpriv->cap & HOST_CAP_64)
1055 4 : writel((pp->rx_fis_dma >> 16) >> 16,
1056 : port_mmio + PORT_FIS_ADDR_HI);
1057 12 : writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
1058 :
1059 : /* enable FIS reception */
1060 4 : tmp = readl(port_mmio + PORT_CMD);
1061 2 : tmp |= PORT_CMD_FIS_RX;
1062 4 : writel(tmp, port_mmio + PORT_CMD);
1063 :
1064 : /* flush */
1065 4 : readl(port_mmio + PORT_CMD);
1066 2 : }
1067 :
1068 : static int ahci_stop_fis_rx(struct ata_port *ap)
1069 : {
1070 12 : void __iomem *port_mmio = ahci_port_base(ap);
1071 3 : u32 tmp;
1072 3 :
1073 : /* disable FIS reception */
1074 6 : tmp = readl(port_mmio + PORT_CMD);
1075 3 : tmp &= ~PORT_CMD_FIS_RX;
1076 6 : writel(tmp, port_mmio + PORT_CMD);
1077 :
1078 : /* wait for completion, spec says 500ms, give it 1000 */
1079 3 : tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
1080 : PORT_CMD_FIS_ON, 10, 1000);
1081 6 : if (tmp & PORT_CMD_FIS_ON)
1082 3 : return -EBUSY;
1083 :
1084 3 : return 0;
1085 : }
1086 :
1087 : static void ahci_power_up(struct ata_port *ap)
1088 : {
1089 6 : struct ahci_host_priv *hpriv = ap->host->private_data;
1090 8 : void __iomem *port_mmio = ahci_port_base(ap);
1091 2 : u32 cmd;
1092 2 :
1093 8 : cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1094 :
1095 : /* spin up device */
1096 4 : if (hpriv->cap & HOST_CAP_SSS) {
1097 2 : cmd |= PORT_CMD_SPIN_UP;
1098 4 : writel(cmd, port_mmio + PORT_CMD);
1099 : }
1100 :
1101 : /* wake up link */
1102 8 : writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
1103 2 : }
1104 :
1105 : static void ahci_disable_alpm(struct ata_port *ap)
1106 : {
1107 12 : struct ahci_host_priv *hpriv = ap->host->private_data;
1108 16 : void __iomem *port_mmio = ahci_port_base(ap);
1109 4 : u32 cmd;
1110 12 : struct ahci_port_priv *pp = ap->private_data;
1111 4 :
1112 : /* IPM bits should be disabled by libata-core */
1113 : /* get the existing command bits */
1114 8 : cmd = readl(port_mmio + PORT_CMD);
1115 :
1116 : /* disable ALPM and ASP */
1117 4 : cmd &= ~PORT_CMD_ASP;
1118 4 : cmd &= ~PORT_CMD_ALPE;
1119 :
1120 : /* force the interface back to active */
1121 4 : cmd |= PORT_CMD_ICC_ACTIVE;
1122 :
1123 : /* write out new cmd value */
1124 8 : writel(cmd, port_mmio + PORT_CMD);
1125 8 : cmd = readl(port_mmio + PORT_CMD);
1126 :
1127 : /* wait 10ms to be sure we've come out of any low power state */
1128 4 : msleep(10);
1129 :
1130 : /* clear out any PhyRdy stuff from interrupt status */
1131 8 : writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
1132 :
1133 : /* go ahead and clean out PhyRdy Change from Serror too */
1134 12 : ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1135 :
1136 : /*
1137 : * Clear flag to indicate that we should ignore all PhyRdy
1138 : * state changes
1139 : */
1140 4 : hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1141 :
1142 : /*
1143 : * Enable interrupts on Phy Ready.
1144 : */
1145 4 : pp->intr_mask |= PORT_IRQ_PHYRDY;
1146 8 : writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1147 4 :
1148 : /*
1149 : * don't change the link pm policy - we can be called
1150 : * just to turn of link pm temporarily
1151 : */
1152 : }
1153 :
1154 : static int ahci_enable_alpm(struct ata_port *ap,
1155 : enum link_pm policy)
1156 2 : {
1157 6 : struct ahci_host_priv *hpriv = ap->host->private_data;
1158 8 : void __iomem *port_mmio = ahci_port_base(ap);
1159 2 : u32 cmd;
1160 6 : struct ahci_port_priv *pp = ap->private_data;
1161 2 : u32 asp;
1162 :
1163 : /* Make sure the host is capable of link power management */
1164 4 : if (!(hpriv->cap & HOST_CAP_ALPM))
1165 2 : return -EINVAL;
1166 :
1167 : switch (policy) {
1168 6 : case MAX_PERFORMANCE:
1169 6 : case NOT_AVAILABLE:
1170 : /*
1171 : * if we came here with NOT_AVAILABLE,
1172 : * it just means this is the first time we
1173 : * have tried to enable - default to max performance,
1174 : * and let the user go to lower power modes on request.
1175 : */
1176 4 : ahci_disable_alpm(ap);
1177 2 : return 0;
1178 8 : case MIN_POWER:
1179 : /* configure HBA to enter SLUMBER */
1180 2 : asp = PORT_CMD_ASP;
1181 2 : break;
1182 8 : case MEDIUM_POWER:
1183 : /* configure HBA to enter PARTIAL */
1184 2 : asp = 0;
1185 2 : break;
1186 4 : default:
1187 4 : return -EINVAL;
1188 2 : }
1189 :
1190 : /*
1191 : * Disable interrupts on Phy Ready. This keeps us from
1192 : * getting woken up due to spurious phy ready interrupts
1193 : * TBD - Hot plug should be done via polling now, is
1194 : * that even supported?
1195 : */
1196 2 : pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1197 4 : writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1198 :
1199 : /*
1200 : * Set a flag to indicate that we should ignore all PhyRdy
1201 : * state changes since these can happen now whenever we
1202 : * change link state
1203 : */
1204 2 : hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1205 :
1206 : /* get the existing command bits */
1207 4 : cmd = readl(port_mmio + PORT_CMD);
1208 :
1209 : /*
1210 : * Set ASP based on Policy
1211 : */
1212 2 : cmd |= asp;
1213 :
1214 : /*
1215 : * Setting this bit will instruct the HBA to aggressively
1216 : * enter a lower power link state when it's appropriate and
1217 : * based on the value set above for ASP
1218 : */
1219 2 : cmd |= PORT_CMD_ALPE;
1220 :
1221 : /* write out new cmd value */
1222 4 : writel(cmd, port_mmio + PORT_CMD);
1223 4 : cmd = readl(port_mmio + PORT_CMD);
1224 :
1225 : /* IPM bits should be set by libata-core */
1226 2 : return 0;
1227 : }
1228 :
1229 : #ifdef CONFIG_PM
1230 : static void ahci_power_down(struct ata_port *ap)
1231 : {
1232 : struct ahci_host_priv *hpriv = ap->host->private_data;
1233 : void __iomem *port_mmio = ahci_port_base(ap);
1234 : u32 cmd, scontrol;
1235 :
1236 : if (!(hpriv->cap & HOST_CAP_SSS))
1237 : return;
1238 :
1239 : /* put device into listen mode, first set PxSCTL.DET to 0 */
1240 : scontrol = readl(port_mmio + PORT_SCR_CTL);
1241 : scontrol &= ~0xf;
1242 : writel(scontrol, port_mmio + PORT_SCR_CTL);
1243 :
1244 : /* then set PxCMD.SUD to 0 */
1245 : cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1246 : cmd &= ~PORT_CMD_SPIN_UP;
1247 : writel(cmd, port_mmio + PORT_CMD);
1248 : }
1249 : #endif
1250 :
1251 : static void ahci_start_port(struct ata_port *ap)
1252 : {
1253 6 : struct ahci_port_priv *pp = ap->private_data;
1254 2 : struct ata_link *link;
1255 2 : struct ahci_em_priv *emp;
1256 2 : ssize_t rc;
1257 2 : int i;
1258 :
1259 : /* enable FIS reception */
1260 4 : ahci_start_fis_rx(ap);
1261 :
1262 : /* enable DMA */
1263 4 : ahci_start_engine(ap);
1264 :
1265 : /* turn on LEDs */
1266 4 : if (ap->flags & ATA_FLAG_EM) {
1267 12 : ata_for_each_link(link, ap, EDGE) {
1268 6 : emp = &pp->em_priv[link->pmp];
1269 6 :
1270 : /* EM Transmit bit maybe busy during init */
1271 10 : for (i = 0; i < EM_MAX_RETRY; i++) {
1272 14 : rc = ahci_transmit_led_message(ap,
1273 2 : emp->led_state,
1274 : 4);
1275 4 : if (rc == -EBUSY)
1276 2 : msleep(1);
1277 2 : else
1278 2 : break;
1279 : }
1280 : }
1281 : }
1282 :
1283 8 : if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1284 14 : ata_for_each_link(link, ap, EDGE)
1285 6 : ahci_init_sw_activity(link);
1286 4 :
1287 : }
1288 :
1289 : static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1290 : {
1291 3 : int rc;
1292 6 :
1293 : /* disable DMA */
1294 9 : rc = ahci_stop_engine(ap);
1295 6 : if (rc) {
1296 3 : *emsg = "failed to stop engine";
1297 3 : return rc;
1298 : }
1299 :
1300 : /* disable FIS reception */
1301 6 : rc = ahci_stop_fis_rx(ap);
1302 6 : if (rc) {
1303 3 : *emsg = "failed stop FIS RX";
1304 3 : return rc;
1305 : }
1306 :
1307 3 : return 0;
1308 : }
1309 :
1310 : static int ahci_reset_controller(struct ata_host *host)
1311 : {
1312 4 : struct pci_dev *pdev = to_pci_dev(host->dev);
1313 3 : struct ahci_host_priv *hpriv = host->private_data;
1314 2 : void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1315 1 : u32 tmp;
1316 1 :
1317 1 : /* we must be in AHCI mode, before using anything
1318 1 : * AHCI-specific, such as HOST_RESET.
1319 1 : */
1320 5 : ahci_enable_ahci(mmio);
1321 1 :
1322 : /* global controller reset */
1323 2 : if (!ahci_skip_host_reset) {
1324 2 : tmp = readl(mmio + HOST_CTL);
1325 2 : if ((tmp & HOST_RESET) == 0) {
1326 2 : writel(tmp | HOST_RESET, mmio + HOST_CTL);
1327 2 : readl(mmio + HOST_CTL); /* flush */
1328 : }
1329 :
1330 : /*
1331 : * to perform host reset, OS should set HOST_RESET
1332 : * and poll until this bit is read to be "0".
1333 : * reset must complete within 1 second, or
1334 : * the hardware should be considered fried.
1335 : */
1336 2 : tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1337 : HOST_RESET, 10, 1000);
1338 :
1339 4 : if (tmp & HOST_RESET) {
1340 9 : dev_printk(KERN_ERR, host->dev,
1341 : "controller reset failed (0x%x)\n", tmp);
1342 1 : return -EIO;
1343 : }
1344 :
1345 : /* turn on AHCI mode */
1346 8 : ahci_enable_ahci(mmio);
1347 :
1348 : /* Some registers might be cleared on reset. Restore
1349 : * initial values.
1350 : */
1351 2 : ahci_restore_initial_config(host);
1352 : } else
1353 6 : dev_printk(KERN_INFO, host->dev,
1354 : "skipping global host reset\n");
1355 :
1356 6 : if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1357 : u16 tmp16;
1358 :
1359 : /* configure PCS */
1360 4 : pci_read_config_word(pdev, 0x92, &tmp16);
1361 2 : if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1362 2 : tmp16 |= hpriv->port_map;
1363 2 : pci_write_config_word(pdev, 0x92, tmp16);
1364 : }
1365 : }
1366 :
1367 4 : return 0;
1368 : }
1369 :
1370 : static void ahci_sw_activity(struct ata_link *link)
1371 : {
1372 4 : struct ata_port *ap = link->ap;
1373 6 : struct ahci_port_priv *pp = ap->private_data;
1374 6 : struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1375 2 :
1376 6 : if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1377 2 : return;
1378 :
1379 2 : emp->activity++;
1380 8 : if (!timer_pending(&emp->timer))
1381 6 : mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1382 4 : }
1383 :
1384 : static void ahci_sw_activity_blink(unsigned long arg)
1385 : {
1386 0 : struct ata_link *link = (struct ata_link *)arg;
1387 0 : struct ata_port *ap = link->ap;
1388 0 : struct ahci_port_priv *pp = ap->private_data;
1389 0 : struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1390 0 : unsigned long led_message = emp->led_state;
1391 0 : u32 activity_led_state;
1392 0 : unsigned long flags;
1393 0 :
1394 0 : led_message &= EM_MSG_LED_VALUE;
1395 0 : led_message |= ap->port_no | (link->pmp << 8);
1396 :
1397 : /* check to see if we've had activity. If so,
1398 : * toggle state of LED and reset timer. If not,
1399 : * turn LED to desired idle state.
1400 : */
1401 0 : spin_lock_irqsave(ap->lock, flags);
1402 0 : if (emp->saved_activity != emp->activity) {
1403 0 : emp->saved_activity = emp->activity;
1404 : /* get the current LED state */
1405 0 : activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1406 :
1407 0 : if (activity_led_state)
1408 0 : activity_led_state = 0;
1409 : else
1410 0 : activity_led_state = 1;
1411 :
1412 : /* clear old state */
1413 0 : led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1414 :
1415 : /* toggle state */
1416 0 : led_message |= (activity_led_state << 16);
1417 0 : mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1418 : } else {
1419 : /* switch to idle */
1420 0 : led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1421 0 : if (emp->blink_policy == BLINK_OFF)
1422 0 : led_message |= (1 << 16);
1423 : }
1424 0 : spin_unlock_irqrestore(ap->lock, flags);
1425 0 : ahci_transmit_led_message(ap, led_message, 4);
1426 0 : }
1427 :
1428 : static void ahci_init_sw_activity(struct ata_link *link)
1429 : {
1430 4 : struct ata_port *ap = link->ap;
1431 6 : struct ahci_port_priv *pp = ap->private_data;
1432 6 : struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1433 2 :
1434 : /* init activity stats, setup timer */
1435 6 : emp->saved_activity = emp->activity = 0;
1436 4 : setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1437 :
1438 : /* check our blink policy and set flag for link if it's enabled */
1439 6 : if (emp->blink_policy)
1440 2 : link->flags |= ATA_LFLAG_SW_ACTIVITY;
1441 2 : }
1442 :
1443 : static int ahci_reset_em(struct ata_host *host)
1444 : {
1445 2 : void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1446 1 : u32 em_ctl;
1447 :
1448 2 : em_ctl = readl(mmio + HOST_EM_CTL);
1449 2 : if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1450 1 : return -EINVAL;
1451 :
1452 2 : writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1453 1 : return 0;
1454 : }
1455 :
1456 : static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1457 : ssize_t size)
1458 8 : {
1459 24 : struct ahci_host_priv *hpriv = ap->host->private_data;
1460 24 : struct ahci_port_priv *pp = ap->private_data;
1461 16 : void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1462 8 : u32 em_ctl;
1463 24 : u32 message[] = {0, 0};
1464 8 : unsigned long flags;
1465 8 : int pmp;
1466 8 : struct ahci_em_priv *emp;
1467 :
1468 : /* get the slot number from the message */
1469 8 : pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1470 16 : if (pmp < EM_MAX_SLOTS)
1471 8 : emp = &pp->em_priv[pmp];
1472 : else
1473 8 : return -EINVAL;
1474 :
1475 24 : spin_lock_irqsave(ap->lock, flags);
1476 :
1477 : /*
1478 : * if we are still busy transmitting a previous message,
1479 : * do not allow
1480 : */
1481 16 : em_ctl = readl(mmio + HOST_EM_CTL);
1482 16 : if (em_ctl & EM_CTL_TM) {
1483 16 : spin_unlock_irqrestore(ap->lock, flags);
1484 8 : return -EBUSY;
1485 : }
1486 :
1487 : /*
1488 : * create message header - this is all zero except for
1489 : * the message size, which is 4 bytes.
1490 : */
1491 8 : message[0] |= (4 << 8);
1492 :
1493 : /* ignore 0:4 of byte zero, fill in port info yourself */
1494 8 : message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1495 :
1496 : /* write message to EM_LOC */
1497 24 : writel(message[0], mmio + hpriv->em_loc);
1498 24 : writel(message[1], mmio + hpriv->em_loc+4);
1499 :
1500 : /* save off new led state for port/slot */
1501 8 : emp->led_state = state;
1502 :
1503 : /*
1504 : * tell hardware to transmit the message
1505 : */
1506 16 : writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1507 :
1508 16 : spin_unlock_irqrestore(ap->lock, flags);
1509 8 : return size;
1510 : }
1511 :
1512 : static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1513 : {
1514 6 : struct ahci_port_priv *pp = ap->private_data;
1515 2 : struct ata_link *link;
1516 2 : struct ahci_em_priv *emp;
1517 4 : int rc = 0;
1518 2 :
1519 10 : ata_for_each_link(link, ap, EDGE) {
1520 6 : emp = &pp->em_priv[link->pmp];
1521 8 : rc += sprintf(buf, "%lx\n", emp->led_state);
1522 : }
1523 2 : return rc;
1524 : }
1525 :
1526 : static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1527 : size_t size)
1528 2 : {
1529 2 : int state;
1530 2 : int pmp;
1531 6 : struct ahci_port_priv *pp = ap->private_data;
1532 2 : struct ahci_em_priv *emp;
1533 2 :
1534 4 : state = simple_strtoul(buf, NULL, 0);
1535 :
1536 : /* get the slot number from the message */
1537 2 : pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1538 4 : if (pmp < EM_MAX_SLOTS)
1539 2 : emp = &pp->em_priv[pmp];
1540 : else
1541 2 : return -EINVAL;
1542 :
1543 : /* mask off the activity bits if we are in sw_activity
1544 : * mode, user should turn off sw_activity before setting
1545 : * activity led through em_message
1546 : */
1547 6 : if (emp->blink_policy)
1548 2 : state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1549 :
1550 10 : return ahci_transmit_led_message(ap, state, size);
1551 : }
1552 :
1553 : static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1554 : {
1555 4 : struct ata_link *link = dev->link;
1556 4 : struct ata_port *ap = link->ap;
1557 6 : struct ahci_port_priv *pp = ap->private_data;
1558 6 : struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1559 6 : u32 port_led_state = emp->led_state;
1560 :
1561 : /* save the desired Activity LED behavior */
1562 4 : if (val == OFF) {
1563 : /* clear LFLAG */
1564 2 : link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1565 :
1566 : /* set the LED to OFF */
1567 2 : port_led_state &= EM_MSG_LED_VALUE_OFF;
1568 2 : port_led_state |= (ap->port_no | (link->pmp << 8));
1569 8 : ahci_transmit_led_message(ap, port_led_state, 4);
1570 : } else {
1571 2 : link->flags |= ATA_LFLAG_SW_ACTIVITY;
1572 4 : if (val == BLINK_OFF) {
1573 : /* set LED to ON for idle */
1574 2 : port_led_state &= EM_MSG_LED_VALUE_OFF;
1575 2 : port_led_state |= (ap->port_no | (link->pmp << 8));
1576 2 : port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1577 8 : ahci_transmit_led_message(ap, port_led_state, 4);
1578 : }
1579 : }
1580 6 : emp->blink_policy = val;
1581 6 : return 0;
1582 : }
1583 :
1584 : static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1585 : {
1586 4 : struct ata_link *link = dev->link;
1587 4 : struct ata_port *ap = link->ap;
1588 6 : struct ahci_port_priv *pp = ap->private_data;
1589 6 : struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1590 2 :
1591 : /* display the saved value of activity behavior for this
1592 : * disk.
1593 : */
1594 6 : return sprintf(buf, "%d\n", emp->blink_policy);
1595 : }
1596 :
1597 : static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1598 : int port_no, void __iomem *mmio,
1599 : void __iomem *port_mmio)
1600 1 : {
1601 2 : const char *emsg = NULL;
1602 1 : int rc;
1603 1 : u32 tmp;
1604 1 :
1605 : /* make sure port is not active */
1606 3 : rc = ahci_deinit_port(ap, &emsg);
1607 2 : if (rc)
1608 4 : dev_printk(KERN_WARNING, &pdev->dev,
1609 : "%s (%d)\n", emsg, rc);
1610 :
1611 : /* clear SError */
1612 4 : tmp = readl(port_mmio + PORT_SCR_ERR);
1613 : VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1614 2 : writel(tmp, port_mmio + PORT_SCR_ERR);
1615 :
1616 : /* clear port IRQ */
1617 2 : tmp = readl(port_mmio + PORT_IRQ_STAT);
1618 : VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1619 2 : if (tmp)
1620 2 : writel(tmp, port_mmio + PORT_IRQ_STAT);
1621 :
1622 4 : writel(1 << port_no, mmio + HOST_IRQ_STAT);
1623 1 : }
1624 :
1625 : static void ahci_init_controller(struct ata_host *host)
1626 : {
1627 3 : struct ahci_host_priv *hpriv = host->private_data;
1628 4 : struct pci_dev *pdev = to_pci_dev(host->dev);
1629 2 : void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1630 1 : int i;
1631 1 : void __iomem *port_mmio;
1632 1 : u32 tmp;
1633 1 : int mv;
1634 1 :
1635 3 : if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1636 4 : if (pdev->device == 0x6121)
1637 1 : mv = 2;
1638 : else
1639 1 : mv = 4;
1640 2 : port_mmio = __ahci_port_base(host, mv);
1641 :
1642 2 : writel(0, port_mmio + PORT_IRQ_MASK);
1643 :
1644 : /* clear port IRQ */
1645 2 : tmp = readl(port_mmio + PORT_IRQ_STAT);
1646 : VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1647 2 : if (tmp)
1648 2 : writel(tmp, port_mmio + PORT_IRQ_STAT);
1649 : }
1650 :
1651 10 : for (i = 0; i < host->n_ports; i++) {
1652 4 : struct ata_port *ap = host->ports[i];
1653 1 :
1654 2 : port_mmio = ahci_port_base(ap);
1655 4 : if (ata_port_is_dummy(ap))
1656 1 : continue;
1657 :
1658 2 : ahci_port_init(pdev, ap, i, mmio, port_mmio);
1659 : }
1660 1 :
1661 2 : tmp = readl(mmio + HOST_CTL);
1662 : VPRINTK("HOST_CTL 0x%x\n", tmp);
1663 2 : writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1664 2 : tmp = readl(mmio + HOST_CTL);
1665 1 : VPRINTK("HOST_CTL 0x%x\n", tmp);
1666 : }
1667 :
1668 : static void ahci_dev_config(struct ata_device *dev)
1669 : {
1670 6 : struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1671 :
1672 4 : if (hpriv->flags & AHCI_HFLAG_SECT255) {
1673 2 : dev->max_sectors = 255;
1674 4 : ata_dev_printk(dev, KERN_INFO,
1675 : "SB600 AHCI: limiting to 255 sectors per cmd\n");
1676 2 : }
1677 : }
1678 :
1679 : static unsigned int ahci_dev_classify(struct ata_port *ap)
1680 : {
1681 16 : void __iomem *port_mmio = ahci_port_base(ap);
1682 4 : struct ata_taskfile tf;
1683 4 : u32 tmp;
1684 4 :
1685 12 : tmp = readl(port_mmio + PORT_SIG);
1686 4 : tf.lbah = (tmp >> 24) & 0xff;
1687 4 : tf.lbam = (tmp >> 16) & 0xff;
1688 4 : tf.lbal = (tmp >> 8) & 0xff;
1689 4 : tf.nsect = (tmp) & 0xff;
1690 :
1691 8 : return ata_dev_classify(&tf);
1692 : }
1693 :
1694 : static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1695 : u32 opts)
1696 12 : {
1697 : dma_addr_t cmd_tbl_dma;
1698 :
1699 12 : cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1700 :
1701 12 : pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1702 12 : pp->cmd_slot[tag].status = 0;
1703 12 : pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1704 12 : pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1705 12 : }
1706 :
1707 : static int ahci_kick_engine(struct ata_port *ap)
1708 : {
1709 60 : void __iomem *port_mmio = ahci_port_base(ap);
1710 45 : struct ahci_host_priv *hpriv = ap->host->private_data;
1711 60 : u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1712 15 : u32 tmp;
1713 15 : int busy, rc;
1714 15 :
1715 15 : /* stop engine */
1716 60 : rc = ahci_stop_engine(ap);
1717 45 : if (rc)
1718 30 : goto out_restart;
1719 :
1720 : /* need to do CLO?
1721 : * always do CLO if PMP is attached (AHCI-1.3 9.2)
1722 : */
1723 15 : busy = status & (ATA_BUSY | ATA_DRQ);
1724 150 : if (!busy && !sata_pmp_attached(ap)) {
1725 15 : rc = 0;
1726 15 : goto out_restart;
1727 : }
1728 :
1729 60 : if (!(hpriv->cap & HOST_CAP_CLO)) {
1730 30 : rc = -EOPNOTSUPP;
1731 30 : goto out_restart;
1732 : }
1733 :
1734 : /* perform CLO */
1735 60 : tmp = readl(port_mmio + PORT_CMD);
1736 15 : tmp |= PORT_CMD_CLO;
1737 30 : writel(tmp, port_mmio + PORT_CMD);
1738 :
1739 15 : rc = 0;
1740 15 : tmp = ata_wait_register(port_mmio + PORT_CMD,
1741 : PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1742 30 : if (tmp & PORT_CMD_CLO)
1743 15 : rc = -EIO;
1744 :
1745 : /* restart engine */
1746 : out_restart:
1747 105 : ahci_start_engine(ap);
1748 15 : return rc;
1749 : }
1750 :
1751 : static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1752 : struct ata_taskfile *tf, int is_cmd, u16 flags,
1753 : unsigned long timeout_msec)
1754 8 : {
1755 16 : const u32 cmd_fis_len = 5; /* five dwords */
1756 24 : struct ahci_port_priv *pp = ap->private_data;
1757 32 : void __iomem *port_mmio = ahci_port_base(ap);
1758 24 : u8 *fis = pp->cmd_tbl;
1759 8 : u32 tmp;
1760 :
1761 : /* prep the command */
1762 8 : ata_tf_to_fis(tf, pmp, is_cmd, fis);
1763 16 : ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1764 :
1765 : /* issue & wait */
1766 16 : writel(1, port_mmio + PORT_CMD_ISSUE);
1767 :
1768 16 : if (timeout_msec) {
1769 8 : tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1770 : 1, timeout_msec);
1771 16 : if (tmp & 0x1) {
1772 16 : ahci_kick_engine(ap);
1773 8 : return -EBUSY;
1774 : }
1775 : } else
1776 16 : readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1777 :
1778 16 : return 0;
1779 : }
1780 :
1781 : static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1782 : int pmp, unsigned long deadline,
1783 : int (*check_ready)(struct ata_link *link))
1784 4 : {
1785 8 : struct ata_port *ap = link->ap;
1786 12 : struct ahci_host_priv *hpriv = ap->host->private_data;
1787 8 : const char *reason = NULL;
1788 4 : unsigned long now, msecs;
1789 4 : struct ata_taskfile tf;
1790 4 : int rc;
1791 4 :
1792 4 : DPRINTK("ENTER\n");
1793 4 :
1794 4 : /* prepare for SRST (AHCI-1.1 10.4.1) */
1795 12 : rc = ahci_kick_engine(ap);
1796 16 : if (rc && rc != -EOPNOTSUPP)
1797 36 : ata_link_printk(link, KERN_WARNING,
1798 : "failed to reset engine (errno=%d)\n", rc);
1799 :
1800 16 : ata_tf_init(link->device, &tf);
1801 :
1802 : /* issue the first D2H Register FIS */
1803 4 : msecs = 0;
1804 4 : now = jiffies;
1805 8 : if (time_after(now, deadline))
1806 8 : msecs = jiffies_to_msecs(deadline - now);
1807 :
1808 4 : tf.ctl |= ATA_SRST;
1809 24 : if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1810 : AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1811 4 : rc = -EIO;
1812 4 : reason = "1st FIS failed";
1813 4 : goto fail;
1814 : }
1815 :
1816 : /* spec says at least 5us, but be generous and sleep for 1ms */
1817 4 : msleep(1);
1818 :
1819 : /* issue the second D2H Register FIS */
1820 4 : tf.ctl &= ~ATA_SRST;
1821 16 : ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1822 :
1823 : /* wait for link to become ready */
1824 4 : rc = ata_wait_after_reset(link, deadline, check_ready);
1825 16 : if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1826 : /*
1827 : * Workaround for cases where link online status can't
1828 : * be trusted. Treat device readiness timeout as link
1829 : * offline.
1830 : */
1831 36 : ata_link_printk(link, KERN_INFO,
1832 : "device not ready, treating as offline\n");
1833 4 : *class = ATA_DEV_NONE;
1834 8 : } else if (rc) {
1835 : /* link occupied, -ENODEV too is an error */
1836 4 : reason = "device not ready";
1837 4 : goto fail;
1838 : } else
1839 8 : *class = ahci_dev_classify(ap);
1840 :
1841 : DPRINTK("EXIT, class=%u\n", *class);
1842 8 : return 0;
1843 8 :
1844 : fail:
1845 44 : ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1846 4 : return rc;
1847 : }
1848 :
1849 : static int ahci_check_ready(struct ata_link *link)
1850 : {
1851 0 : void __iomem *port_mmio = ahci_port_base(link->ap);
1852 0 : u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1853 0 :
1854 0 : return ata_check_ready(status);
1855 0 : }
1856 :
1857 : static int ahci_softreset(struct ata_link *link, unsigned int *class,
1858 : unsigned long deadline)
1859 4 : {
1860 20 : int pmp = sata_srst_pmp(link);
1861 4 :
1862 : DPRINTK("ENTER\n");
1863 :
1864 20 : return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1865 : }
1866 :
1867 : static int ahci_sb600_check_ready(struct ata_link *link)
1868 : {
1869 0 : void __iomem *port_mmio = ahci_port_base(link->ap);
1870 0 : u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1871 0 : u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1872 0 :
1873 0 : /*
1874 0 : * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1875 0 : * which can save timeout delay.
1876 : */
1877 0 : if (irq_status & PORT_IRQ_BAD_PMP)
1878 0 : return -EIO;
1879 :
1880 0 : return ata_check_ready(status);
1881 : }
1882 :
1883 : static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1884 : unsigned long deadline)
1885 0 : {
1886 0 : struct ata_port *ap = link->ap;
1887 0 : void __iomem *port_mmio = ahci_port_base(ap);
1888 0 : int pmp = sata_srst_pmp(link);
1889 0 : int rc;
1890 0 : u32 irq_sts;
1891 0 :
1892 0 : DPRINTK("ENTER\n");
1893 :
1894 0 : rc = ahci_do_softreset(link, class, pmp, deadline,
1895 : ahci_sb600_check_ready);
1896 :
1897 : /*
1898 : * Soft reset fails on some ATI chips with IPMS set when PMP
1899 : * is enabled but SATA HDD/ODD is connected to SATA port,
1900 : * do soft reset again to port 0.
1901 : */
1902 0 : if (rc == -EIO) {
1903 0 : irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1904 0 : if (irq_sts & PORT_IRQ_BAD_PMP) {
1905 0 : ata_link_printk(link, KERN_WARNING,
1906 : "applying SB600 PMP SRST workaround "
1907 : "and retrying\n");
1908 0 : rc = ahci_do_softreset(link, class, 0, deadline,
1909 : ahci_check_ready);
1910 : }
1911 : }
1912 :
1913 0 : return rc;
1914 : }
1915 :
1916 : static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1917 : unsigned long deadline)
1918 0 : {
1919 0 : const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1920 0 : struct ata_port *ap = link->ap;
1921 0 : struct ahci_port_priv *pp = ap->private_data;
1922 0 : u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1923 0 : struct ata_taskfile tf;
1924 0 : bool online;
1925 0 : int rc;
1926 :
1927 : DPRINTK("ENTER\n");
1928 :
1929 0 : ahci_stop_engine(ap);
1930 :
1931 : /* clear D2H reception area to properly wait for D2H FIS */
1932 0 : ata_tf_init(link->device, &tf);
1933 0 : tf.command = 0x80;
1934 0 : ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1935 :
1936 0 : rc = sata_link_hardreset(link, timing, deadline, &online,
1937 : ahci_check_ready);
1938 :
1939 0 : ahci_start_engine(ap);
1940 :
1941 0 : if (online)
1942 0 : *class = ahci_dev_classify(ap);
1943 :
1944 : DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1945 0 : return rc;
1946 : }
1947 :
1948 : static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1949 : unsigned long deadline)
1950 1 : {
1951 2 : struct ata_port *ap = link->ap;
1952 1 : bool online;
1953 1 : int rc;
1954 :
1955 : DPRINTK("ENTER\n");
1956 :
1957 3 : ahci_stop_engine(ap);
1958 :
1959 3 : rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1960 : deadline, &online, NULL);
1961 :
1962 2 : ahci_start_engine(ap);
1963 :
1964 : DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1965 :
1966 : /* vt8251 doesn't clear BSY on signature FIS reception,
1967 : * request follow-up softreset.
1968 : */
1969 6 : return online ? -EAGAIN : rc;
1970 : }
1971 :
1972 : static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1973 : unsigned long deadline)
1974 1 : {
1975 2 : struct ata_port *ap = link->ap;
1976 3 : struct ahci_port_priv *pp = ap->private_data;
1977 2 : u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1978 1 : struct ata_taskfile tf;
1979 1 : bool online;
1980 1 : int rc;
1981 :
1982 3 : ahci_stop_engine(ap);
1983 :
1984 : /* clear D2H reception area to properly wait for D2H FIS */
1985 2 : ata_tf_init(link->device, &tf);
1986 1 : tf.command = 0x80;
1987 1 : ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1988 :
1989 3 : rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1990 : deadline, &online, NULL);
1991 :
1992 2 : ahci_start_engine(ap);
1993 :
1994 : /* The pseudo configuration device on SIMG4726 attached to
1995 : * ASUS P5W-DH Deluxe doesn't send signature FIS after
1996 : * hardreset if no device is attached to the first downstream
1997 : * port && the pseudo device locks up on SRST w/ PMP==0. To
1998 : * work around this, wait for !BSY only briefly. If BSY isn't
1999 : * cleared, perform CLO and proceed to IDENTIFY (achieved by
2000 : * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
2001 : *
2002 : * Wait for two seconds. Devices attached to downstream port
2003 : * which can't process the following IDENTIFY after this will
2004 : * have to be reset again. For most cases, this should
2005 : * suffice while making probing snappish enough.
2006 : */
2007 2 : if (online) {
2008 1 : rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
2009 : ahci_check_ready);
2010 2 : if (rc)
2011 2 : ahci_kick_engine(ap);
2012 : }
2013 2 : return rc;
2014 : }
2015 :
2016 : static void ahci_postreset(struct ata_link *link, unsigned int *class)
2017 : {
2018 4 : struct ata_port *ap = link->ap;
2019 8 : void __iomem *port_mmio = ahci_port_base(ap);
2020 2 : u32 new_tmp, tmp;
2021 2 :
2022 4 : ata_std_postreset(link, class);
2023 :
2024 : /* Make sure port's ATAPI bit is set appropriately */
2025 6 : new_tmp = tmp = readl(port_mmio + PORT_CMD);
2026 4 : if (*class == ATA_DEV_ATAPI)
2027 2 : new_tmp |= PORT_CMD_ATAPI;
2028 : else
2029 2 : new_tmp &= ~PORT_CMD_ATAPI;
2030 4 : if (new_tmp != tmp) {
2031 4 : writel(new_tmp, port_mmio + PORT_CMD);
2032 4 : readl(port_mmio + PORT_CMD); /* flush */
2033 : }
2034 4 : }
2035 :
2036 : static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
2037 : {
2038 2 : struct scatterlist *sg;
2039 4 : struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
2040 2 : unsigned int si;
2041 2 :
2042 2 : VPRINTK("ENTER\n");
2043 :
2044 : /*
2045 : * Next, the S/G list.
2046 : */
2047 14 : for_each_sg(qc->sg, sg, qc->n_elem, si) {
2048 4 : dma_addr_t addr = sg_dma_address(sg);
2049 6 : u32 sg_len = sg_dma_len(sg);
2050 :
2051 2 : ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
2052 2 : ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
2053 2 : ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
2054 : }
2055 :
2056 2 : return si;
2057 : }
2058 :
2059 : static void ahci_qc_prep(struct ata_queued_cmd *qc)
2060 : {
2061 4 : struct ata_port *ap = qc->ap;
2062 6 : struct ahci_port_priv *pp = ap->private_data;
2063 8 : int is_atapi = ata_is_atapi(qc->tf.protocol);
2064 2 : void *cmd_tbl;
2065 2 : u32 opts;
2066 4 : const u32 cmd_fis_len = 5; /* five dwords */
2067 2 : unsigned int n_elem;
2068 2 :
2069 : /*
2070 : * Fill in command table information. First, the header,
2071 : * a SATA Register - Host to Device command FIS.
2072 : */
2073 2 : cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
2074 :
2075 4 : ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
2076 4 : if (is_atapi) {
2077 2 : memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
2078 4 : memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
2079 : }
2080 :
2081 2 : n_elem = 0;
2082 4 : if (qc->flags & ATA_QCFLAG_DMAMAP)
2083 4 : n_elem = ahci_fill_sg(qc, cmd_tbl);
2084 :
2085 : /*
2086 : * Fill in command slot information.
2087 : */
2088 4 : opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
2089 8 : if (qc->tf.flags & ATA_TFLAG_WRITE)
2090 4 : opts |= AHCI_CMD_WRITE;
2091 8 : if (is_atapi)
2092 4 : opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
2093 :
2094 8 : ahci_fill_cmd_slot(pp, qc->tag, opts);
2095 2 : }
2096 :
2097 : static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
2098 : {
2099 0 : struct ahci_host_priv *hpriv = ap->host->private_data;
2100 0 : struct ahci_port_priv *pp = ap->private_data;
2101 0 : struct ata_eh_info *host_ehi = &ap->link.eh_info;
2102 0 : struct ata_link *link = NULL;
2103 0 : struct ata_queued_cmd *active_qc;
2104 0 : struct ata_eh_info *active_ehi;
2105 0 : u32 serror;
2106 0 :
2107 0 : /* determine active link */
2108 0 : ata_for_each_link(link, ap, EDGE)
2109 0 : if (ata_link_active(link))
2110 0 : break;
2111 0 : if (!link)
2112 0 : link = &ap->link;
2113 :
2114 0 : active_qc = ata_qc_from_tag(ap, link->active_tag);
2115 0 : active_ehi = &link->eh_info;
2116 :
2117 : /* record irq stat */
2118 0 : ata_ehi_clear_desc(host_ehi);
2119 0 : ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
2120 :
2121 : /* AHCI needs SError cleared; otherwise, it might lock up */
2122 0 : ahci_scr_read(&ap->link, SCR_ERROR, &serror);
2123 0 : ahci_scr_write(&ap->link, SCR_ERROR, serror);
2124 0 : host_ehi->serror |= serror;
2125 :
2126 : /* some controllers set IRQ_IF_ERR on device errors, ignore it */
2127 0 : if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
2128 0 : irq_stat &= ~PORT_IRQ_IF_ERR;
2129 :
2130 0 : if (irq_stat & PORT_IRQ_TF_ERR) {
2131 : /* If qc is active, charge it; otherwise, the active
2132 : * link. There's no active qc on NCQ errors. It will
2133 : * be determined by EH by reading log page 10h.
2134 : */
2135 0 : if (active_qc)
2136 0 : active_qc->err_mask |= AC_ERR_DEV;
2137 : else
2138 0 : active_ehi->err_mask |= AC_ERR_DEV;
2139 :
2140 0 : if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
2141 0 : host_ehi->serror &= ~SERR_INTERNAL;
2142 : }
2143 :
2144 0 : if (irq_stat & PORT_IRQ_UNK_FIS) {
2145 0 : u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
2146 :
2147 0 : active_ehi->err_mask |= AC_ERR_HSM;
2148 0 : active_ehi->action |= ATA_EH_RESET;
2149 0 : ata_ehi_push_desc(active_ehi,
2150 : "unknown FIS %08x %08x %08x %08x" ,
2151 : unk[0], unk[1], unk[2], unk[3]);
2152 : }
2153 :
2154 0 : if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
2155 0 : active_ehi->err_mask |= AC_ERR_HSM;
2156 0 : active_ehi->action |= ATA_EH_RESET;
2157 0 : ata_ehi_push_desc(active_ehi, "incorrect PMP");
2158 : }
2159 :
2160 0 : if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
2161 0 : host_ehi->err_mask |= AC_ERR_HOST_BUS;
2162 0 : host_ehi->action |= ATA_EH_RESET;
2163 0 : ata_ehi_push_desc(host_ehi, "host bus error");
2164 : }
2165 :
2166 0 : if (irq_stat & PORT_IRQ_IF_ERR) {
2167 0 : host_ehi->err_mask |= AC_ERR_ATA_BUS;
2168 0 : host_ehi->action |= ATA_EH_RESET;
2169 0 : ata_ehi_push_desc(host_ehi, "interface fatal error");
2170 : }
2171 :
2172 0 : if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
2173 0 : ata_ehi_hotplugged(host_ehi);
2174 0 : ata_ehi_push_desc(host_ehi, "%s",
2175 : irq_stat & PORT_IRQ_CONNECT ?
2176 : "connection status changed" : "PHY RDY changed");
2177 : }
2178 :
2179 : /* okay, let's hand over to EH */
2180 :
2181 0 : if (irq_stat & PORT_IRQ_FREEZE)
2182 0 : ata_port_freeze(ap);
2183 : else
2184 0 : ata_port_abort(ap);
2185 0 : }
2186 :
2187 : static void ahci_port_intr(struct ata_port *ap)
2188 : {
2189 0 : void __iomem *port_mmio = ahci_port_base(ap);
2190 0 : struct ata_eh_info *ehi = &ap->link.eh_info;
2191 0 : struct ahci_port_priv *pp = ap->private_data;
2192 0 : struct ahci_host_priv *hpriv = ap->host->private_data;
2193 0 : int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
2194 0 : u32 status, qc_active;
2195 0 : int rc;
2196 0 :
2197 0 : status = readl(port_mmio + PORT_IRQ_STAT);
2198 0 : writel(status, port_mmio + PORT_IRQ_STAT);
2199 0 :
2200 0 : /* ignore BAD_PMP while resetting */
2201 0 : if (unlikely(resetting))
2202 0 : status &= ~PORT_IRQ_BAD_PMP;
2203 :
2204 : /* If we are getting PhyRdy, this is
2205 : * just a power state change, we should
2206 : * clear out this, plus the PhyRdy/Comm
2207 : * Wake bits from Serror
2208 : */
2209 0 : if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2210 : (status & PORT_IRQ_PHYRDY)) {
2211 0 : status &= ~PORT_IRQ_PHYRDY;
2212 0 : ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
2213 : }
2214 :
2215 0 : if (unlikely(status & PORT_IRQ_ERROR)) {
2216 0 : ahci_error_intr(ap, status);
2217 0 : return;
2218 : }
2219 :
2220 0 : if (status & PORT_IRQ_SDB_FIS) {
2221 : /* If SNotification is available, leave notification
2222 : * handling to sata_async_notification(). If not,
2223 : * emulate it by snooping SDB FIS RX area.
2224 : *
2225 : * Snooping FIS RX area is probably cheaper than
2226 : * poking SNotification but some constrollers which
2227 : * implement SNotification, ICH9 for example, don't
2228 : * store AN SDB FIS into receive area.
2229 : */
2230 0 : if (hpriv->cap & HOST_CAP_SNTF)
2231 0 : sata_async_notification(ap);
2232 : else {
2233 : /* If the 'N' bit in word 0 of the FIS is set,
2234 : * we just received asynchronous notification.
2235 : * Tell libata about it.
2236 : */
2237 0 : const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2238 0 : u32 f0 = le32_to_cpu(f[0]);
2239 :
2240 0 : if (f0 & (1 << 15))
2241 0 : sata_async_notification(ap);
2242 : }
2243 : }
2244 :
2245 : /* pp->active_link is valid iff any command is in flight */
2246 0 : if (ap->qc_active && pp->active_link->sactive)
2247 0 : qc_active = readl(port_mmio + PORT_SCR_ACT);
2248 : else
2249 0 : qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2250 :
2251 0 : rc = ata_qc_complete_multiple(ap, qc_active);
2252 :
2253 : /* while resetting, invalid completions are expected */
2254 0 : if (unlikely(rc < 0 && !resetting)) {
2255 0 : ehi->err_mask |= AC_ERR_HSM;
2256 0 : ehi->action |= ATA_EH_RESET;
2257 0 : ata_port_freeze(ap);
2258 : }
2259 0 : }
2260 :
2261 : static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
2262 : {
2263 0 : struct ata_host *host = dev_instance;
2264 0 : struct ahci_host_priv *hpriv;
2265 0 : unsigned int i, handled = 0;
2266 0 : void __iomem *mmio;
2267 0 : u32 irq_stat, irq_masked;
2268 0 :
2269 0 : VPRINTK("ENTER\n");
2270 0 :
2271 0 : hpriv = host->private_data;
2272 0 : mmio = host->iomap[AHCI_PCI_BAR];
2273 0 :
2274 : /* sigh. 0xffffffff is a valid return from h/w */
2275 0 : irq_stat = readl(mmio + HOST_IRQ_STAT);
2276 0 : if (!irq_stat)
2277 0 : return IRQ_NONE;
2278 :
2279 0 : irq_masked = irq_stat & hpriv->port_map;
2280 :
2281 0 : spin_lock(&host->lock);
2282 :
2283 0 : for (i = 0; i < host->n_ports; i++) {
2284 0 : struct ata_port *ap;
2285 0 :
2286 0 : if (!(irq_masked & (1 << i)))
2287 0 : continue;
2288 :
2289 0 : ap = host->ports[i];
2290 0 : if (ap) {
2291 0 : ahci_port_intr(ap);
2292 : VPRINTK("port %u\n", i);
2293 : } else {
2294 : VPRINTK("port %u (no irq)\n", i);
2295 0 : if (ata_ratelimit())
2296 0 : dev_printk(KERN_WARNING, host->dev,
2297 : "interrupt on disabled port %u\n", i);
2298 : }
2299 :
2300 0 : handled = 1;
2301 0 : }
2302 :
2303 : /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2304 : * it should be cleared after all the port events are cleared;
2305 : * otherwise, it will raise a spurious interrupt after each
2306 : * valid one. Please read section 10.6.2 of ahci 1.1 for more
2307 : * information.
2308 : *
2309 : * Also, use the unmasked value to clear interrupt as spurious
2310 : * pending event on a dummy port might cause screaming IRQ.
2311 : */
2312 0 : writel(irq_stat, mmio + HOST_IRQ_STAT);
2313 :
2314 0 : spin_unlock(&host->lock);
2315 :
2316 : VPRINTK("EXIT\n");
2317 :
2318 0 : return IRQ_RETVAL(handled);
2319 : }
2320 :
2321 : static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2322 : {
2323 4 : struct ata_port *ap = qc->ap;
2324 8 : void __iomem *port_mmio = ahci_port_base(ap);
2325 6 : struct ahci_port_priv *pp = ap->private_data;
2326 2 :
2327 : /* Keep track of the currently active link. It will be used
2328 : * in completion path to determine whether NCQ phase is in
2329 : * progress.
2330 : */
2331 2 : pp->active_link = qc->dev->link;
2332 :
2333 4 : if (qc->tf.protocol == ATA_PROT_NCQ)
2334 6 : writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2335 12 : writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2336 :
2337 8 : ahci_sw_activity(qc->dev->link);
2338 :
2339 2 : return 0;
2340 : }
2341 :
2342 : static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2343 : {
2344 6 : struct ahci_port_priv *pp = qc->ap->private_data;
2345 4 : u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2346 :
2347 2 : ata_tf_from_fis(d2h_fis, &qc->result_tf);
2348 2 : return true;
2349 : }
2350 :
2351 : static void ahci_freeze(struct ata_port *ap)
2352 : {
2353 8 : void __iomem *port_mmio = ahci_port_base(ap);
2354 2 :
2355 : /* turn IRQ off */
2356 4 : writel(0, port_mmio + PORT_IRQ_MASK);
2357 2 : }
2358 :
2359 : static void ahci_thaw(struct ata_port *ap)
2360 : {
2361 4 : void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
2362 8 : void __iomem *port_mmio = ahci_port_base(ap);
2363 2 : u32 tmp;
2364 6 : struct ahci_port_priv *pp = ap->private_data;
2365 2 :
2366 : /* clear IRQ */
2367 4 : tmp = readl(port_mmio + PORT_IRQ_STAT);
2368 4 : writel(tmp, port_mmio + PORT_IRQ_STAT);
2369 6 : writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2370 :
2371 : /* turn IRQ back on */
2372 4 : writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2373 2 : }
2374 :
2375 : static void ahci_error_handler(struct ata_port *ap)
2376 : {
2377 4 : if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2378 : /* restart engine */
2379 6 : ahci_stop_engine(ap);
2380 4 : ahci_start_engine(ap);
2381 : }
2382 :
2383 4 : sata_pmp_error_handler(ap);
2384 4 : }
2385 :
2386 : static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2387 : {
2388 4 : struct ata_port *ap = qc->ap;
2389 :
2390 : /* make DMA engine forget about the failed command */
2391 4 : if (qc->flags & ATA_QCFLAG_FAILED)
2392 4 : ahci_kick_engine(ap);
2393 4 : }
2394 :
2395 : static void ahci_pmp_attach(struct ata_port *ap)
2396 : {
2397 16 : void __iomem *port_mmio = ahci_port_base(ap);
2398 12 : struct ahci_port_priv *pp = ap->private_data;
2399 4 : u32 cmd;
2400 4 :
2401 8 : cmd = readl(port_mmio + PORT_CMD);
2402 4 : cmd |= PORT_CMD_PMP;
2403 8 : writel(cmd, port_mmio + PORT_CMD);
2404 :
2405 4 : pp->intr_mask |= PORT_IRQ_BAD_PMP;
2406 8 : writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2407 4 : }
2408 :
2409 : static void ahci_pmp_detach(struct ata_port *ap)
2410 : {
2411 16 : void __iomem *port_mmio = ahci_port_base(ap);
2412 12 : struct ahci_port_priv *pp = ap->private_data;
2413 4 : u32 cmd;
2414 4 :
2415 8 : cmd = readl(port_mmio + PORT_CMD);
2416 4 : cmd &= ~PORT_CMD_PMP;
2417 8 : writel(cmd, port_mmio + PORT_CMD);
2418 :
2419 4 : pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2420 8 : writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2421 4 : }
2422 :
2423 : static int ahci_port_resume(struct ata_port *ap)
2424 : {
2425 6 : ahci_power_up(ap);
2426 8 : ahci_start_port(ap);
2427 :
2428 8 : if (sata_pmp_attached(ap))
2429 4 : ahci_pmp_attach(ap);
2430 : else
2431 4 : ahci_pmp_detach(ap);
2432 :
2433 4 : return 0;
2434 : }
2435 :
2436 : #ifdef CONFIG_PM
2437 : static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2438 : {
2439 : const char *emsg = NULL;
2440 : int rc;
2441 :
2442 : rc = ahci_deinit_port(ap, &emsg);
2443 : if (rc == 0)
2444 : ahci_power_down(ap);
2445 : else {
2446 : ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2447 : ahci_start_port(ap);
2448 : }
2449 :
2450 : return rc;
2451 : }
2452 :
2453 : static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2454 : {
2455 : struct ata_host *host = dev_get_drvdata(&pdev->dev);
2456 : struct ahci_host_priv *hpriv = host->private_data;
2457 : void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2458 : u32 ctl;
2459 :
2460 : if (mesg.event & PM_EVENT_SUSPEND &&
2461 : hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
2462 : dev_printk(KERN_ERR, &pdev->dev,
2463 : "BIOS update required for suspend/resume\n");
2464 : return -EIO;
2465 : }
2466 :
2467 : if (mesg.event & PM_EVENT_SLEEP) {
2468 : /* AHCI spec rev1.1 section 8.3.3:
2469 : * Software must disable interrupts prior to requesting a
2470 : * transition of the HBA to D3 state.
2471 : */
2472 : ctl = readl(mmio + HOST_CTL);
2473 : ctl &= ~HOST_IRQ_EN;
2474 : writel(ctl, mmio + HOST_CTL);
2475 : readl(mmio + HOST_CTL); /* flush */
2476 : }
2477 :
2478 : return ata_pci_device_suspend(pdev, mesg);
2479 : }
2480 :
2481 : static int ahci_pci_device_resume(struct pci_dev *pdev)
2482 : {
2483 : struct ata_host *host = dev_get_drvdata(&pdev->dev);
2484 : int rc;
2485 :
2486 : rc = ata_pci_device_do_resume(pdev);
2487 : if (rc)
2488 : return rc;
2489 :
2490 : if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2491 : rc = ahci_reset_controller(host);
2492 : if (rc)
2493 : return rc;
2494 :
2495 : ahci_init_controller(host);
2496 : }
2497 :
2498 : ata_host_resume(host);
2499 :
2500 : return 0;
2501 : }
2502 : #endif
2503 :
2504 : static int ahci_port_start(struct ata_port *ap)
2505 : {
2506 4 : struct device *dev = ap->host->dev;
2507 2 : struct ahci_port_priv *pp;
2508 2 : void *mem;
2509 2 : dma_addr_t mem_dma;
2510 2 :
2511 6 : pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2512 4 : if (!pp)
2513 2 : return -ENOMEM;
2514 :
2515 2 : mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2516 : GFP_KERNEL);
2517 4 : if (!mem)
2518 2 : return -ENOMEM;
2519 2 : memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2520 :
2521 : /*
2522 : * First item in chunk of DMA memory: 32-slot command table,
2523 : * 32 bytes each in size
2524 : */
2525 2 : pp->cmd_slot = mem;
2526 2 : pp->cmd_slot_dma = mem_dma;
2527 :
2528 2 : mem += AHCI_CMD_SLOT_SZ;
2529 2 : mem_dma += AHCI_CMD_SLOT_SZ;
2530 :
2531 : /*
2532 : * Second item: Received-FIS area
2533 : */
2534 2 : pp->rx_fis = mem;
2535 2 : pp->rx_fis_dma = mem_dma;
2536 :
2537 2 : mem += AHCI_RX_FIS_SZ;
2538 2 : mem_dma += AHCI_RX_FIS_SZ;
2539 :
2540 : /*
2541 : * Third item: data area for storing a single command
2542 : * and its scatter-gather table
2543 : */
2544 2 : pp->cmd_tbl = mem;
2545 2 : pp->cmd_tbl_dma = mem_dma;
2546 :
2547 : /*
2548 : * Save off initial list of interrupts to be enabled.
2549 : * This could be changed later
2550 : */
2551 2 : pp->intr_mask = DEF_PORT_IRQ;
2552 :
2553 2 : ap->private_data = pp;
2554 :
2555 : /* engage engines, captain */
2556 8 : return ahci_port_resume(ap);
2557 : }
2558 :
2559 : static void ahci_port_stop(struct ata_port *ap)
2560 : {
2561 4 : const char *emsg = NULL;
2562 2 : int rc;
2563 :
2564 : /* de-initialize port */
2565 6 : rc = ahci_deinit_port(ap, &emsg);
2566 4 : if (rc)
2567 2 : ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2568 2 : }
2569 :
2570 : static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2571 : {
2572 1 : int rc;
2573 1 :
2574 7 : if (using_dac &&
2575 1 : !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2576 2 : rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2577 4 : if (rc) {
2578 2 : rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2579 3 : if (rc) {
2580 4 : dev_printk(KERN_ERR, &pdev->dev,
2581 : "64-bit DMA enable failed\n");
2582 1 : return rc;
2583 : }
2584 : }
2585 : } else {
2586 1 : rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2587 2 : if (rc) {
2588 4 : dev_printk(KERN_ERR, &pdev->dev,
2589 : "32-bit DMA enable failed\n");
2590 1 : return rc;
2591 : }
2592 1 : rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2593 2 : if (rc) {
2594 4 : dev_printk(KERN_ERR, &pdev->dev,
2595 : "32-bit consistent DMA enable failed\n");
2596 1 : return rc;
2597 : }
2598 : }
2599 1 : return 0;
2600 : }
2601 :
2602 : static void ahci_print_info(struct ata_host *host)
2603 : {
2604 3 : struct ahci_host_priv *hpriv = host->private_data;
2605 4 : struct pci_dev *pdev = to_pci_dev(host->dev);
2606 2 : void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2607 1 : u32 vers, cap, cap2, impl, speed;
2608 1 : const char *speed_s;
2609 1 : u16 cc;
2610 1 : const char *scc_s;
2611 1 :
2612 3 : vers = readl(mmio + HOST_VERSION);
2613 2 : cap = hpriv->cap;
2614 2 : cap2 = hpriv->cap2;
2615 2 : impl = hpriv->port_map;
2616 1 :
2617 2 : speed = (cap >> 20) & 0xf;
2618 3 : if (speed == 1)
2619 2 : speed_s = "1.5";
2620 2 : else if (speed == 2)
2621 1 : speed_s = "3";
2622 2 : else if (speed == 3)
2623 1 : speed_s = "6";
2624 : else
2625 1 : speed_s = "?";
2626 :
2627 2 : pci_read_config_word(pdev, 0x0a, &cc);
2628 2 : if (cc == PCI_CLASS_STORAGE_IDE)
2629 1 : scc_s = "IDE";
2630 2 : else if (cc == PCI_CLASS_STORAGE_SATA)
2631 1 : scc_s = "SATA";
2632 2 : else if (cc == PCI_CLASS_STORAGE_RAID)
2633 1 : scc_s = "RAID";
2634 : else
2635 1 : scc_s = "unknown";
2636 :
2637 4 : dev_printk(KERN_INFO, &pdev->dev,
2638 : "AHCI %02x%02x.%02x%02x "
2639 : "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2640 : ,
2641 :
2642 : (vers >> 24) & 0xff,
2643 : (vers >> 16) & 0xff,
2644 : (vers >> 8) & 0xff,
2645 : vers & 0xff,
2646 :
2647 : ((cap >> 8) & 0x1f) + 1,
2648 : (cap & 0x1f) + 1,
2649 : speed_s,
2650 : impl,
2651 : scc_s);
2652 :
2653 24 : dev_printk(KERN_INFO, &pdev->dev,
2654 9 : "flags: "
2655 8 : "%s%s%s%s%s%s%s"
2656 8 : "%s%s%s%s%s%s%s"
2657 8 : "%s%s%s%s%s%s\n"
2658 8 : ,
2659 8 :
2660 8 : cap & HOST_CAP_64 ? "64bit " : "",
2661 8 : cap & HOST_CAP_NCQ ? "ncq " : "",
2662 8 : cap & HOST_CAP_SNTF ? "sntf " : "",
2663 8 : cap & HOST_CAP_MPS ? "ilck " : "",
2664 : cap & HOST_CAP_SSS ? "stag " : "",
2665 : cap & HOST_CAP_ALPM ? "pm " : "",
2666 : cap & HOST_CAP_LED ? "led " : "",
2667 : cap & HOST_CAP_CLO ? "clo " : "",
2668 : cap & HOST_CAP_ONLY ? "only " : "",
2669 : cap & HOST_CAP_PMP ? "pmp " : "",
2670 : cap & HOST_CAP_FBS ? "fbs " : "",
2671 : cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2672 : cap & HOST_CAP_SSC ? "slum " : "",
2673 : cap & HOST_CAP_PART ? "part " : "",
2674 : cap & HOST_CAP_CCC ? "ccc " : "",
2675 : cap & HOST_CAP_EMS ? "ems " : "",
2676 : cap & HOST_CAP_SXS ? "sxs " : "",
2677 : cap2 & HOST_CAP2_APST ? "apst " : "",
2678 : cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2679 : cap2 & HOST_CAP2_BOH ? "boh " : ""
2680 : );
2681 : }
2682 :
2683 : /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2684 : * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2685 : * support PMP and the 4726 either directly exports the device
2686 : * attached to the first downstream port or acts as a hardware storage
2687 : * controller and emulate a single ATA device (can be RAID 0/1 or some
2688 : * other configuration).
2689 : *
2690 : * When there's no device attached to the first downstream port of the
2691 : * 4726, "Config Disk" appears, which is a pseudo ATA device to
2692 : * configure the 4726. However, ATA emulation of the device is very
2693 : * lame. It doesn't send signature D2H Reg FIS after the initial
2694 : * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2695 : *
2696 : * The following function works around the problem by always using
2697 : * hardreset on the port and not depending on receiving signature FIS
2698 : * afterward. If signature FIS isn't received soon, ATA class is
2699 : * assumed without follow-up softreset.
2700 : */
2701 : static void ahci_p5wdh_workaround(struct ata_host *host)
2702 : {
2703 474 : static struct dmi_system_id sysids[] = {
2704 5 : {
2705 5 : .ident = "P5W DH Deluxe",
2706 1 : .matches = {
2707 1 : DMI_MATCH(DMI_SYS_VENDOR,
2708 1 : "ASUSTEK COMPUTER INC"),
2709 1 : DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2710 1 : },
2711 1 : },
2712 1 : { }
2713 1 : };
2714 3 : struct pci_dev *pdev = to_pci_dev(host->dev);
2715 :
2716 9 : if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2717 : dmi_check_system(sysids)) {
2718 1 : struct ata_port *ap = host->ports[1];
2719 :
2720 4 : dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2721 : "Deluxe on-board SIMG4726 workaround\n");
2722 :
2723 1 : ap->ops = &ahci_p5wdh_ops;
2724 1 : ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2725 : }
2726 3 : }
2727 :
2728 : /* only some SB600 ahci controllers can do 64bit DMA */
2729 : static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
2730 : {
2731 2940 : static const struct dmi_system_id sysids[] = {
2732 44 : /*
2733 44 : * The oldest version known to be broken is 0901 and
2734 4 : * working is 1501 which was released on 2007-10-26.
2735 4 : * Enable 64bit DMA on 1501 and anything newer.
2736 4 : *
2737 4 : * Please read bko#9412 for more info.
2738 4 : */
2739 4 : {
2740 4 : .ident = "ASUS M2A-VM",
2741 4 : .matches = {
2742 4 : DMI_MATCH(DMI_BOARD_VENDOR,
2743 4 : "ASUSTeK Computer INC."),
2744 4 : DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
2745 4 : },
2746 4 : .driver_data = "20071026", /* yyyymmdd */
2747 4 : },
2748 4 : /*
2749 4 : * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
2750 4 : * support 64bit DMA.
2751 4 : *
2752 : * BIOS versions earlier than 1.5 had the Manufacturer DMI
2753 : * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
2754 : * This spelling mistake was fixed in BIOS version 1.5, so
2755 : * 1.5 and later have the Manufacturer as
2756 : * "MICRO-STAR INTERNATIONAL CO.,LTD".
2757 : * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
2758 : *
2759 : * BIOS versions earlier than 1.9 had a Board Product Name
2760 : * DMI field of "MS-7376". This was changed to be
2761 : * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
2762 : * match on DMI_BOARD_NAME of "MS-7376".
2763 : */
2764 : {
2765 : .ident = "MSI K9A2 Platinum",
2766 : .matches = {
2767 : DMI_MATCH(DMI_BOARD_VENDOR,
2768 : "MICRO-STAR INTER"),
2769 : DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
2770 : },
2771 : },
2772 : /*
2773 : * All BIOS versions for the Asus M3A support 64bit DMA.
2774 : * (all release versions from 0301 to 1206 were tested)
2775 : */
2776 : {
2777 : .ident = "ASUS M3A",
2778 : .matches = {
2779 : DMI_MATCH(DMI_BOARD_VENDOR,
2780 : "ASUSTeK Computer INC."),
2781 : DMI_MATCH(DMI_BOARD_NAME, "M3A"),
2782 : },
2783 : },
2784 : { }
2785 : };
2786 : const struct dmi_system_id *match;
2787 : int year, month, date;
2788 : char buf[9];
2789 :
2790 8 : match = dmi_first_match(sysids);
2791 28 : if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
2792 : !match)
2793 4 : return false;
2794 :
2795 12 : if (!match->driver_data)
2796 4 : goto enable_64bit;
2797 :
2798 8 : dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
2799 4 : snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
2800 :
2801 16 : if (strcmp(buf, match->driver_data) >= 0)
2802 : goto enable_64bit;
2803 : else {
2804 16 : dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
2805 : "forcing 32bit DMA, update BIOS\n", match->ident);
2806 4 : return false;
2807 : }
2808 4 :
2809 : enable_64bit:
2810 24 : dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
2811 : match->ident);
2812 4 : return true;
2813 : }
2814 :
2815 : static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
2816 : {
2817 1224 : static const struct dmi_system_id broken_systems[] = {
2818 16 : {
2819 16 : .ident = "HP Compaq nx6310",
2820 2 : .matches = {
2821 2 : DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2822 2 : DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
2823 2 : },
2824 2 : /* PCI slot number of the controller */
2825 2 : .driver_data = (void *)0x1FUL,
2826 2 : },
2827 2 : {
2828 : .ident = "HP Compaq 6720s",
2829 : .matches = {
2830 : DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2831 : DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
2832 : },
2833 : /* PCI slot number of the controller */
2834 : .driver_data = (void *)0x1FUL,
2835 : },
2836 :
2837 : { } /* terminate list */
2838 : };
2839 6 : const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
2840 :
2841 4 : if (dmi) {
2842 4 : unsigned long slot = (unsigned long)dmi->driver_data;
2843 : /* apply the quirk only to on-board controllers */
2844 2 : return slot == PCI_SLOT(pdev->devfn);
2845 : }
2846 :
2847 2 : return false;
2848 : }
2849 :
2850 : static bool ahci_broken_suspend(struct pci_dev *pdev)
2851 : {
2852 2130 : static const struct dmi_system_id sysids[] = {
2853 34 : /*
2854 34 : * On HP dv[4-6] and HDX18 with earlier BIOSen, link
2855 2 : * to the harddisk doesn't become online after
2856 2 : * resuming from STR. Warn and fail suspend.
2857 2 : *
2858 2 : * http://bugzilla.kernel.org/show_bug.cgi?id=12276
2859 2 : *
2860 2 : * Use dates instead of versions to match as HP is
2861 2 : * apparently recycling both product and version
2862 2 : * strings.
2863 2 : *
2864 2 : * http://bugzilla.kernel.org/show_bug.cgi?id=15462
2865 2 : */
2866 2 : {
2867 2 : .ident = "dv4",
2868 2 : .matches = {
2869 2 : DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2870 2 : DMI_MATCH(DMI_PRODUCT_NAME,
2871 2 : "HP Pavilion dv4 Notebook PC"),
2872 2 : },
2873 2 : .driver_data = "20090105", /* F.30 */
2874 2 : },
2875 2 : {
2876 : .ident = "dv5",
2877 : .matches = {
2878 : DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2879 : DMI_MATCH(DMI_PRODUCT_NAME,
2880 : "HP Pavilion dv5 Notebook PC"),
2881 : },
2882 : .driver_data = "20090506", /* F.16 */
2883 : },
2884 : {
2885 : .ident = "dv6",
2886 : .matches = {
2887 : DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2888 : DMI_MATCH(DMI_PRODUCT_NAME,
2889 : "HP Pavilion dv6 Notebook PC"),
2890 : },
2891 : .driver_data = "20090423", /* F.21 */
2892 : },
2893 : {
2894 : .ident = "HDX18",
2895 : .matches = {
2896 : DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2897 : DMI_MATCH(DMI_PRODUCT_NAME,
2898 : "HP HDX18 Notebook PC"),
2899 : },
2900 : .driver_data = "20090430", /* F.23 */
2901 : },
2902 : /*
2903 : * Acer eMachines G725 has the same problem. BIOS
2904 : * V1.03 is known to be broken. V3.04 is known to
2905 : * work. Inbetween, there are V1.06, V2.06 and V3.03
2906 : * that we don't have much idea about. For now,
2907 : * blacklist anything older than V3.04.
2908 : *
2909 : * http://bugzilla.kernel.org/show_bug.cgi?id=15104
2910 : */
2911 : {
2912 : .ident = "G725",
2913 : .matches = {
2914 : DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
2915 : DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
2916 : },
2917 : .driver_data = "20091216", /* V3.04 */
2918 : },
2919 : { } /* terminate list */
2920 : };
2921 6 : const struct dmi_system_id *dmi = dmi_first_match(sysids);
2922 : int year, month, date;
2923 : char buf[9];
2924 :
2925 14 : if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
2926 2 : return false;
2927 :
2928 4 : dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
2929 2 : snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
2930 :
2931 6 : return strcmp(buf, dmi->driver_data) < 0;
2932 : }
2933 :
2934 : static bool ahci_broken_online(struct pci_dev *pdev)
2935 : {
2936 2 : #define ENCODE_BUSDEVFN(bus, slot, func) \
2937 2 : (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
2938 1250 : static const struct dmi_system_id sysids[] = {
2939 16 : /*
2940 16 : * There are several gigabyte boards which use
2941 2 : * SIMG5723s configured as hardware RAID. Certain
2942 2 : * 5723 firmware revisions shipped there keep the link
2943 2 : * online but fail to answer properly to SRST or
2944 2 : * IDENTIFY when no device is attached downstream
2945 2 : * causing libata to retry quite a few times leading
2946 2 : * to excessive detection delay.
2947 : *
2948 : * As these firmwares respond to the second reset try
2949 : * with invalid device signature, considering unknown
2950 : * sig as offline works around the problem acceptably.
2951 : */
2952 : {
2953 : .ident = "EP45-DQ6",
2954 : .matches = {
2955 : DMI_MATCH(DMI_BOARD_VENDOR,
2956 : "Gigabyte Technology Co., Ltd."),
2957 : DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
2958 : },
2959 : .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
2960 : },
2961 : {
2962 : .ident = "EP45-DS5",
2963 : .matches = {
2964 : DMI_MATCH(DMI_BOARD_VENDOR,
2965 : "Gigabyte Technology Co., Ltd."),
2966 : DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
2967 : },
2968 : .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
2969 : },
2970 : { } /* terminate list */
2971 : };
2972 : #undef ENCODE_BUSDEVFN
2973 6 : const struct dmi_system_id *dmi = dmi_first_match(sysids);
2974 : unsigned int val;
2975 :
2976 4 : if (!dmi)
2977 2 : return false;
2978 :
2979 4 : val = (unsigned long)dmi->driver_data;
2980 :
2981 14 : return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
2982 : }
2983 :
2984 : #ifdef CONFIG_ATA_ACPI
2985 : static void ahci_gtf_filter_workaround(struct ata_host *host)
2986 : {
2987 : static const struct dmi_system_id sysids[] = {
2988 : /*
2989 : * Aspire 3810T issues a bunch of SATA enable commands
2990 : * via _GTF including an invalid one and one which is
2991 : * rejected by the device. Among the successful ones
2992 : * is FPDMA non-zero offset enable which when enabled
2993 : * only on the drive side leads to NCQ command
2994 : * failures. Filter it out.
2995 : */
2996 : {
2997 : .ident = "Aspire 3810T",
2998 : .matches = {
2999 : DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
3000 : DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
3001 : },
3002 : .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
3003 : },
3004 : { }
3005 : };
3006 : const struct dmi_system_id *dmi = dmi_first_match(sysids);
3007 : unsigned int filter;
3008 : int i;
3009 :
3010 : if (!dmi)
3011 : return;
3012 :
3013 : filter = (unsigned long)dmi->driver_data;
3014 : dev_printk(KERN_INFO, host->dev,
3015 : "applying extra ACPI _GTF filter 0x%x for %s\n",
3016 : filter, dmi->ident);
3017 :
3018 : for (i = 0; i < host->n_ports; i++) {
3019 : struct ata_port *ap = host->ports[i];
3020 : struct ata_link *link;
3021 : struct ata_device *dev;
3022 :
3023 : ata_for_each_link(link, ap, EDGE)
3024 : ata_for_each_dev(dev, link, ALL)
3025 : dev->gtf_filter |= filter;
3026 : }
3027 : }
3028 : #else
3029 : static inline void ahci_gtf_filter_workaround(struct ata_host *host)
3030 : {}
3031 1 : #endif
3032 :
3033 : static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3034 : {
3035 1 : static int printed_version;
3036 3 : unsigned int board_id = ent->driver_data;
3037 2 : struct ata_port_info pi = ahci_port_info[board_id];
3038 3 : const struct ata_port_info *ppi[] = { &pi, NULL };
3039 2 : struct device *dev = &pdev->dev;
3040 1 : struct ahci_host_priv *hpriv;
3041 1 : struct ata_host *host;
3042 1 : int n_ports, i, rc;
3043 1 :
3044 1 : VPRINTK("ENTER\n");
3045 1 :
3046 9 : WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
3047 1 :
3048 5 : if (!printed_version++)
3049 5 : dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
3050 1 :
3051 1 : /* The AHCI driver can only drive the SATA ports, the PATA driver
3052 1 : can drive them all so if both drivers are selected make sure
3053 1 : AHCI stays out of the way */
3054 11 : if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
3055 3 : return -ENODEV;
3056 1 :
3057 1 : /*
3058 1 : * For some reason, MCP89 on MacBook 7,1 doesn't work with
3059 1 : * ahci, use ata_generic instead.
3060 1 : */
3061 9 : if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
3062 1 : pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
3063 1 : pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
3064 1 : pdev->subsystem_device == 0xcb89)
3065 3 : return -ENODEV;
3066 1 :
3067 1 : /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
3068 1 : * At the moment, we can only use the AHCI mode. Let the users know
3069 1 : * that for SAS drives they're out of luck.
3070 1 : */
3071 7 : if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
3072 7 : dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
3073 1 : "can only drive SATA devices with this driver\n");
3074 1 :
3075 1 : /* acquire resources */
3076 4 : rc = pcim_enable_device(pdev);
3077 7 : if (rc)
3078 4 : return rc;
3079 1 :
3080 : /* AHCI controllers often implement SFF compatible interface.
3081 : * Grab all PCI BARs just in case.
3082 : */
3083 3 : rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
3084 6 : if (rc == -EBUSY)
3085 3 : pcim_pin_device(pdev);
3086 6 : if (rc)
3087 3 : return rc;
3088 :
3089 18 : if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
3090 : (pdev->device == 0x2652 || pdev->device == 0x2653)) {
3091 : u8 map;
3092 :
3093 : /* ICH6s share the same PCI ID for both piix and ahci
3094 : * modes. Enabling ahci mode while MAP indicates
3095 : * combined mode is a bad idea. Yield to ata_piix.
3096 : */
3097 6 : pci_read_config_byte(pdev, ICH_MAP, &map);
3098 2 : if (map & 0x3) {
3099 4 : dev_printk(KERN_INFO, &pdev->dev, "controller is in "
3100 : "combined mode, can't enable AHCI mode\n");
3101 1 : return -ENODEV;
3102 : }
3103 : }
3104 :
3105 8 : hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
3106 8 : if (!hpriv)
3107 4 : return -ENOMEM;
3108 4 : hpriv->flags |= (unsigned long)pi.private_data;
3109 :
3110 : /* MCP65 revision A1 and A2 can't do MSI */
3111 20 : if (board_id == board_ahci_mcp65 &&
3112 : (pdev->revision == 0xa1 || pdev->revision == 0xa2))
3113 4 : hpriv->flags |= AHCI_HFLAG_NO_MSI;
3114 :
3115 : /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
3116 20 : if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
3117 4 : hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
3118 :
3119 : /* only some SB600s can do 64bit DMA */
3120 18 : if (ahci_sb600_enable_64bit(pdev))
3121 1 : hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
3122 :
3123 6 : if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
3124 2 : pci_intx(pdev, 1);
3125 :
3126 : /* save initial config */
3127 26 : ahci_save_initial_config(pdev, hpriv);
3128 :
3129 : /* prepare host */
3130 2 : if (hpriv->cap & HOST_CAP_NCQ) {
3131 1 : pi.flags |= ATA_FLAG_NCQ;
3132 : /* Auto-activate optimization is supposed to be supported on
3133 : all AHCI controllers indicating NCQ support, but it seems
3134 : to be broken at least on some NVIDIA MCP79 chipsets.
3135 : Until we get info on which NVIDIA chipsets don't have this
3136 : issue, if any, disable AA on all NVIDIA AHCIs. */
3137 3 : if (pdev->vendor != PCI_VENDOR_ID_NVIDIA)
3138 1 : pi.flags |= ATA_FLAG_FPDMA_AA;
3139 : }
3140 :
3141 2 : if (hpriv->cap & HOST_CAP_PMP)
3142 1 : pi.flags |= ATA_FLAG_PMP;
3143 :
3144 4 : if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
3145 : u8 messages;
3146 2 : void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
3147 3 : u32 em_loc = readl(mmio + HOST_EM_LOC);
3148 3 : u32 em_ctl = readl(mmio + HOST_EM_CTL);
3149 :
3150 1 : messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
3151 :
3152 : /* we only support LED message type right now */
3153 4 : if ((messages & 0x01) && (ahci_em_messages == 1)) {
3154 : /* store em_loc */
3155 1 : hpriv->em_loc = ((em_loc >> 16) * 4);
3156 1 : pi.flags |= ATA_FLAG_EM;
3157 2 : if (!(em_ctl & EM_CTL_ALHD))
3158 1 : pi.flags |= ATA_FLAG_SW_ACTIVITY;
3159 : }
3160 : }
3161 :
3162 6 : if (ahci_broken_system_poweroff(pdev)) {
3163 1 : pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
3164 4 : dev_info(&pdev->dev,
3165 : "quirky BIOS, skipping spindown on poweroff\n");
3166 : }
3167 :
3168 8 : if (ahci_broken_suspend(pdev)) {
3169 1 : hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
3170 4 : dev_printk(KERN_WARNING, &pdev->dev,
3171 : "BIOS update required for suspend/resume\n");
3172 : }
3173 :
3174 6 : if (ahci_broken_online(pdev)) {
3175 1 : hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
3176 4 : dev_info(&pdev->dev,
3177 : "online status unreliable, applying workaround\n");
3178 : }
3179 :
3180 : /* CAP.NP sometimes indicate the index of the last enabled
3181 : * port, at other times, that of the last possible port, so
3182 : * determining the maximum port number requires looking at
3183 : * both CAP.NP and port_map.
3184 : */
3185 15 : n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
3186 :
3187 1 : host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3188 2 : if (!host)
3189 1 : return -ENOMEM;
3190 1 : host->iomap = pcim_iomap_table(pdev);
3191 1 : host->private_data = hpriv;
3192 :
3193 4 : if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
3194 1 : host->flags |= ATA_HOST_PARALLEL_SCAN;
3195 : else
3196 1 : printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
3197 :
3198 2 : if (pi.flags & ATA_FLAG_EM)
3199 3 : ahci_reset_em(host);
3200 :
3201 7 : for (i = 0; i < host->n_ports; i++) {
3202 3 : struct ata_port *ap = host->ports[i];
3203 1 :
3204 1 : ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
3205 1 : ata_port_pbar_desc(ap, AHCI_PCI_BAR,
3206 : 0x100 + ap->port_no * 0x80, "port");
3207 :
3208 : /* set initial link pm policy */
3209 1 : ap->pm_policy = NOT_AVAILABLE;
3210 :
3211 : /* set enclosure management message type */
3212 2 : if (ap->flags & ATA_FLAG_EM)
3213 1 : ap->em_message_type = ahci_em_messages;
3214 :
3215 :
3216 : /* disabled/not-implemented port */
3217 2 : if (!(hpriv->port_map & (1 << i)))
3218 1 : ap->ops = &ata_dummy_port_ops;
3219 : }
3220 :
3221 : /* apply workaround for ASUS P5W DH Deluxe mainboard */
3222 4 : ahci_p5wdh_workaround(host);
3223 :
3224 : /* apply gtf filter quirk */
3225 2 : ahci_gtf_filter_workaround(host);
3226 :
3227 : /* initialize adapter */
3228 6 : rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
3229 2 : if (rc)
3230 1 : return rc;
3231 :
3232 6 : rc = ahci_reset_controller(host);
3233 2 : if (rc)
3234 1 : return rc;
3235 :
3236 2 : ahci_init_controller(host);
3237 2 : ahci_print_info(host);
3238 :
3239 1 : pci_set_master(pdev);
3240 3 : return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
3241 : &ahci_sht);
3242 : }
3243 :
3244 : static int __init ahci_init(void)
3245 : {
3246 4 : return pci_register_driver(&ahci_pci_driver);
3247 : }
3248 :
3249 : static void __exit ahci_exit(void)
3250 : {
3251 4 : pci_unregister_driver(&ahci_pci_driver);
3252 2 : }
3253 :
3254 :
3255 : MODULE_AUTHOR("Jeff Garzik");
3256 : MODULE_DESCRIPTION("AHCI SATA low-level driver");
3257 : MODULE_LICENSE("GPL");
3258 : MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
3259 : MODULE_VERSION(DRV_VERSION);
3260 :
3261 : module_init(ahci_init);
3262 : module_exit(ahci_exit);
|