Line data Source code
1 : /*
2 : * OHCI HCD (Host Controller Driver) for USB.
3 : *
4 : * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 : * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
6 : *
7 : * [ Initialisation is based on Linus' ]
8 : * [ uhci code and gregs ohci fragments ]
9 : * [ (C) Copyright 1999 Linus Torvalds ]
10 : * [ (C) Copyright 1999 Gregory P. Smith]
11 : *
12 : *
13 : * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14 : * interfaces (though some non-x86 Intel chips use it). It supports
15 : * smarter hardware than UHCI. A download link for the spec available
16 : * through the http://www.usb.org website.
17 : *
18 : * This file is licenced under the GPL.
19 : */
20 :
21 : #include <linux/module.h>
22 : #include <linux/moduleparam.h>
23 : #include <linux/pci.h>
24 : #include <linux/kernel.h>
25 : #include <linux/delay.h>
26 : #include <linux/ioport.h>
27 : #include <linux/sched.h>
28 : #include <linux/slab.h>
29 : #include <linux/errno.h>
30 : #include <linux/init.h>
31 : #include <linux/timer.h>
32 : #include <linux/list.h>
33 : #include <linux/usb.h>
34 : #include <linux/usb/otg.h>
35 : #include <linux/dma-mapping.h>
36 : #include <linux/dmapool.h>
37 : #include <linux/workqueue.h>
38 : #include <linux/debugfs.h>
39 :
40 : #include <asm/io.h>
41 : #include <asm/irq.h>
42 : #include <asm/system.h>
43 : #include <asm/unaligned.h>
44 : #include <asm/byteorder.h>
45 :
46 : #include "../core/hcd.h"
47 :
48 : #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
49 : #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
50 :
51 : /*-------------------------------------------------------------------------*/
52 :
53 : #undef OHCI_VERBOSE_DEBUG /* not always helpful */
54 :
55 : /* For initializing controller (mask in an HCFS mode too) */
56 : #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
57 : #define OHCI_INTR_INIT \
58 : (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
59 : | OHCI_INTR_RD | OHCI_INTR_WDH)
60 :
61 : #ifdef __hppa__
62 : /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
63 : #define IR_DISABLE
64 : #endif
65 :
66 : #ifdef CONFIG_ARCH_OMAP
67 : /* OMAP doesn't support IR (no SMM; not needed) */
68 : #define IR_DISABLE
69 : #endif
70 :
71 : /*-------------------------------------------------------------------------*/
72 :
73 1 : static const char hcd_name [] = "ohci_hcd";
74 :
75 : #define STATECHANGE_DELAY msecs_to_jiffies(300)
76 :
77 : #include "ohci.h"
78 :
79 : static void ohci_dump (struct ohci_hcd *ohci, int verbose);
80 : static int ohci_init (struct ohci_hcd *ohci);
81 : static void ohci_stop (struct usb_hcd *hcd);
82 :
83 : #if defined(CONFIG_PM) || defined(CONFIG_PCI)
84 : static int ohci_restart (struct ohci_hcd *ohci);
85 : #endif
86 :
87 : #ifdef CONFIG_PCI
88 : static void quirk_amd_pll(int state);
89 : static void amd_iso_dev_put(void);
90 : static void sb800_prefetch(struct ohci_hcd *ohci, int on);
91 : #else
92 : static inline void quirk_amd_pll(int state)
93 : {
94 : return;
95 : }
96 : static inline void amd_iso_dev_put(void)
97 : {
98 : return;
99 : }
100 : static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
101 : {
102 : return;
103 : }
104 : #endif
105 :
106 :
107 : #include "ohci-hub.c"
108 : #include "ohci-dbg.c"
109 : #include "ohci-mem.c"
110 : #include "ohci-q.c"
111 :
112 :
113 : /*
114 : * On architectures with edge-triggered interrupts we must never return
115 : * IRQ_NONE.
116 : */
117 : #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
118 : #define IRQ_NOTMINE IRQ_HANDLED
119 : #else
120 : #define IRQ_NOTMINE IRQ_NONE
121 : #endif
122 :
123 :
124 : /* Some boards misreport power switching/overcurrent */
125 1 : static int distrust_firmware = 1;
126 : module_param (distrust_firmware, bool, 0);
127 : MODULE_PARM_DESC (distrust_firmware,
128 : "true to distrust firmware power/overcurrent setup");
129 :
130 : /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
131 1 : static int no_handshake = 0;
132 : module_param (no_handshake, bool, 0);
133 : MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
134 :
135 : /*-------------------------------------------------------------------------*/
136 :
137 : /*
138 : * queue up an urb for anything except the root hub
139 : */
140 : static int ohci_urb_enqueue (
141 : struct usb_hcd *hcd,
142 1 : struct urb *urb,
143 1 : gfp_t mem_flags
144 1 : ) {
145 4 : struct ohci_hcd *ohci = hcd_to_ohci (hcd);
146 1 : struct ed *ed;
147 1 : urb_priv_t *urb_priv;
148 2 : unsigned int pipe = urb->pipe;
149 2 : int i, size = 0;
150 1 : unsigned long flags;
151 2 : int retval = 0;
152 1 :
153 1 : #ifdef OHCI_VERBOSE_DEBUG
154 1 : urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
155 1 : #endif
156 1 :
157 1 : /* every endpoint has a ed, locate and maybe (re)initialize it */
158 5 : if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
159 1 : return -ENOMEM;
160 :
161 : /* for the private part of the URB we need the number of TDs (size) */
162 : switch (ed->type) {
163 4 : case PIPE_CONTROL:
164 : /* td_submit_urb() doesn't yet handle these */
165 2 : if (urb->transfer_buffer_length > 4096)
166 1 : return -EMSGSIZE;
167 :
168 : /* 1 TD for setup, 1 for ACK, plus ... */
169 1 : size = 2;
170 1 : /* FALLTHROUGH */
171 : // case PIPE_INTERRUPT:
172 : // case PIPE_BULK:
173 1 : default:
174 1 : /* one TD for every 4096 Bytes (can be upto 8K) */
175 1 : size += urb->transfer_buffer_length / 4096;
176 : /* ... and for any remaining bytes ... */
177 2 : if ((urb->transfer_buffer_length % 4096) != 0)
178 1 : size++;
179 : /* ... and maybe a zero length packet to wrap it up */
180 2 : if (size == 0)
181 1 : size++;
182 7 : else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
183 : && (urb->transfer_buffer_length
184 : % usb_maxpacket (urb->dev, pipe,
185 : usb_pipeout (pipe))) == 0)
186 1 : size++;
187 2 : break;
188 5 : case PIPE_ISOCHRONOUS: /* number of packets from URB */
189 1 : size = urb->number_of_packets;
190 1 : break;
191 : }
192 :
193 : /* allocate the private part of the URB */
194 5 : urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
195 : mem_flags);
196 2 : if (!urb_priv)
197 1 : return -ENOMEM;
198 2 : INIT_LIST_HEAD (&urb_priv->pending);
199 1 : urb_priv->length = size;
200 1 : urb_priv->ed = ed;
201 :
202 : /* allocate the TDs (deferring hash chain updates) */
203 5 : for (i = 0; i < size; i++) {
204 5 : urb_priv->td [i] = td_alloc (ohci, mem_flags);
205 3 : if (!urb_priv->td [i]) {
206 1 : urb_priv->length = i;
207 2 : urb_free_priv (ohci, urb_priv);
208 1 : return -ENOMEM;
209 : }
210 : }
211 :
212 3 : spin_lock_irqsave (&ohci->lock, flags);
213 :
214 : /* don't submit to a dead HC */
215 4 : if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
216 1 : retval = -ENODEV;
217 1 : goto fail;
218 : }
219 2 : if (!HC_IS_RUNNING(hcd->state)) {
220 1 : retval = -ENODEV;
221 1 : goto fail;
222 : }
223 1 : retval = usb_hcd_link_urb_to_ep(hcd, urb);
224 2 : if (retval)
225 1 : goto fail;
226 :
227 : /* schedule the ed if needed */
228 3 : if (ed->state == ED_IDLE) {
229 9 : retval = ed_schedule (ohci, ed);
230 2 : if (retval < 0) {
231 1 : usb_hcd_unlink_urb_from_ep(hcd, urb);
232 1 : goto fail;
233 : }
234 3 : if (ed->type == PIPE_ISOCHRONOUS) {
235 3 : u16 frame = ohci_frame_no(ohci);
236 :
237 : /* delay a few frames before the first TD */
238 8 : frame += max_t (u16, 8, ed->interval);
239 2 : frame &= ~(ed->interval - 1);
240 2 : frame |= ed->branch;
241 1 : urb->start_frame = frame;
242 :
243 : /* yes, only URB_ISO_ASAP is supported, and
244 : * urb->start_frame is never used as input.
245 : */
246 : }
247 3 : } else if (ed->type == PIPE_ISOCHRONOUS)
248 3 : urb->start_frame = ed->last_iso + ed->interval;
249 :
250 : /* fill the TDs and link them to the ed; and
251 : * enable that part of the schedule, if needed
252 : * and update count of queued periodic urbs
253 : */
254 3 : urb->hcpriv = urb_priv;
255 27 : td_submit_urb (ohci, urb);
256 :
257 1 : fail:
258 6 : if (retval)
259 6 : urb_free_priv (ohci, urb_priv);
260 8 : spin_unlock_irqrestore (&ohci->lock, flags);
261 1 : return retval;
262 : }
263 :
264 : /*
265 : * decouple the URB from the HC queues (TDs, urb_priv).
266 : * reporting is always done
267 : * asynchronously, and we might be dealing with an urb that's
268 : * partially transferred, or an ED with other urbs being unlinked.
269 : */
270 : static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
271 : {
272 4 : struct ohci_hcd *ohci = hcd_to_ohci (hcd);
273 1 : unsigned long flags;
274 1 : int rc;
275 1 :
276 1 : #ifdef OHCI_VERBOSE_DEBUG
277 1 : urb_print(urb, "UNLINK", 1, status);
278 : #endif
279 :
280 3 : spin_lock_irqsave (&ohci->lock, flags);
281 1 : rc = usb_hcd_check_unlink_urb(hcd, urb, status);
282 2 : if (rc) {
283 : ; /* Do nothing */
284 2 : } else if (HC_IS_RUNNING(hcd->state)) {
285 : urb_priv_t *urb_priv;
286 :
287 : /* Unless an IRQ completed the unlink while it was being
288 : * handed to us, flag it for unlink and giveback, and force
289 : * some upcoming INTR_SF to call finish_unlinks()
290 : */
291 2 : urb_priv = urb->hcpriv;
292 2 : if (urb_priv) {
293 3 : if (urb_priv->ed->state == ED_OPER)
294 2 : start_ed_unlink (ohci, urb_priv->ed);
295 : }
296 : } else {
297 : /*
298 : * with HC dead, we won't respect hc queue pointers
299 : * any more ... just clean up every urb's memory.
300 : */
301 3 : if (urb->hcpriv)
302 4 : finish_urb(ohci, urb, status);
303 : }
304 6 : spin_unlock_irqrestore (&ohci->lock, flags);
305 1 : return rc;
306 : }
307 :
308 : /*-------------------------------------------------------------------------*/
309 :
310 : /* frees config/altsetting state for endpoints,
311 : * including ED memory, dummy TD, and bulk/intr data toggle
312 : */
313 :
314 : static void
315 : ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
316 : {
317 4 : struct ohci_hcd *ohci = hcd_to_ohci (hcd);
318 1 : unsigned long flags;
319 3 : struct ed *ed = ep->hcpriv;
320 2 : unsigned limit = 1000;
321 1 :
322 1 : /* ASSERT: any requests/urbs are being unlinked */
323 1 : /* ASSERT: nobody can be submitting urbs for this any more */
324 1 :
325 3 : if (!ed)
326 2 : return;
327 1 :
328 1 : rescan:
329 4 : spin_lock_irqsave (&ohci->lock, flags);
330 2 :
331 3 : if (!HC_IS_RUNNING (hcd->state)) {
332 2 : sanitize:
333 4 : ed->state = ED_IDLE;
334 12 : if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
335 2 : ohci->eds_scheduled--;
336 10 : finish_unlinks (ohci, 0);
337 1 : }
338 1 :
339 1 : switch (ed->state) {
340 4 : case ED_UNLINK: /* wait for hw to finish? */
341 : /* major IRQ delivery trouble loses INTR_SF too... */
342 4 : if (limit-- == 0) {
343 8 : ohci_warn(ohci, "ED unlink timeout\n");
344 4 : if (quirk_zfmicro(ohci)) {
345 8 : ohci_warn(ohci, "Attempting ZF TD recovery\n");
346 1 : ohci->ed_to_check = ed;
347 1 : ohci->zf_delay = 2;
348 : }
349 2 : goto sanitize;
350 : }
351 2 : spin_unlock_irqrestore (&ohci->lock, flags);
352 1 : schedule_timeout_uninterruptible(1);
353 1 : goto rescan;
354 5 : case ED_IDLE: /* fully unlinked */
355 4 : if (list_empty (&ed->td_list)) {
356 3 : td_free (ohci, ed->dummy);
357 2 : ed_free (ohci, ed);
358 1 : break;
359 : }
360 : /* else FALL THROUGH */
361 1 : default:
362 2 : /* caller was supposed to have unlinked any requests;
363 : * that's not our job. can't recover; must leak ed.
364 : */
365 14 : ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
366 4 : ed, ep->desc.bEndpointAddress, ed->state,
367 : list_empty (&ed->td_list) ? "" : " (has tds)");
368 3 : td_free (ohci, ed->dummy);
369 1 : break;
370 : }
371 2 : ep->hcpriv = NULL;
372 4 : spin_unlock_irqrestore (&ohci->lock, flags);
373 1 : return;
374 : }
375 :
376 : static int ohci_get_frame (struct usb_hcd *hcd)
377 : {
378 4 : struct ohci_hcd *ohci = hcd_to_ohci (hcd);
379 1 :
380 4 : return ohci_frame_no(ohci);
381 : }
382 :
383 : static void ohci_usb_reset (struct ohci_hcd *ohci)
384 : {
385 12 : ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
386 6 : ohci->hc_control &= OHCI_CTRL_RWC;
387 12 : ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
388 6 : }
389 :
390 : /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
391 : * other cases where the next software may expect clean state from the
392 : * "firmware". this is bus-neutral, unlike shutdown() methods.
393 : */
394 : static void
395 : ohci_shutdown (struct usb_hcd *hcd)
396 : {
397 1 : struct ohci_hcd *ohci;
398 :
399 2 : ohci = hcd_to_ohci (hcd);
400 2 : ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
401 2 : ohci_usb_reset (ohci);
402 : /* flush the writes */
403 2 : (void) ohci_readl (ohci, &ohci->regs->control);
404 1 : }
405 :
406 : static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
407 : {
408 22 : return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
409 1 : && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
410 1 : == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
411 1 : && !list_empty(&ed->td_list);
412 1 : }
413 :
414 : /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
415 : * an interrupt TD but neglects to add it to the donelist. On systems with
416 : * this chipset, we need to periodically check the state of the queues to look
417 : * for such "lost" TDs.
418 : */
419 : static void unlink_watchdog_func(unsigned long _ohci)
420 : {
421 0 : unsigned long flags;
422 0 : unsigned max;
423 0 : unsigned seen_count = 0;
424 0 : unsigned i;
425 0 : struct ed **seen = NULL;
426 0 : struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
427 0 :
428 0 : spin_lock_irqsave(&ohci->lock, flags);
429 0 : max = ohci->eds_scheduled;
430 0 : if (!max)
431 0 : goto done;
432 0 :
433 0 : if (ohci->ed_to_check)
434 0 : goto out;
435 :
436 0 : seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
437 0 : if (!seen)
438 0 : goto out;
439 :
440 0 : for (i = 0; i < NUM_INTS; i++) {
441 0 : struct ed *ed = ohci->periodic[i];
442 0 :
443 0 : while (ed) {
444 0 : unsigned temp;
445 0 :
446 : /* scan this branch of the periodic schedule tree */
447 0 : for (temp = 0; temp < seen_count; temp++) {
448 0 : if (seen[temp] == ed) {
449 0 : /* we've checked it and what's after */
450 0 : ed = NULL;
451 0 : break;
452 : }
453 0 : }
454 0 : if (!ed)
455 0 : break;
456 0 : seen[seen_count++] = ed;
457 0 : if (!check_ed(ohci, ed)) {
458 0 : ed = ed->ed_next;
459 0 : continue;
460 : }
461 :
462 : /* HC's TD list is empty, but HCD sees at least one
463 : * TD that's not been sent through the donelist.
464 : */
465 0 : ohci->ed_to_check = ed;
466 0 : ohci->zf_delay = 2;
467 :
468 : /* The HC may wait until the next frame to report the
469 : * TD as done through the donelist and INTR_WDH. (We
470 : * just *assume* it's not a multi-TD interrupt URB;
471 : * those could defer the IRQ more than one frame, using
472 : * DI...) Check again after the next INTR_SF.
473 : */
474 0 : ohci_writel(ohci, OHCI_INTR_SF,
475 : &ohci->regs->intrstatus);
476 0 : ohci_writel(ohci, OHCI_INTR_SF,
477 : &ohci->regs->intrenable);
478 :
479 : /* flush those writes */
480 0 : (void) ohci_readl(ohci, &ohci->regs->control);
481 :
482 0 : goto out;
483 0 : }
484 : }
485 : out:
486 0 : kfree(seen);
487 0 : if (ohci->eds_scheduled)
488 0 : mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
489 : done:
490 0 : spin_unlock_irqrestore(&ohci->lock, flags);
491 0 : }
492 :
493 0 : /*-------------------------------------------------------------------------*
494 : * HC functions
495 : *-------------------------------------------------------------------------*/
496 :
497 : /* init memory, and kick BIOS/SMM off */
498 :
499 : static int ohci_init (struct ohci_hcd *ohci)
500 : {
501 1 : int ret;
502 4 : struct usb_hcd *hcd = ohci_to_hcd(ohci);
503 1 :
504 3 : if (distrust_firmware)
505 2 : ohci->flags |= OHCI_QUIRK_HUB_POWER;
506 1 :
507 3 : disable (ohci);
508 3 : ohci->regs = hcd->regs;
509 1 :
510 1 : /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
511 1 : * was never needed for most non-PCI systems ... remove the code?
512 1 : */
513 1 :
514 : #ifndef IR_DISABLE
515 : /* SMM owns the HC? not for long! */
516 6 : if (!no_handshake && ohci_readl (ohci,
517 : &ohci->regs->control) & OHCI_CTRL_IR) {
518 : u32 temp;
519 :
520 : ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
521 :
522 : /* this timeout is arbitrary. we make it long, so systems
523 : * depending on usb keyboards may be usable even if the
524 : * BIOS/SMM code seems pretty broken.
525 : */
526 1 : temp = 500; /* arbitrary: five seconds */
527 :
528 2 : ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
529 2 : ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
530 5 : while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
531 2 : msleep (10);
532 4 : if (--temp == 0) {
533 8 : ohci_err (ohci, "USB HC takeover failed!"
534 : " (BIOS/SMM bug)\n");
535 1 : return -EBUSY;
536 : }
537 : }
538 2 : ohci_usb_reset (ohci);
539 1 : }
540 : #endif
541 :
542 : /* Disable HC interrupts */
543 6 : ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
544 :
545 : /* flush the writes, and save key bits like RWC */
546 4 : if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
547 1 : ohci->hc_control |= OHCI_CTRL_RWC;
548 :
549 : /* Read the number of ports unless overridden */
550 2 : if (ohci->num_ports == 0)
551 5 : ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
552 :
553 6 : if (ohci->hcca)
554 2 : return 0;
555 :
556 7 : ohci->hcca = dma_alloc_coherent (hcd->self.controller,
557 : sizeof *ohci->hcca, &ohci->hcca_dma, 0);
558 3 : if (!ohci->hcca)
559 1 : return -ENOMEM;
560 :
561 5 : if ((ret = ohci_mem_init (ohci)) < 0)
562 3 : ohci_stop (hcd);
563 : else {
564 2 : create_debug_files (ohci);
565 : }
566 :
567 2 : return ret;
568 : }
569 :
570 : /*-------------------------------------------------------------------------*/
571 :
572 : /* Start an OHCI controller, set the BUS operational
573 : * resets USB and controller
574 : * enable interrupts
575 : */
576 : static int ohci_run (struct ohci_hcd *ohci)
577 : {
578 1 : u32 mask, val;
579 2 : int first = ohci->fminterval == 0;
580 4 : struct usb_hcd *hcd = ohci_to_hcd(ohci);
581 1 :
582 3 : disable (ohci);
583 1 :
584 1 : /* boot firmware should have set this up (5.1.1.3.1) */
585 3 : if (first) {
586 1 :
587 3 : val = ohci_readl (ohci, &ohci->regs->fminterval);
588 2 : ohci->fminterval = val & 0x3fff;
589 1 : if (ohci->fminterval != FI)
590 1 : ohci_dbg (ohci, "fminterval delta %d\n",
591 1 : ohci->fminterval - FI);
592 2 : ohci->fminterval |= FSMP (ohci->fminterval) << 16;
593 1 : /* also: power/overcurrent flags in roothub.a */
594 1 : }
595 1 :
596 1 : /* Reset USB nearly "by the book". RemoteWakeupConnected has
597 1 : * to be checked in case boot firmware (BIOS/SMM/...) has set up
598 1 : * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
599 1 : * If the bus glue detected wakeup capability then it should
600 : * already be enabled; if so we'll just enable it again.
601 : */
602 4 : if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
603 4 : device_set_wakeup_capable(hcd->self.controller, 1);
604 :
605 : switch (ohci->hc_control & OHCI_CTRL_HCFS) {
606 9 : case OHCI_USB_OPER:
607 3 : val = 0;
608 3 : break;
609 12 : case OHCI_USB_SUSPEND:
610 12 : case OHCI_USB_RESUME:
611 3 : ohci->hc_control &= OHCI_CTRL_RWC;
612 3 : ohci->hc_control |= OHCI_USB_RESUME;
613 3 : val = 10 /* msec wait */;
614 3 : break;
615 3 : // case OHCI_USB_RESET:
616 3 : default:
617 6 : ohci->hc_control &= OHCI_CTRL_RWC;
618 3 : ohci->hc_control |= OHCI_USB_RESET;
619 3 : val = 50 /* msec wait */;
620 3 : break;
621 : }
622 6 : ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
623 : // flush the writes
624 2 : (void) ohci_readl (ohci, &ohci->regs->control);
625 1 : msleep(val);
626 :
627 2 : memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
628 :
629 : /* 2msec timelimit here means no irqs/preempt */
630 2 : spin_lock_irq (&ohci->lock);
631 :
632 1 : retry:
633 : /* HC Reset requires max 10 us delay */
634 2 : ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
635 1 : val = 30; /* ... allow extra time */
636 5 : while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
637 4 : if (--val == 0) {
638 3 : spin_unlock_irq (&ohci->lock);
639 8 : ohci_err (ohci, "USB HC reset timed out!\n");
640 1 : return -1;
641 : }
642 1 : udelay (1);
643 : }
644 1 :
645 : /* now we're in the SUSPEND state ... must go OPERATIONAL
646 : * within 2msec else HC enters RESUME
647 : *
648 : * ... but some hardware won't init fmInterval "by the book"
649 : * (SiS, OPTi ...), so reset again instead. SiS doesn't need
650 : * this if we write fmInterval after we're OPERATIONAL.
651 : * Unclear about ALi, ServerWorks, and others ... this could
652 : * easily be a longstanding bug in chip init on Linux.
653 : */
654 2 : if (ohci->flags & OHCI_QUIRK_INITRESET) {
655 2 : ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
656 : // flush those writes
657 2 : (void) ohci_readl (ohci, &ohci->regs->control);
658 : }
659 :
660 : /* Tell the controller where the control and bulk lists are
661 : * The lists are empty now. */
662 4 : ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
663 2 : ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
664 :
665 : /* a reset clears this */
666 3 : ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
667 :
668 2 : periodic_reinit (ohci);
669 :
670 : /* some OHCI implementations are finicky about how they init.
671 : * bogus values here mean not even enumeration could work.
672 : */
673 9 : if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
674 1 : || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
675 4 : if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
676 2 : ohci->flags |= OHCI_QUIRK_INITRESET;
677 : ohci_dbg (ohci, "enabling initreset quirk\n");
678 2 : goto retry;
679 : }
680 4 : spin_unlock_irq (&ohci->lock);
681 12 : ohci_err (ohci, "init err (%08x %04x)\n",
682 : ohci_readl (ohci, &ohci->regs->fminterval),
683 : ohci_readl (ohci, &ohci->regs->periodicstart));
684 1 : return -EOVERFLOW;
685 : }
686 :
687 : /* use rhsc irqs after khubd is fully initialized */
688 1 : hcd->poll_rh = 1;
689 1 : hcd->uses_new_polling = 1;
690 :
691 : /* start controller operations */
692 1 : ohci->hc_control &= OHCI_CTRL_RWC;
693 1 : ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
694 2 : ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
695 1 : hcd->state = HC_STATE_RUNNING;
696 :
697 : /* wake on ConnectStatusChange, matching external hubs */
698 2 : ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
699 :
700 : /* Choose the interrupts we care about now, others later on demand */
701 1 : mask = OHCI_INTR_INIT;
702 2 : ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
703 2 : ohci_writel (ohci, mask, &ohci->regs->intrenable);
704 :
705 : /* handle root hub init quirks ... */
706 4 : val = roothub_a (ohci);
707 1 : val &= ~(RH_A_PSM | RH_A_OCPM);
708 2 : if (ohci->flags & OHCI_QUIRK_SUPERIO) {
709 : /* NSC 87560 and maybe others */
710 1 : val |= RH_A_NOCP;
711 1 : val &= ~(RH_A_POTPGT | RH_A_NPS);
712 2 : ohci_writel (ohci, val, &ohci->regs->roothub.a);
713 5 : } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
714 : (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
715 : /* hub power always on; required for AMD-756 and some
716 : * Mac platforms. ganged overcurrent reporting, if any.
717 : */
718 1 : val |= RH_A_NPS;
719 2 : ohci_writel (ohci, val, &ohci->regs->roothub.a);
720 : }
721 6 : ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
722 7 : ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
723 : &ohci->regs->roothub.b);
724 : // flush those writes
725 2 : (void) ohci_readl (ohci, &ohci->regs->control);
726 :
727 2 : ohci->next_statechange = jiffies + STATECHANGE_DELAY;
728 2 : spin_unlock_irq (&ohci->lock);
729 :
730 : // POTPGT delay is bits 24-31, in 2 ms units.
731 7 : mdelay ((val >> 23) & 0x1fe);
732 2 : hcd->state = HC_STATE_RUNNING;
733 2 :
734 4 : if (quirk_zfmicro(ohci)) {
735 : /* Create timer to watch for bad queue state on ZF Micro */
736 2 : setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
737 : (unsigned long) ohci);
738 :
739 1 : ohci->eds_scheduled = 0;
740 1 : ohci->ed_to_check = NULL;
741 : }
742 :
743 4 : ohci_dump (ohci, 1);
744 :
745 1 : return 0;
746 : }
747 :
748 : /*-------------------------------------------------------------------------*/
749 :
750 : /* an interrupt happens */
751 :
752 : static irqreturn_t ohci_irq (struct usb_hcd *hcd)
753 : {
754 4 : struct ohci_hcd *ohci = hcd_to_ohci (hcd);
755 2 : struct ohci_regs __iomem *regs = ohci->regs;
756 1 : int ints;
757 1 :
758 1 : /* Read interrupt status (and flush pending writes). We ignore the
759 1 : * optimization of checking the LSB of hcca->done_head; it doesn't
760 1 : * work on all systems (edge triggering for OHCI can be a factor).
761 1 : */
762 4 : ints = ohci_readl(ohci, ®s->intrstatus);
763 1 :
764 1 : /* Check for an all 1's result which is a typical consequence
765 1 : * of dead, unclocked, or unplugged (CardBus...) devices
766 1 : */
767 3 : if (ints == ~(u32)0) {
768 3 : disable (ohci);
769 1 : ohci_dbg (ohci, "device removed!\n");
770 2 : return IRQ_HANDLED;
771 1 : }
772 1 :
773 1 : /* We only care about interrupts that are enabled */
774 4 : ints &= ohci_readl(ohci, ®s->intrenable);
775 1 :
776 1 : /* interrupt for some other device? */
777 3 : if (ints == 0)
778 2 : return IRQ_NOTMINE;
779 1 :
780 2 : if (ints & OHCI_INTR_UE) {
781 : // e.g. due to PCI Master/Target Abort
782 4 : if (quirk_nec(ohci)) {
783 : /* Workaround for a silicon bug in some NEC chips used
784 : * in Apple's PowerBooks. Adapted from Darwin code.
785 : */
786 8 : ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
787 :
788 2 : ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
789 :
790 1 : schedule_work (&ohci->nec_work);
791 : } else {
792 2 : disable (ohci);
793 8 : ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
794 : }
795 :
796 4 : ohci_dump (ohci, 1);
797 2 : ohci_usb_reset (ohci);
798 : }
799 :
800 4 : if (ints & OHCI_INTR_RHSC) {
801 : ohci_vdbg(ohci, "rhsc\n");
802 4 : ohci->next_statechange = jiffies + STATECHANGE_DELAY;
803 4 : ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
804 : ®s->intrstatus);
805 :
806 : /* NOTE: Vendors didn't always make the same implementation
807 : * choices for RHSC. Many followed the spec; RHSC triggers
808 : * on an edge, like setting and maybe clearing a port status
809 : * change bit. With others it's level-triggered, active
810 : * until khubd clears all the port status change bits. We'll
811 : * always disable it here and rely on polling until khubd
812 : * re-enables it.
813 : */
814 2 : ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
815 1 : usb_hcd_poll_rh_status(hcd);
816 : }
817 :
818 : /* For connect and disconnect events, we expect the controller
819 : * to turn on RHSC along with RD. But for remote wakeup events
820 : * this might not happen.
821 : */
822 4 : else if (ints & OHCI_INTR_RD) {
823 : ohci_vdbg(ohci, "resume detect\n");
824 4 : ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
825 1 : hcd->poll_rh = 1;
826 2 : if (ohci->autostop) {
827 2 : spin_lock (&ohci->lock);
828 2 : ohci_rh_resume (ohci);
829 2 : spin_unlock (&ohci->lock);
830 : } else
831 2 : usb_hcd_resume_root_hub(hcd);
832 : }
833 :
834 10 : if (ints & OHCI_INTR_WDH) {
835 10 : spin_lock (&ohci->lock);
836 2 : dl_done_list (ohci);
837 2 : spin_unlock (&ohci->lock);
838 : }
839 :
840 16 : if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
841 2 : spin_lock(&ohci->lock);
842 3 : if (ohci->ed_to_check) {
843 1 : struct ed *ed = ohci->ed_to_check;
844 :
845 6 : if (check_ed(ohci, ed)) {
846 : /* HC thinks the TD list is empty; HCD knows
847 : * at least one TD is outstanding
848 : */
849 3 : if (--ohci->zf_delay == 0) {
850 2 : struct td *td = list_entry(
851 : ed->td_list.next,
852 : struct td, td_list);
853 8 : ohci_warn(ohci,
854 : "Reclaiming orphan TD %p\n",
855 : td);
856 8 : takeback_td(ohci, td);
857 1 : ohci->ed_to_check = NULL;
858 : }
859 : } else
860 1 : ohci->ed_to_check = NULL;
861 : }
862 6 : spin_unlock(&ohci->lock);
863 : }
864 :
865 : /* could track INTR_SO to reduce available PCI/... bandwidth */
866 :
867 : /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
868 : * when there's still unlinking to be done (next frame).
869 : */
870 4 : spin_lock (&ohci->lock);
871 3 : if (ohci->ed_rm_list)
872 11 : finish_unlinks (ohci, ohci_frame_no(ohci));
873 20 : if ((ints & OHCI_INTR_SF) != 0
874 : && !ohci->ed_rm_list
875 : && !ohci->ed_to_check
876 : && HC_IS_RUNNING(hcd->state))
877 4 : ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
878 6 : spin_unlock (&ohci->lock);
879 :
880 2 : if (HC_IS_RUNNING(hcd->state)) {
881 2 : ohci_writel (ohci, ints, ®s->intrstatus);
882 2 : ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
883 : // flush those writes
884 2 : (void) ohci_readl (ohci, &ohci->regs->control);
885 : }
886 :
887 2 : return IRQ_HANDLED;
888 : }
889 :
890 : /*-------------------------------------------------------------------------*/
891 :
892 : static void ohci_stop (struct usb_hcd *hcd)
893 : {
894 12 : struct ohci_hcd *ohci = hcd_to_ohci (hcd);
895 3 :
896 9 : ohci_dump (ohci, 1);
897 3 :
898 3 : flush_scheduled_work();
899 :
900 6 : ohci_usb_reset (ohci);
901 6 : ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
902 9 : free_irq(hcd->irq, hcd);
903 3 : hcd->irq = -1;
904 :
905 12 : if (quirk_zfmicro(ohci))
906 6 : del_timer(&ohci->unlink_watchdog);
907 18 : if (quirk_amdiso(ohci))
908 6 : amd_iso_dev_put();
909 :
910 12 : remove_debug_files (ohci);
911 6 : ohci_mem_cleanup (ohci);
912 9 : if (ohci->hcca) {
913 9 : dma_free_coherent (hcd->self.controller,
914 : sizeof *ohci->hcca,
915 : ohci->hcca, ohci->hcca_dma);
916 3 : ohci->hcca = NULL;
917 3 : ohci->hcca_dma = 0;
918 : }
919 6 : }
920 :
921 : /*-------------------------------------------------------------------------*/
922 :
923 : #if defined(CONFIG_PM) || defined(CONFIG_PCI)
924 :
925 : /* must not be called from interrupt context */
926 : static int ohci_restart (struct ohci_hcd *ohci)
927 : {
928 0 : int temp;
929 0 : int i;
930 0 : struct urb_priv *priv;
931 0 :
932 0 : spin_lock_irq(&ohci->lock);
933 0 : disable (ohci);
934 0 :
935 0 : /* Recycle any "live" eds/tds (and urbs). */
936 0 : if (!list_empty (&ohci->pending))
937 0 : ohci_dbg(ohci, "abort schedule...\n");
938 0 : list_for_each_entry (priv, &ohci->pending, pending) {
939 0 : struct urb *urb = priv->td[0]->urb;
940 0 : struct ed *ed = priv->ed;
941 :
942 : switch (ed->state) {
943 0 : case ED_OPER:
944 0 : ed->state = ED_UNLINK;
945 0 : ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
946 0 : ed_deschedule (ohci, ed);
947 :
948 0 : ed->ed_next = ohci->ed_rm_list;
949 0 : ed->ed_prev = NULL;
950 0 : ohci->ed_rm_list = ed;
951 : /* FALLTHROUGH */
952 0 : case ED_UNLINK:
953 0 : break;
954 0 : default:
955 0 : ohci_dbg(ohci, "bogus ed %p state %d\n",
956 : ed, ed->state);
957 0 : }
958 :
959 0 : if (!urb->unlinked)
960 0 : urb->unlinked = -ESHUTDOWN;
961 : }
962 0 : finish_unlinks (ohci, 0);
963 0 : spin_unlock_irq(&ohci->lock);
964 :
965 : /* paranoia, in case that didn't work: */
966 :
967 : /* empty the interrupt branches */
968 0 : for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
969 0 : for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
970 0 :
971 0 : /* no EDs to remove */
972 0 : ohci->ed_rm_list = NULL;
973 :
974 : /* empty control and bulk lists */
975 0 : ohci->ed_controltail = NULL;
976 0 : ohci->ed_bulktail = NULL;
977 :
978 0 : if ((temp = ohci_run (ohci)) < 0) {
979 0 : ohci_err (ohci, "can't restart, %d\n", temp);
980 0 : return temp;
981 : }
982 : ohci_dbg(ohci, "restart complete\n");
983 0 : return 0;
984 : }
985 :
986 : #endif
987 :
988 : /*-------------------------------------------------------------------------*/
989 :
990 : MODULE_AUTHOR (DRIVER_AUTHOR);
991 : MODULE_DESCRIPTION(DRIVER_DESC);
992 : MODULE_LICENSE ("GPL");
993 :
994 : #ifdef CONFIG_PCI
995 : #include "ohci-pci.c"
996 : #define PCI_DRIVER ohci_pci_driver
997 : #endif
998 :
999 : #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1000 : #include "ohci-sa1111.c"
1001 : #define SA1111_DRIVER ohci_hcd_sa1111_driver
1002 : #endif
1003 :
1004 : #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX)
1005 : #include "ohci-s3c2410.c"
1006 : #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1007 : #endif
1008 :
1009 : #ifdef CONFIG_ARCH_OMAP
1010 : #include "ohci-omap.c"
1011 : #define PLATFORM_DRIVER ohci_hcd_omap_driver
1012 : #endif
1013 :
1014 : #ifdef CONFIG_ARCH_LH7A404
1015 : #include "ohci-lh7a404.c"
1016 : #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver
1017 : #endif
1018 :
1019 : #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1020 : #include "ohci-pxa27x.c"
1021 : #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1022 : #endif
1023 :
1024 : #ifdef CONFIG_ARCH_EP93XX
1025 : #include "ohci-ep93xx.c"
1026 : #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1027 : #endif
1028 :
1029 : #ifdef CONFIG_SOC_AU1X00
1030 : #include "ohci-au1xxx.c"
1031 : #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver
1032 : #endif
1033 :
1034 : #ifdef CONFIG_PNX8550
1035 : #include "ohci-pnx8550.c"
1036 : #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver
1037 : #endif
1038 :
1039 : #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
1040 : #include "ohci-ppc-soc.c"
1041 : #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver
1042 : #endif
1043 :
1044 : #ifdef CONFIG_ARCH_AT91
1045 : #include "ohci-at91.c"
1046 : #define PLATFORM_DRIVER ohci_hcd_at91_driver
1047 : #endif
1048 :
1049 : #ifdef CONFIG_ARCH_PNX4008
1050 : #include "ohci-pnx4008.c"
1051 : #define PLATFORM_DRIVER usb_hcd_pnx4008_driver
1052 : #endif
1053 :
1054 : #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
1055 : defined(CONFIG_CPU_SUBTYPE_SH7721) || \
1056 : defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1057 : defined(CONFIG_CPU_SUBTYPE_SH7786)
1058 : #include "ohci-sh.c"
1059 : #define PLATFORM_DRIVER ohci_hcd_sh_driver
1060 : #endif
1061 :
1062 :
1063 : #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1064 : #include "ohci-ppc-of.c"
1065 : #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1066 : #endif
1067 :
1068 : #ifdef CONFIG_PPC_PS3
1069 : #include "ohci-ps3.c"
1070 : #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1071 : #endif
1072 :
1073 : #ifdef CONFIG_USB_OHCI_HCD_SSB
1074 : #include "ohci-ssb.c"
1075 : #define SSB_OHCI_DRIVER ssb_ohci_driver
1076 : #endif
1077 :
1078 : #ifdef CONFIG_MFD_SM501
1079 : #include "ohci-sm501.c"
1080 : #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1081 : #endif
1082 :
1083 : #ifdef CONFIG_MFD_TC6393XB
1084 : #include "ohci-tmio.c"
1085 : #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1086 : #endif
1087 :
1088 : #if !defined(PCI_DRIVER) && \
1089 : !defined(PLATFORM_DRIVER) && \
1090 : !defined(OF_PLATFORM_DRIVER) && \
1091 : !defined(SA1111_DRIVER) && \
1092 : !defined(PS3_SYSTEM_BUS_DRIVER) && \
1093 : !defined(SM501_OHCI_DRIVER) && \
1094 : !defined(TMIO_OHCI_DRIVER) && \
1095 : !defined(SSB_OHCI_DRIVER)
1096 : #error "missing bus glue for ohci-hcd"
1097 : #endif
1098 :
1099 : static int __init ohci_hcd_mod_init(void)
1100 : {
1101 2 : int retval = 0;
1102 1 :
1103 3 : if (usb_disabled())
1104 1 : return -ENODEV;
1105 :
1106 1 : printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1107 : pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1108 : sizeof (struct ed), sizeof (struct td));
1109 2 : set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1110 :
1111 : #ifdef DEBUG
1112 : ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1113 : if (!ohci_debug_root) {
1114 : retval = -ENOENT;
1115 : goto error_debug;
1116 : }
1117 : #endif
1118 :
1119 : #ifdef PS3_SYSTEM_BUS_DRIVER
1120 : retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1121 : if (retval < 0)
1122 : goto error_ps3;
1123 : #endif
1124 :
1125 : #ifdef PLATFORM_DRIVER
1126 : retval = platform_driver_register(&PLATFORM_DRIVER);
1127 : if (retval < 0)
1128 : goto error_platform;
1129 : #endif
1130 :
1131 : #ifdef OF_PLATFORM_DRIVER
1132 : retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
1133 : if (retval < 0)
1134 : goto error_of_platform;
1135 : #endif
1136 :
1137 : #ifdef SA1111_DRIVER
1138 : retval = sa1111_driver_register(&SA1111_DRIVER);
1139 : if (retval < 0)
1140 : goto error_sa1111;
1141 : #endif
1142 :
1143 : #ifdef PCI_DRIVER
1144 2 : retval = pci_register_driver(&PCI_DRIVER);
1145 2 : if (retval < 0)
1146 1 : goto error_pci;
1147 : #endif
1148 :
1149 : #ifdef SSB_OHCI_DRIVER
1150 : retval = ssb_driver_register(&SSB_OHCI_DRIVER);
1151 : if (retval)
1152 : goto error_ssb;
1153 : #endif
1154 :
1155 : #ifdef SM501_OHCI_DRIVER
1156 : retval = platform_driver_register(&SM501_OHCI_DRIVER);
1157 : if (retval < 0)
1158 : goto error_sm501;
1159 : #endif
1160 :
1161 : #ifdef TMIO_OHCI_DRIVER
1162 : retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1163 : if (retval < 0)
1164 : goto error_tmio;
1165 : #endif
1166 :
1167 1 : return retval;
1168 :
1169 : /* Error path */
1170 : #ifdef TMIO_OHCI_DRIVER
1171 : platform_driver_unregister(&TMIO_OHCI_DRIVER);
1172 : error_tmio:
1173 : #endif
1174 : #ifdef SM501_OHCI_DRIVER
1175 : platform_driver_unregister(&SM501_OHCI_DRIVER);
1176 : error_sm501:
1177 : #endif
1178 : #ifdef SSB_OHCI_DRIVER
1179 : ssb_driver_unregister(&SSB_OHCI_DRIVER);
1180 : error_ssb:
1181 : #endif
1182 : #ifdef PCI_DRIVER
1183 : pci_unregister_driver(&PCI_DRIVER);
1184 : error_pci:
1185 1 : #endif
1186 : #ifdef SA1111_DRIVER
1187 : sa1111_driver_unregister(&SA1111_DRIVER);
1188 : error_sa1111:
1189 : #endif
1190 : #ifdef OF_PLATFORM_DRIVER
1191 : of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1192 : error_of_platform:
1193 : #endif
1194 : #ifdef PLATFORM_DRIVER
1195 : platform_driver_unregister(&PLATFORM_DRIVER);
1196 : error_platform:
1197 : #endif
1198 : #ifdef PS3_SYSTEM_BUS_DRIVER
1199 : ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1200 : error_ps3:
1201 : #endif
1202 : #ifdef DEBUG
1203 : debugfs_remove(ohci_debug_root);
1204 : ohci_debug_root = NULL;
1205 : error_debug:
1206 : #endif
1207 :
1208 2 : clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1209 1 : return retval;
1210 : }
1211 : module_init(ohci_hcd_mod_init);
1212 :
1213 : static void __exit ohci_hcd_mod_exit(void)
1214 : {
1215 : #ifdef TMIO_OHCI_DRIVER
1216 : platform_driver_unregister(&TMIO_OHCI_DRIVER);
1217 : #endif
1218 : #ifdef SM501_OHCI_DRIVER
1219 : platform_driver_unregister(&SM501_OHCI_DRIVER);
1220 : #endif
1221 : #ifdef SSB_OHCI_DRIVER
1222 : ssb_driver_unregister(&SSB_OHCI_DRIVER);
1223 : #endif
1224 : #ifdef PCI_DRIVER
1225 4 : pci_unregister_driver(&PCI_DRIVER);
1226 : #endif
1227 : #ifdef SA1111_DRIVER
1228 : sa1111_driver_unregister(&SA1111_DRIVER);
1229 : #endif
1230 : #ifdef OF_PLATFORM_DRIVER
1231 : of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1232 : #endif
1233 : #ifdef PLATFORM_DRIVER
1234 : platform_driver_unregister(&PLATFORM_DRIVER);
1235 : #endif
1236 : #ifdef PS3_SYSTEM_BUS_DRIVER
1237 : ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1238 : #endif
1239 : #ifdef DEBUG
1240 : debugfs_remove(ohci_debug_root);
1241 : #endif
1242 4 : clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1243 2 : }
1244 : module_exit(ohci_hcd_mod_exit);
1245 1 :
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