Line data Source code
1 : /*
2 : * xHCI host controller driver
3 : *
4 : * Copyright (C) 2008 Intel Corp.
5 : *
6 : * Author: Sarah Sharp
7 : * Some code borrowed from the Linux EHCI driver.
8 : *
9 : * This program is free software; you can redistribute it and/or modify
10 : * it under the terms of the GNU General Public License version 2 as
11 : * published by the Free Software Foundation.
12 : *
13 : * This program is distributed in the hope that it will be useful, but
14 : * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 : * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 : * for more details.
17 : *
18 : * You should have received a copy of the GNU General Public License
19 : * along with this program; if not, write to the Free Software Foundation,
20 : * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 : */
22 :
23 : #include "xhci.h"
24 :
25 : #define XHCI_INIT_VALUE 0x0
26 :
27 : /* Add verbose debugging later, just print everything for now */
28 :
29 : void xhci_dbg_regs(struct xhci_hcd *xhci)
30 : {
31 1 : u32 temp;
32 :
33 : xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
34 : xhci->cap_regs);
35 2 : temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
36 : xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
37 : &xhci->cap_regs->hc_capbase, temp);
38 : xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n",
39 : (unsigned int) HC_LENGTH(temp));
40 : #if 0
41 : xhci_dbg(xhci, "// HCIVERSION: 0x%x\n",
42 : (unsigned int) HC_VERSION(temp));
43 : #endif
44 :
45 : xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);
46 :
47 2 : temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
48 : xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
49 : &xhci->cap_regs->run_regs_off,
50 : (unsigned int) temp & RTSOFF_MASK);
51 : xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);
52 :
53 2 : temp = xhci_readl(xhci, &xhci->cap_regs->db_off);
54 : xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
55 : xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
56 : }
57 1 :
58 : static void xhci_print_cap_regs(struct xhci_hcd *xhci)
59 : {
60 1 : u32 temp;
61 :
62 : xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);
63 :
64 2 : temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
65 : xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
66 : (unsigned int) temp);
67 : xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
68 : (unsigned int) HC_LENGTH(temp));
69 : xhci_dbg(xhci, "HCIVERSION: 0x%x\n",
70 : (unsigned int) HC_VERSION(temp));
71 :
72 2 : temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
73 : xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
74 : (unsigned int) temp);
75 : xhci_dbg(xhci, " Max device slots: %u\n",
76 : (unsigned int) HCS_MAX_SLOTS(temp));
77 : xhci_dbg(xhci, " Max interrupters: %u\n",
78 : (unsigned int) HCS_MAX_INTRS(temp));
79 : xhci_dbg(xhci, " Max ports: %u\n",
80 : (unsigned int) HCS_MAX_PORTS(temp));
81 :
82 2 : temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
83 : xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
84 : (unsigned int) temp);
85 : xhci_dbg(xhci, " Isoc scheduling threshold: %u\n",
86 : (unsigned int) HCS_IST(temp));
87 : xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n",
88 : (unsigned int) HCS_ERST_MAX(temp));
89 :
90 2 : temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
91 : xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
92 : (unsigned int) temp);
93 : xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n",
94 : (unsigned int) HCS_U1_LATENCY(temp));
95 : xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n",
96 : (unsigned int) HCS_U2_LATENCY(temp));
97 :
98 2 : temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
99 : xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
100 : xhci_dbg(xhci, " HC generates %s bit addresses\n",
101 : HCC_64BIT_ADDR(temp) ? "64" : "32");
102 : /* FIXME */
103 : xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n");
104 :
105 2 : temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
106 : xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
107 : }
108 1 :
109 : static void xhci_print_command_reg(struct xhci_hcd *xhci)
110 : {
111 1 : u32 temp;
112 :
113 2 : temp = xhci_readl(xhci, &xhci->op_regs->command);
114 : xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
115 : xhci_dbg(xhci, " HC is %s\n",
116 : (temp & CMD_RUN) ? "running" : "being stopped");
117 : xhci_dbg(xhci, " HC has %sfinished hard reset\n",
118 : (temp & CMD_RESET) ? "not " : "");
119 : xhci_dbg(xhci, " Event Interrupts %s\n",
120 : (temp & CMD_EIE) ? "enabled " : "disabled");
121 : xhci_dbg(xhci, " Host System Error Interrupts %s\n",
122 : (temp & CMD_EIE) ? "enabled " : "disabled");
123 : xhci_dbg(xhci, " HC has %sfinished light reset\n",
124 : (temp & CMD_LRESET) ? "not " : "");
125 1 : }
126 :
127 : static void xhci_print_status(struct xhci_hcd *xhci)
128 : {
129 1 : u32 temp;
130 :
131 2 : temp = xhci_readl(xhci, &xhci->op_regs->status);
132 : xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
133 : xhci_dbg(xhci, " Event ring is %sempty\n",
134 : (temp & STS_EINT) ? "not " : "");
135 : xhci_dbg(xhci, " %sHost System Error\n",
136 : (temp & STS_FATAL) ? "WARNING: " : "No ");
137 : xhci_dbg(xhci, " HC is %s\n",
138 : (temp & STS_HALT) ? "halted" : "running");
139 1 : }
140 :
141 : static void xhci_print_op_regs(struct xhci_hcd *xhci)
142 : {
143 : xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
144 2 : xhci_print_command_reg(xhci);
145 2 : xhci_print_status(xhci);
146 1 : }
147 :
148 : static void xhci_print_ports(struct xhci_hcd *xhci)
149 : {
150 1 : u32 __iomem *addr;
151 1 : int i, j;
152 1 : int ports;
153 5 : char *names[NUM_PORT_REGS] = {
154 1 : "status",
155 : "power",
156 : "link",
157 : "reserved",
158 : };
159 :
160 1 : ports = HCS_MAX_PORTS(xhci->hcs_params1);
161 1 : addr = &xhci->op_regs->port_status_base;
162 5 : for (i = 0; i < ports; i++) {
163 7 : for (j = 0; j < NUM_PORT_REGS; ++j) {
164 3 : xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
165 1 : addr, names[j],
166 : (unsigned int) xhci_readl(xhci, addr));
167 1 : addr++;
168 : }
169 1 : }
170 : }
171 :
172 : void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num)
173 : {
174 3 : void *addr;
175 3 : u32 temp;
176 3 : u64 temp_64;
177 :
178 3 : addr = &ir_set->irq_pending;
179 6 : temp = xhci_readl(xhci, addr);
180 6 : if (temp == XHCI_INIT_VALUE)
181 3 : return;
182 :
183 : xhci_dbg(xhci, " %p: ir_set[%i]\n", ir_set, set_num);
184 :
185 : xhci_dbg(xhci, " %p: ir_set.pending = 0x%x\n", addr,
186 : (unsigned int)temp);
187 :
188 3 : addr = &ir_set->irq_control;
189 6 : temp = xhci_readl(xhci, addr);
190 : xhci_dbg(xhci, " %p: ir_set.control = 0x%x\n", addr,
191 : (unsigned int)temp);
192 :
193 3 : addr = &ir_set->erst_size;
194 6 : temp = xhci_readl(xhci, addr);
195 : xhci_dbg(xhci, " %p: ir_set.erst_size = 0x%x\n", addr,
196 : (unsigned int)temp);
197 :
198 3 : addr = &ir_set->rsvd;
199 6 : temp = xhci_readl(xhci, addr);
200 : if (temp != XHCI_INIT_VALUE)
201 : xhci_dbg(xhci, " WARN: %p: ir_set.rsvd = 0x%x\n",
202 : addr, (unsigned int)temp);
203 :
204 3 : addr = &ir_set->erst_base;
205 6 : temp_64 = xhci_read_64(xhci, addr);
206 : xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n",
207 : addr, temp_64);
208 :
209 3 : addr = &ir_set->erst_dequeue;
210 6 : temp_64 = xhci_read_64(xhci, addr);
211 : xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n",
212 : addr, temp_64);
213 3 : }
214 :
215 : void xhci_print_run_regs(struct xhci_hcd *xhci)
216 : {
217 1 : u32 temp;
218 1 : int i;
219 :
220 : xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
221 2 : temp = xhci_readl(xhci, &xhci->run_regs->microframe_index);
222 : xhci_dbg(xhci, " %p: Microframe index = 0x%x\n",
223 : &xhci->run_regs->microframe_index,
224 : (unsigned int) temp);
225 5 : for (i = 0; i < 7; ++i) {
226 3 : temp = xhci_readl(xhci, &xhci->run_regs->rsvd[i]);
227 2 : if (temp != XHCI_INIT_VALUE)
228 : xhci_dbg(xhci, " WARN: %p: Rsvd[%i] = 0x%x\n",
229 : &xhci->run_regs->rsvd[i],
230 : i, (unsigned int) temp);
231 : }
232 1 : }
233 :
234 : void xhci_print_registers(struct xhci_hcd *xhci)
235 : {
236 2 : xhci_print_cap_regs(xhci);
237 2 : xhci_print_op_regs(xhci);
238 2 : xhci_print_ports(xhci);
239 1 : }
240 :
241 : void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb)
242 : {
243 3 : int i;
244 15 : for (i = 0; i < 4; ++i)
245 6 : xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",
246 3 : i*4, trb->generic.field[i]);
247 : }
248 :
249 : /**
250 : * Debug a transfer request block (TRB).
251 3 : */
252 : void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb)
253 : {
254 1 : u64 address;
255 4 : u32 type = xhci_readl(xhci, &trb->link.control) & TRB_TYPE_BITMASK;
256 1 :
257 : switch (type) {
258 3 : case TRB_TYPE(TRB_LINK):
259 : xhci_dbg(xhci, "Link TRB:\n");
260 2 : xhci_print_trb_offsets(xhci, trb);
261 :
262 1 : address = trb->link.segment_ptr;
263 : xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);
264 :
265 : xhci_dbg(xhci, "Interrupter target = 0x%x\n",
266 : GET_INTR_TARGET(trb->link.intr_target));
267 : xhci_dbg(xhci, "Cycle bit = %u\n",
268 : (unsigned int) (trb->link.control & TRB_CYCLE));
269 : xhci_dbg(xhci, "Toggle cycle bit = %u\n",
270 : (unsigned int) (trb->link.control & LINK_TOGGLE));
271 : xhci_dbg(xhci, "No Snoop bit = %u\n",
272 : (unsigned int) (trb->link.control & TRB_NO_SNOOP));
273 1 : break;
274 4 : case TRB_TYPE(TRB_TRANSFER):
275 1 : address = trb->trans_event.buffer;
276 : /*
277 : * FIXME: look at flags to figure out if it's an address or if
278 : * the data is directly in the buffer field.
279 : */
280 : xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
281 1 : break;
282 4 : case TRB_TYPE(TRB_COMPLETION):
283 1 : address = trb->event_cmd.cmd_trb;
284 : xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
285 : xhci_dbg(xhci, "Completion status = %u\n",
286 : (unsigned int) GET_COMP_CODE(trb->event_cmd.status));
287 : xhci_dbg(xhci, "Flags = 0x%x\n", (unsigned int) trb->event_cmd.flags);
288 1 : break;
289 2 : default:
290 1 : xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
291 : (unsigned int) type>>10);
292 2 : xhci_print_trb_offsets(xhci, trb);
293 1 : break;
294 : }
295 : }
296 3 :
297 : /**
298 : * Debug a segment with an xHCI ring.
299 : *
300 : * @return The Link TRB of the segment, or NULL if there is no Link TRB
301 : * (which is a bug, since all segments must have a Link TRB).
302 : *
303 : * Prints out all TRBs in the segment, even those after the Link TRB.
304 : *
305 : * XXX: should we print out TRBs that the HC owns? As long as we don't
306 : * write, that should be fine... We shouldn't expect that the memory pointed to
307 : * by the TRB is valid at all. Do we care about ones the HC owns? Probably,
308 : * for HC debugging.
309 : */
310 : void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg)
311 : {
312 8 : int i;
313 24 : u32 addr = (u32) seg->dma;
314 16 : union xhci_trb *trb = seg->trbs;
315 :
316 40 : for (i = 0; i < TRBS_PER_SEGMENT; ++i) {
317 24 : trb = &seg->trbs[i];
318 8 : xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", addr,
319 : lower_32_bits(trb->link.segment_ptr),
320 : upper_32_bits(trb->link.segment_ptr),
321 : (unsigned int) trb->link.intr_target,
322 : (unsigned int) trb->link.control);
323 16 : addr += sizeof(*trb);
324 : }
325 : }
326 :
327 : void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring)
328 : {
329 : xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n",
330 : ring->dequeue,
331 : (unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg,
332 : ring->dequeue));
333 : xhci_dbg(xhci, "Ring deq updated %u times\n",
334 : ring->deq_updates);
335 : xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n",
336 : ring->enqueue,
337 : (unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg,
338 : ring->enqueue));
339 : xhci_dbg(xhci, "Ring enq updated %u times\n",
340 : ring->enq_updates);
341 2 : }
342 :
343 : /**
344 : * Debugging for an xHCI ring, which is a queue broken into multiple segments.
345 : *
346 : * Print out each segment in the ring. Check that the DMA address in
347 : * each link segment actually matches the segment's stored DMA address.
348 : * Check that the link end bit is only set at the end of the ring.
349 : * Check that the dequeue and enqueue pointers point to real data in this ring
350 : * (not some other ring).
351 : */
352 : void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring)
353 : {
354 4 : /* FIXME: Throw an error if any segment doesn't have a Link TRB */
355 4 : struct xhci_segment *seg;
356 4 : struct xhci_segment *first_seg = ring->first_seg;
357 8 : xhci_debug_segment(xhci, first_seg);
358 :
359 16 : if (!ring->enq_updates && !ring->deq_updates) {
360 : xhci_dbg(xhci, " Ring has not been updated\n");
361 4 : return;
362 : }
363 20 : for (seg = first_seg->next; seg != first_seg; seg = seg->next)
364 12 : xhci_debug_segment(xhci, seg);
365 8 : }
366 :
367 : void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
368 : {
369 3 : u32 addr = (u32) erst->erst_dma_addr;
370 5 : int i;
371 1 : struct xhci_erst_entry *entry;
372 :
373 5 : for (i = 0; i < erst->num_entries; ++i) {
374 3 : entry = &erst->entries[i];
375 1 : xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n",
376 : (unsigned int) addr,
377 : lower_32_bits(entry->seg_addr),
378 : upper_32_bits(entry->seg_addr),
379 : (unsigned int) entry->seg_size,
380 1 : (unsigned int) entry->rsvd);
381 1 : addr += sizeof(*entry);
382 : }
383 : }
384 :
385 : void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
386 : {
387 2 : u64 val;
388 :
389 4 : val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
390 : xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
391 : lower_32_bits(val));
392 : xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
393 : upper_32_bits(val));
394 2 : }
395 :
396 : /* Print the last 32 bytes for 64-byte contexts */
397 : static void dbg_rsvd64(struct xhci_hcd *xhci, u64 *ctx, dma_addr_t dma)
398 : {
399 60 : int i;
400 300 : for (i = 0; i < 4; ++i) {
401 120 : xhci_dbg(xhci, "@%p (virt) @%08llx "
402 60 : "(dma) %#08llx - rsvd64[%d]\n",
403 : &ctx[4 + i], (unsigned long long)dma,
404 : ctx[4 + i], i);
405 60 : dma += 8;
406 : }
407 60 : }
408 :
409 : void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx)
410 : {
411 20 : /* Fields are 32 bits wide, DMA addresses are in bytes */
412 40 : int field_size = 32 / 8;
413 20 : int i;
414 20 :
415 80 : struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
416 60 : dma_addr_t dma = ctx->dma +
417 : ((unsigned long)slot_ctx - (unsigned long)ctx->bytes);
418 40 : int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
419 :
420 : xhci_dbg(xhci, "Slot Context:\n");
421 : xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",
422 : &slot_ctx->dev_info,
423 : (unsigned long long)dma, slot_ctx->dev_info);
424 20 : dma += field_size;
425 : xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",
426 : &slot_ctx->dev_info2,
427 : (unsigned long long)dma, slot_ctx->dev_info2);
428 20 : dma += field_size;
429 : xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",
430 : &slot_ctx->tt_info,
431 : (unsigned long long)dma, slot_ctx->tt_info);
432 20 : dma += field_size;
433 : xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",
434 : &slot_ctx->dev_state,
435 : (unsigned long long)dma, slot_ctx->dev_state);
436 20 : dma += field_size;
437 100 : for (i = 0; i < 4; ++i) {
438 40 : xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
439 20 : &slot_ctx->reserved[i], (unsigned long long)dma,
440 : slot_ctx->reserved[i], i);
441 20 : dma += field_size;
442 : }
443 :
444 40 : if (csz)
445 40 : dbg_rsvd64(xhci, (u64 *)slot_ctx, dma);
446 40 : }
447 :
448 : void xhci_dbg_ep_ctx(struct xhci_hcd *xhci,
449 : struct xhci_container_ctx *ctx,
450 20 : unsigned int last_ep)
451 20 : {
452 20 : int i, j;
453 40 : int last_ep_ctx = 31;
454 20 : /* Fields are 32 bits wide, DMA addresses are in bytes */
455 40 : int field_size = 32 / 8;
456 60 : int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
457 20 :
458 40 : if (last_ep < 31)
459 20 : last_ep_ctx = last_ep + 1;
460 120 : for (i = 0; i < last_ep_ctx; ++i) {
461 120 : struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, ctx, i);
462 60 : dma_addr_t dma = ctx->dma +
463 : ((unsigned long)ep_ctx - (unsigned long)ctx->bytes);
464 :
465 : xhci_dbg(xhci, "Endpoint %02d Context:\n", i);
466 : xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",
467 20 : &ep_ctx->ep_info,
468 : (unsigned long long)dma, ep_ctx->ep_info);
469 20 : dma += field_size;
470 : xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",
471 : &ep_ctx->ep_info2,
472 : (unsigned long long)dma, ep_ctx->ep_info2);
473 20 : dma += field_size;
474 : xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n",
475 : &ep_ctx->deq,
476 : (unsigned long long)dma, ep_ctx->deq);
477 20 : dma += 2*field_size;
478 : xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",
479 : &ep_ctx->tx_info,
480 : (unsigned long long)dma, ep_ctx->tx_info);
481 20 : dma += field_size;
482 100 : for (j = 0; j < 3; ++j) {
483 40 : xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
484 20 : &ep_ctx->reserved[j],
485 : (unsigned long long)dma,
486 : ep_ctx->reserved[j], j);
487 20 : dma += field_size;
488 : }
489 :
490 40 : if (csz)
491 40 : dbg_rsvd64(xhci, (u64 *)ep_ctx, dma);
492 : }
493 : }
494 :
495 : void xhci_dbg_ctx(struct xhci_hcd *xhci,
496 : struct xhci_container_ctx *ctx,
497 20 : unsigned int last_ep)
498 20 : {
499 20 : int i;
500 20 : /* Fields are 32 bits wide, DMA addresses are in bytes */
501 40 : int field_size = 32 / 8;
502 20 : struct xhci_slot_ctx *slot_ctx;
503 40 : dma_addr_t dma = ctx->dma;
504 40 : int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
505 :
506 40 : if (ctx->type == XHCI_CTX_TYPE_INPUT) {
507 60 : struct xhci_input_control_ctx *ctrl_ctx =
508 : xhci_get_input_control_ctx(xhci, ctx);
509 : xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",
510 : &ctrl_ctx->drop_flags, (unsigned long long)dma,
511 : ctrl_ctx->drop_flags);
512 20 : dma += field_size;
513 : xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n",
514 : &ctrl_ctx->add_flags, (unsigned long long)dma,
515 : ctrl_ctx->add_flags);
516 20 : dma += field_size;
517 100 : for (i = 0; i < 6; ++i) {
518 40 : xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n",
519 20 : &ctrl_ctx->rsvd2[i], (unsigned long long)dma,
520 : ctrl_ctx->rsvd2[i], i);
521 20 : dma += field_size;
522 : }
523 :
524 40 : if (csz)
525 40 : dbg_rsvd64(xhci, (u64 *)ctrl_ctx, dma);
526 : }
527 :
528 120 : slot_ctx = xhci_get_slot_ctx(xhci, ctx);
529 60 : xhci_dbg_slot_ctx(xhci, ctx);
530 40 : xhci_dbg_ep_ctx(xhci, ctx, last_ep);
531 20 : }
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