Line data Source code
1 : /*
2 : * linux/drivers/char/8250.c
3 : *
4 : * Driver for 8250/16550-type serial ports
5 : *
6 : * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 : *
8 : * Copyright (C) 2001 Russell King.
9 : *
10 : * This program is free software; you can redistribute it and/or modify
11 : * it under the terms of the GNU General Public License as published by
12 : * the Free Software Foundation; either version 2 of the License, or
13 : * (at your option) any later version.
14 : *
15 : * A note about mapbase / membase
16 : *
17 : * mapbase is the physical address of the IO port.
18 : * membase is an 'ioremapped' cookie.
19 : */
20 :
21 : #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 : #define SUPPORT_SYSRQ
23 : #endif
24 :
25 : #include <linux/module.h>
26 : #include <linux/moduleparam.h>
27 : #include <linux/ioport.h>
28 : #include <linux/init.h>
29 : #include <linux/console.h>
30 : #include <linux/sysrq.h>
31 : #include <linux/delay.h>
32 : #include <linux/platform_device.h>
33 : #include <linux/tty.h>
34 : #include <linux/tty_flip.h>
35 : #include <linux/serial_reg.h>
36 : #include <linux/serial_core.h>
37 : #include <linux/serial.h>
38 : #include <linux/serial_8250.h>
39 : #include <linux/nmi.h>
40 : #include <linux/mutex.h>
41 :
42 : #include <asm/io.h>
43 : #include <asm/irq.h>
44 :
45 : #include "8250.h"
46 :
47 : #ifdef CONFIG_SPARC
48 : #include "suncore.h"
49 : #endif
50 :
51 : /*
52 : * Configuration:
53 : * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 : * is unsafe when used on edge-triggered interrupts.
55 : */
56 1 : static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57 :
58 1 : static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59 :
60 1 : static struct uart_driver serial8250_reg;
61 :
62 : static int serial_index(struct uart_port *port)
63 : {
64 14 : return (serial8250_reg.minor - 64) + port->line;
65 : }
66 :
67 1 : static unsigned int skip_txen_test; /* force skip of txen test at init time */
68 :
69 : /*
70 : * Debugging.
71 : */
72 : #if 0
73 : #define DEBUG_AUTOCONF(fmt...) printk(fmt)
74 : #else
75 : #define DEBUG_AUTOCONF(fmt...) do { } while (0)
76 : #endif
77 :
78 : #if 0
79 : #define DEBUG_INTR(fmt...) printk(fmt)
80 : #else
81 : #define DEBUG_INTR(fmt...) do { } while (0)
82 : #endif
83 :
84 : #define PASS_LIMIT 256
85 :
86 : #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87 :
88 :
89 : /*
90 : * We default to IRQ0 for the "no irq" hack. Some
91 : * machine types want others as well - they're free
92 : * to redefine this in their header file.
93 : */
94 : #define is_real_interrupt(irq) ((irq) != 0)
95 :
96 : #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97 : #define CONFIG_SERIAL_DETECT_IRQ 1
98 : #endif
99 : #ifdef CONFIG_SERIAL_8250_MANY_PORTS
100 : #define CONFIG_SERIAL_MANY_PORTS 1
101 : #endif
102 :
103 : /*
104 : * HUB6 is always on. This will be removed once the header
105 : * files have been cleaned.
106 : */
107 : #define CONFIG_HUB6 1
108 :
109 : #include <asm/serial.h>
110 : /*
111 : * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 : * standard enumeration mechanism. Platforms that can find all
113 : * serial ports via mechanisms like ACPI or PCI need not supply it.
114 : */
115 : #ifndef SERIAL_PORT_DFNS
116 : #define SERIAL_PORT_DFNS
117 : #endif
118 :
119 1 : static const struct old_serial_port old_serial_port[] = {
120 1 : SERIAL_PORT_DFNS /* defined in asm/serial.h */
121 : };
122 :
123 : #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
124 :
125 : #ifdef CONFIG_SERIAL_8250_RSA
126 :
127 : #define PORT_RSA_MAX 4
128 : static unsigned long probe_rsa[PORT_RSA_MAX];
129 : static unsigned int probe_rsa_count;
130 : #endif /* CONFIG_SERIAL_8250_RSA */
131 :
132 : struct uart_8250_port {
133 : struct uart_port port;
134 : struct timer_list timer; /* "no irq" timer */
135 : struct list_head list; /* ports on this IRQ */
136 : unsigned short capabilities; /* port capabilities */
137 : unsigned short bugs; /* port bugs */
138 : unsigned int tx_loadsz; /* transmit fifo load size */
139 : unsigned char acr;
140 : unsigned char ier;
141 : unsigned char lcr;
142 : unsigned char mcr;
143 : unsigned char mcr_mask; /* mask of user bits */
144 : unsigned char mcr_force; /* mask of forced bits */
145 : unsigned char cur_iotype; /* Running I/O type */
146 :
147 : /*
148 : * Some bits in registers are cleared on a read, so they must
149 : * be saved whenever the register is read but the bits will not
150 : * be immediately processed.
151 : */
152 : #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 : unsigned char lsr_saved_flags;
154 : #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 : unsigned char msr_saved_flags;
156 :
157 : /*
158 : * We provide a per-port pm hook.
159 : */
160 : void (*pm)(struct uart_port *port,
161 : unsigned int state, unsigned int old);
162 1 : };
163 :
164 : struct irq_info {
165 : struct hlist_node node;
166 : int irq;
167 : spinlock_t lock; /* Protects list not the hash */
168 : struct list_head *head;
169 : };
170 :
171 : #define NR_IRQ_HASH 32 /* Can be adjusted later */
172 1 : static struct hlist_head irq_lists[NR_IRQ_HASH];
173 1 : static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
174 :
175 : /*
176 : * Here we define the default xmit fifo size used for each type of UART.
177 : */
178 1 : static const struct serial8250_config uart_config[] = {
179 : [PORT_UNKNOWN] = {
180 : .name = "unknown",
181 : .fifo_size = 1,
182 : .tx_loadsz = 1,
183 : },
184 : [PORT_8250] = {
185 : .name = "8250",
186 : .fifo_size = 1,
187 : .tx_loadsz = 1,
188 : },
189 : [PORT_16450] = {
190 : .name = "16450",
191 : .fifo_size = 1,
192 : .tx_loadsz = 1,
193 : },
194 : [PORT_16550] = {
195 : .name = "16550",
196 : .fifo_size = 1,
197 : .tx_loadsz = 1,
198 : },
199 : [PORT_16550A] = {
200 : .name = "16550A",
201 : .fifo_size = 16,
202 : .tx_loadsz = 16,
203 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
204 : .flags = UART_CAP_FIFO,
205 : },
206 : [PORT_CIRRUS] = {
207 : .name = "Cirrus",
208 : .fifo_size = 1,
209 : .tx_loadsz = 1,
210 : },
211 : [PORT_16650] = {
212 : .name = "ST16650",
213 : .fifo_size = 1,
214 : .tx_loadsz = 1,
215 : .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
216 : },
217 : [PORT_16650V2] = {
218 : .name = "ST16650V2",
219 : .fifo_size = 32,
220 : .tx_loadsz = 16,
221 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
222 : UART_FCR_T_TRIG_00,
223 : .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
224 : },
225 : [PORT_16750] = {
226 : .name = "TI16750",
227 : .fifo_size = 64,
228 : .tx_loadsz = 64,
229 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
230 : UART_FCR7_64BYTE,
231 : .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
232 : },
233 : [PORT_STARTECH] = {
234 : .name = "Startech",
235 : .fifo_size = 1,
236 : .tx_loadsz = 1,
237 : },
238 : [PORT_16C950] = {
239 : .name = "16C950/954",
240 : .fifo_size = 128,
241 : .tx_loadsz = 128,
242 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 : .flags = UART_CAP_FIFO,
244 : },
245 : [PORT_16654] = {
246 : .name = "ST16654",
247 : .fifo_size = 64,
248 : .tx_loadsz = 32,
249 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
250 : UART_FCR_T_TRIG_10,
251 : .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
252 : },
253 : [PORT_16850] = {
254 : .name = "XR16850",
255 : .fifo_size = 128,
256 : .tx_loadsz = 128,
257 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
258 : /* UART_CAP_EFR breaks billionon CF bluetooth card. */
259 : .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
260 : },
261 : [PORT_RSA] = {
262 : .name = "RSA",
263 : .fifo_size = 2048,
264 : .tx_loadsz = 2048,
265 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
266 : .flags = UART_CAP_FIFO,
267 : },
268 : [PORT_NS16550A] = {
269 : .name = "NS16550A",
270 : .fifo_size = 16,
271 : .tx_loadsz = 16,
272 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 : .flags = UART_CAP_FIFO | UART_NATSEMI,
274 : },
275 : [PORT_XSCALE] = {
276 : .name = "XScale",
277 : .fifo_size = 32,
278 : .tx_loadsz = 32,
279 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
280 : .flags = UART_CAP_FIFO | UART_CAP_UUE,
281 : },
282 : [PORT_RM9000] = {
283 : .name = "RM9000",
284 : .fifo_size = 16,
285 : .tx_loadsz = 16,
286 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
287 : .flags = UART_CAP_FIFO,
288 : },
289 : [PORT_OCTEON] = {
290 : .name = "OCTEON",
291 : .fifo_size = 64,
292 : .tx_loadsz = 64,
293 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
294 : .flags = UART_CAP_FIFO,
295 : },
296 : [PORT_AR7] = {
297 : .name = "AR7",
298 : .fifo_size = 16,
299 : .tx_loadsz = 16,
300 : .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
301 : .flags = UART_CAP_FIFO | UART_CAP_AFE,
302 : },
303 : };
304 :
305 : #if defined (CONFIG_SERIAL_8250_AU1X00)
306 :
307 : /* Au1x00 UART hardware has a weird register layout */
308 : static const u8 au_io_in_map[] = {
309 : [UART_RX] = 0,
310 : [UART_IER] = 2,
311 : [UART_IIR] = 3,
312 : [UART_LCR] = 5,
313 : [UART_MCR] = 6,
314 : [UART_LSR] = 7,
315 : [UART_MSR] = 8,
316 : };
317 :
318 : static const u8 au_io_out_map[] = {
319 : [UART_TX] = 1,
320 : [UART_IER] = 2,
321 : [UART_FCR] = 4,
322 : [UART_LCR] = 5,
323 : [UART_MCR] = 6,
324 : };
325 :
326 : /* sane hardware needs no mapping */
327 : static inline int map_8250_in_reg(struct uart_port *p, int offset)
328 : {
329 : if (p->iotype != UPIO_AU)
330 : return offset;
331 : return au_io_in_map[offset];
332 : }
333 :
334 : static inline int map_8250_out_reg(struct uart_port *p, int offset)
335 : {
336 : if (p->iotype != UPIO_AU)
337 : return offset;
338 : return au_io_out_map[offset];
339 : }
340 :
341 : #elif defined(CONFIG_SERIAL_8250_RM9K)
342 :
343 : static const u8
344 : regmap_in[8] = {
345 : [UART_RX] = 0x00,
346 : [UART_IER] = 0x0c,
347 : [UART_IIR] = 0x14,
348 : [UART_LCR] = 0x1c,
349 : [UART_MCR] = 0x20,
350 : [UART_LSR] = 0x24,
351 : [UART_MSR] = 0x28,
352 : [UART_SCR] = 0x2c
353 : },
354 : regmap_out[8] = {
355 : [UART_TX] = 0x04,
356 : [UART_IER] = 0x0c,
357 : [UART_FCR] = 0x18,
358 : [UART_LCR] = 0x1c,
359 : [UART_MCR] = 0x20,
360 : [UART_LSR] = 0x24,
361 : [UART_MSR] = 0x28,
362 : [UART_SCR] = 0x2c
363 : };
364 :
365 : static inline int map_8250_in_reg(struct uart_port *p, int offset)
366 : {
367 : if (p->iotype != UPIO_RM9000)
368 : return offset;
369 : return regmap_in[offset];
370 : }
371 :
372 : static inline int map_8250_out_reg(struct uart_port *p, int offset)
373 : {
374 : if (p->iotype != UPIO_RM9000)
375 : return offset;
376 : return regmap_out[offset];
377 : }
378 :
379 : #else
380 :
381 : /* sane hardware needs no mapping */
382 : #define map_8250_in_reg(up, offset) (offset)
383 : #define map_8250_out_reg(up, offset) (offset)
384 :
385 : #endif
386 :
387 : static unsigned int hub6_serial_in(struct uart_port *p, int offset)
388 : {
389 0 : offset = map_8250_in_reg(p, offset) << p->regshift;
390 0 : outb(p->hub6 - 1 + offset, p->iobase);
391 0 : return inb(p->iobase + 1);
392 : }
393 :
394 : static void hub6_serial_out(struct uart_port *p, int offset, int value)
395 : {
396 0 : offset = map_8250_out_reg(p, offset) << p->regshift;
397 0 : outb(p->hub6 - 1 + offset, p->iobase);
398 0 : outb(value, p->iobase + 1);
399 0 : }
400 :
401 : static unsigned int mem_serial_in(struct uart_port *p, int offset)
402 : {
403 0 : offset = map_8250_in_reg(p, offset) << p->regshift;
404 0 : return readb(p->membase + offset);
405 : }
406 :
407 : static void mem_serial_out(struct uart_port *p, int offset, int value)
408 : {
409 0 : offset = map_8250_out_reg(p, offset) << p->regshift;
410 0 : writeb(value, p->membase + offset);
411 0 : }
412 :
413 : static void mem32_serial_out(struct uart_port *p, int offset, int value)
414 : {
415 0 : offset = map_8250_out_reg(p, offset) << p->regshift;
416 0 : writel(value, p->membase + offset);
417 0 : }
418 :
419 : static unsigned int mem32_serial_in(struct uart_port *p, int offset)
420 : {
421 0 : offset = map_8250_in_reg(p, offset) << p->regshift;
422 0 : return readl(p->membase + offset);
423 : }
424 :
425 : #ifdef CONFIG_SERIAL_8250_AU1X00
426 : static unsigned int au_serial_in(struct uart_port *p, int offset)
427 : {
428 : offset = map_8250_in_reg(p, offset) << p->regshift;
429 : return __raw_readl(p->membase + offset);
430 : }
431 :
432 : static void au_serial_out(struct uart_port *p, int offset, int value)
433 : {
434 : offset = map_8250_out_reg(p, offset) << p->regshift;
435 : __raw_writel(value, p->membase + offset);
436 : }
437 : #endif
438 :
439 : static unsigned int tsi_serial_in(struct uart_port *p, int offset)
440 : {
441 0 : unsigned int tmp;
442 0 : offset = map_8250_in_reg(p, offset) << p->regshift;
443 0 : if (offset == UART_IIR) {
444 0 : tmp = readl(p->membase + (UART_IIR & ~3));
445 0 : return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
446 : } else
447 0 : return readb(p->membase + offset);
448 : }
449 :
450 : static void tsi_serial_out(struct uart_port *p, int offset, int value)
451 : {
452 0 : offset = map_8250_out_reg(p, offset) << p->regshift;
453 0 : if (!((offset == UART_IER) && (value & UART_IER_UUE)))
454 0 : writeb(value, p->membase + offset);
455 0 : }
456 :
457 : static void dwapb_serial_out(struct uart_port *p, int offset, int value)
458 : {
459 0 : int save_offset = offset;
460 0 : offset = map_8250_out_reg(p, offset) << p->regshift;
461 0 : /* Save the LCR value so it can be re-written when a
462 : * Busy Detect interrupt occurs. */
463 0 : if (save_offset == UART_LCR) {
464 0 : struct uart_8250_port *up = (struct uart_8250_port *)p;
465 0 : up->lcr = value;
466 : }
467 0 : writeb(value, p->membase + offset);
468 : /* Read the IER to ensure any interrupt is cleared before
469 : * returning from ISR. */
470 0 : if (save_offset == UART_TX || save_offset == UART_IER)
471 0 : value = p->serial_in(p, UART_IER);
472 0 : }
473 :
474 : static unsigned int io_serial_in(struct uart_port *p, int offset)
475 : {
476 0 : offset = map_8250_in_reg(p, offset) << p->regshift;
477 0 : return inb(p->iobase + offset);
478 : }
479 :
480 : static void io_serial_out(struct uart_port *p, int offset, int value)
481 : {
482 0 : offset = map_8250_out_reg(p, offset) << p->regshift;
483 0 : outb(value, p->iobase + offset);
484 0 : }
485 :
486 : static void set_io_from_upio(struct uart_port *p)
487 : {
488 12 : struct uart_8250_port *up = (struct uart_8250_port *)p;
489 : switch (p->iotype) {
490 24 : case UPIO_HUB6:
491 6 : p->serial_in = hub6_serial_in;
492 6 : p->serial_out = hub6_serial_out;
493 6 : break;
494 6 :
495 24 : case UPIO_MEM:
496 6 : p->serial_in = mem_serial_in;
497 6 : p->serial_out = mem_serial_out;
498 6 : break;
499 6 :
500 30 : case UPIO_RM9000:
501 24 : case UPIO_MEM32:
502 6 : p->serial_in = mem32_serial_in;
503 6 : p->serial_out = mem32_serial_out;
504 6 : break;
505 6 :
506 : #ifdef CONFIG_SERIAL_8250_AU1X00
507 : case UPIO_AU:
508 : p->serial_in = au_serial_in;
509 : p->serial_out = au_serial_out;
510 : break;
511 : #endif
512 24 : case UPIO_TSI:
513 6 : p->serial_in = tsi_serial_in;
514 6 : p->serial_out = tsi_serial_out;
515 6 : break;
516 6 :
517 24 : case UPIO_DWAPB:
518 6 : p->serial_in = mem_serial_in;
519 6 : p->serial_out = dwapb_serial_out;
520 6 : break;
521 6 :
522 6 : default:
523 12 : p->serial_in = io_serial_in;
524 6 : p->serial_out = io_serial_out;
525 6 : break;
526 : }
527 : /* Remember loaded iotype */
528 6 : up->cur_iotype = p->iotype;
529 6 : }
530 :
531 : static void
532 : serial_out_sync(struct uart_8250_port *up, int offset, int value)
533 : {
534 8 : struct uart_port *p = &up->port;
535 : switch (p->iotype) {
536 16 : case UPIO_MEM:
537 16 : case UPIO_MEM32:
538 : #ifdef CONFIG_SERIAL_8250_AU1X00
539 : case UPIO_AU:
540 : #endif
541 16 : case UPIO_DWAPB:
542 32 : p->serial_out(p, offset, value);
543 24 : p->serial_in(p, UART_LCR); /* safe, no side-effects */
544 4 : break;
545 8 : default:
546 36 : p->serial_out(p, offset, value);
547 4 : }
548 8 : }
549 4 :
550 4 : #define serial_in(up, offset) \
551 : (up->port.serial_in(&(up)->port, (offset)))
552 : #define serial_out(up, offset, value) \
553 : (up->port.serial_out(&(up)->port, (offset), (value)))
554 : /*
555 : * We used to support using pause I/O for certain machines. We
556 : * haven't supported this for a while, but just in case it's badly
557 : * needed for certain old 386 machines, I've left these #define's
558 : * in....
559 : */
560 : #define serial_inp(up, offset) serial_in(up, offset)
561 : #define serial_outp(up, offset, value) serial_out(up, offset, value)
562 :
563 : /* Uart divisor latch read */
564 : static inline int _serial_dl_read(struct uart_8250_port *up)
565 : {
566 224 : return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
567 16 : }
568 :
569 : /* Uart divisor latch write */
570 : static inline void _serial_dl_write(struct uart_8250_port *up, int value)
571 : {
572 192 : serial_outp(up, UART_DLL, value & 0xff);
573 192 : serial_outp(up, UART_DLM, value >> 8 & 0xff);
574 24 : }
575 :
576 : #if defined(CONFIG_SERIAL_8250_AU1X00)
577 : /* Au1x00 haven't got a standard divisor latch */
578 : static int serial_dl_read(struct uart_8250_port *up)
579 : {
580 : if (up->port.iotype == UPIO_AU)
581 : return __raw_readl(up->port.membase + 0x28);
582 : else
583 : return _serial_dl_read(up);
584 : }
585 :
586 : static void serial_dl_write(struct uart_8250_port *up, int value)
587 : {
588 : if (up->port.iotype == UPIO_AU)
589 : __raw_writel(value, up->port.membase + 0x28);
590 : else
591 : _serial_dl_write(up, value);
592 : }
593 : #elif defined(CONFIG_SERIAL_8250_RM9K)
594 : static int serial_dl_read(struct uart_8250_port *up)
595 : {
596 : return (up->port.iotype == UPIO_RM9000) ?
597 : (((__raw_readl(up->port.membase + 0x10) << 8) |
598 : (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
599 : _serial_dl_read(up);
600 : }
601 :
602 : static void serial_dl_write(struct uart_8250_port *up, int value)
603 : {
604 : if (up->port.iotype == UPIO_RM9000) {
605 : __raw_writel(value, up->port.membase + 0x08);
606 : __raw_writel(value >> 8, up->port.membase + 0x10);
607 : } else {
608 : _serial_dl_write(up, value);
609 : }
610 : }
611 : #else
612 : #define serial_dl_read(up) _serial_dl_read(up)
613 : #define serial_dl_write(up, value) _serial_dl_write(up, value)
614 : #endif
615 :
616 : /*
617 : * For the 16C950
618 : */
619 : static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
620 : {
621 704 : serial_out(up, UART_SCR, offset);
622 704 : serial_out(up, UART_ICR, value);
623 88 : }
624 :
625 : static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
626 : {
627 16 : unsigned int value;
628 :
629 48 : serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
630 128 : serial_out(up, UART_SCR, offset);
631 96 : value = serial_in(up, UART_ICR);
632 48 : serial_icr_write(up, UART_ACR, up->acr);
633 :
634 16 : return value;
635 : }
636 :
637 : /*
638 : * FIFO support.
639 : */
640 : static void serial8250_clear_fifos(struct uart_8250_port *p)
641 : {
642 78 : if (p->capabilities & UART_CAP_FIFO) {
643 208 : serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
644 208 : serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
645 : UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
646 208 : serial_outp(p, UART_FCR, 0);
647 : }
648 26 : }
649 :
650 : /*
651 : * IER sleep support. UARTs which have EFRs need the "extended
652 : * capability" bit enabled. Note that on XR16C850s, we need to
653 : * reset LCR to write to IER.
654 : */
655 : static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
656 : {
657 18 : if (p->capabilities & UART_CAP_SLEEP) {
658 18 : if (p->capabilities & UART_CAP_EFR) {
659 48 : serial_outp(p, UART_LCR, 0xBF);
660 48 : serial_outp(p, UART_EFR, UART_EFR_ECB);
661 48 : serial_outp(p, UART_LCR, 0);
662 : }
663 78 : serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
664 18 : if (p->capabilities & UART_CAP_EFR) {
665 48 : serial_outp(p, UART_LCR, 0xBF);
666 48 : serial_outp(p, UART_EFR, 0);
667 48 : serial_outp(p, UART_LCR, 0);
668 : }
669 : }
670 6 : }
671 :
672 : #ifdef CONFIG_SERIAL_8250_RSA
673 : /*
674 : * Attempts to turn on the RSA FIFO. Returns zero on failure.
675 : * We set the port uart clock rate if we succeed.
676 : */
677 : static int __enable_rsa(struct uart_8250_port *up)
678 : {
679 : unsigned char mode;
680 : int result;
681 :
682 : mode = serial_inp(up, UART_RSA_MSR);
683 : result = mode & UART_RSA_MSR_FIFO;
684 :
685 : if (!result) {
686 : serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
687 : mode = serial_inp(up, UART_RSA_MSR);
688 : result = mode & UART_RSA_MSR_FIFO;
689 : }
690 :
691 : if (result)
692 : up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
693 :
694 : return result;
695 : }
696 :
697 : static void enable_rsa(struct uart_8250_port *up)
698 : {
699 : if (up->port.type == PORT_RSA) {
700 : if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
701 : spin_lock_irq(&up->port.lock);
702 : __enable_rsa(up);
703 : spin_unlock_irq(&up->port.lock);
704 : }
705 : if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
706 : serial_outp(up, UART_RSA_FRR, 0);
707 : }
708 : }
709 :
710 : /*
711 : * Attempts to turn off the RSA FIFO. Returns zero on failure.
712 : * It is unknown why interrupts were disabled in here. However,
713 : * the caller is expected to preserve this behaviour by grabbing
714 : * the spinlock before calling this function.
715 : */
716 : static void disable_rsa(struct uart_8250_port *up)
717 : {
718 : unsigned char mode;
719 : int result;
720 :
721 : if (up->port.type == PORT_RSA &&
722 : up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
723 : spin_lock_irq(&up->port.lock);
724 :
725 : mode = serial_inp(up, UART_RSA_MSR);
726 : result = !(mode & UART_RSA_MSR_FIFO);
727 :
728 : if (!result) {
729 : serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
730 : mode = serial_inp(up, UART_RSA_MSR);
731 : result = !(mode & UART_RSA_MSR_FIFO);
732 : }
733 :
734 : if (result)
735 : up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
736 : spin_unlock_irq(&up->port.lock);
737 : }
738 : }
739 : #endif /* CONFIG_SERIAL_8250_RSA */
740 :
741 : /*
742 : * This is a quickie test to see how big the FIFO is.
743 : * It doesn't work at all the time, more's the pity.
744 : */
745 : static int size_fifo(struct uart_8250_port *up)
746 : {
747 8 : unsigned char old_fcr, old_mcr, old_lcr;
748 8 : unsigned short old_dl;
749 8 : int count;
750 8 :
751 64 : old_lcr = serial_inp(up, UART_LCR);
752 72 : serial_outp(up, UART_LCR, 0);
753 64 : old_fcr = serial_inp(up, UART_FCR);
754 64 : old_mcr = serial_inp(up, UART_MCR);
755 72 : serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
756 8 : UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
757 72 : serial_outp(up, UART_MCR, UART_MCR_LOOP);
758 72 : serial_outp(up, UART_LCR, UART_LCR_DLAB);
759 24 : old_dl = serial_dl_read(up);
760 16 : serial_dl_write(up, 0x0001);
761 64 : serial_outp(up, UART_LCR, 0x03);
762 40 : for (count = 0; count < 256; count++)
763 72 : serial_outp(up, UART_TX, count);
764 72 : mdelay(20);/* FIXME - schedule_timeout */
765 104 : for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
766 32 : (count < 256); count++)
767 48 : serial_inp(up, UART_RX);
768 80 : serial_outp(up, UART_FCR, old_fcr);
769 64 : serial_outp(up, UART_MCR, old_mcr);
770 64 : serial_outp(up, UART_LCR, UART_LCR_DLAB);
771 16 : serial_dl_write(up, old_dl);
772 64 : serial_outp(up, UART_LCR, old_lcr);
773 :
774 8 : return count;
775 : }
776 :
777 : /*
778 : * Read UART ID using the divisor method - set DLL and DLM to zero
779 : * and the revision will be in DLL and device type in DLM. We
780 : * preserve the device state across this.
781 : */
782 : static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
783 : {
784 8 : unsigned char old_dll, old_dlm, old_lcr;
785 8 : unsigned int id;
786 8 :
787 64 : old_lcr = serial_inp(p, UART_LCR);
788 72 : serial_outp(p, UART_LCR, UART_LCR_DLAB);
789 8 :
790 64 : old_dll = serial_inp(p, UART_DLL);
791 64 : old_dlm = serial_inp(p, UART_DLM);
792 8 :
793 64 : serial_outp(p, UART_DLL, 0);
794 64 : serial_outp(p, UART_DLM, 0);
795 :
796 104 : id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
797 :
798 64 : serial_outp(p, UART_DLL, old_dll);
799 64 : serial_outp(p, UART_DLM, old_dlm);
800 64 : serial_outp(p, UART_LCR, old_lcr);
801 :
802 8 : return id;
803 : }
804 :
805 : /*
806 : * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
807 : * When this function is called we know it is at least a StarTech
808 : * 16650 V2, but it might be one of several StarTech UARTs, or one of
809 : * its clones. (We treat the broken original StarTech 16650 V1 as a
810 : * 16550, and why not? Startech doesn't seem to even acknowledge its
811 : * existence.)
812 : *
813 : * What evil have men's minds wrought...
814 : */
815 : static void autoconfig_has_efr(struct uart_8250_port *up)
816 : {
817 4 : unsigned int id1, id2, id3, rev;
818 4 :
819 4 : /*
820 4 : * Everything with an EFR has SLEEP
821 4 : */
822 8 : up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
823 :
824 : /*
825 : * First we check to see if it's an Oxford Semiconductor UART.
826 : *
827 : * If we have to do this here because some non-National
828 : * Semiconductor clone chips lock up if you try writing to the
829 : * LSR register (which serial_icr_read does)
830 : */
831 :
832 : /*
833 : * Check for Oxford Semiconductor 16C950.
834 : *
835 : * EFR [4] must be set else this test fails.
836 : *
837 : * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
838 : * claims that it's needed for 952 dual UART's (which are not
839 : * recommended for new designs).
840 : */
841 4 : up->acr = 0;
842 32 : serial_out(up, UART_LCR, 0xBF);
843 32 : serial_out(up, UART_EFR, UART_EFR_ECB);
844 32 : serial_out(up, UART_LCR, 0x00);
845 8 : id1 = serial_icr_read(up, UART_ID1);
846 8 : id2 = serial_icr_read(up, UART_ID2);
847 8 : id3 = serial_icr_read(up, UART_ID3);
848 8 : rev = serial_icr_read(up, UART_REV);
849 :
850 : DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
851 :
852 40 : if (id1 == 0x16 && id2 == 0xC9 &&
853 : (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
854 4 : up->port.type = PORT_16C950;
855 :
856 : /*
857 : * Enable work around for the Oxford Semiconductor 952 rev B
858 : * chip which causes it to seriously miscalculate baud rates
859 : * when DLL is 0.
860 : */
861 16 : if (id3 == 0x52 && rev == 0x01)
862 8 : up->bugs |= UART_BUG_QUOT;
863 4 : return;
864 : }
865 :
866 : /*
867 : * We check for a XR16C850 by setting DLL and DLM to 0, and then
868 : * reading back DLL and DLM. The chip type depends on the DLM
869 : * value read back:
870 : * 0x10 - XR16C850 and the DLL contains the chip revision.
871 : * 0x12 - XR16C2850.
872 : * 0x14 - XR16C854.
873 : */
874 8 : id1 = autoconfig_read_divisor_id(up);
875 : DEBUG_AUTOCONF("850id=%04x ", id1);
876 :
877 4 : id2 = id1 >> 8;
878 24 : if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
879 4 : up->port.type = PORT_16850;
880 4 : return;
881 : }
882 :
883 : /*
884 : * It wasn't an XR16C850.
885 : *
886 : * We distinguish between the '654 and the '650 by counting
887 : * how many bytes are in the FIFO. I'm using this for now,
888 : * since that's the technique that was sent to me in the
889 : * serial driver update, but I'm not convinced this works.
890 : * I've had problems doing this in the past. -TYT
891 : */
892 16 : if (size_fifo(up) == 64)
893 4 : up->port.type = PORT_16654;
894 : else
895 4 : up->port.type = PORT_16650V2;
896 4 : }
897 :
898 : /*
899 : * We detected a chip without a FIFO. Only two fall into
900 : * this category - the original 8250 and the 16450. The
901 : * 16450 has a scratch register (accessible with LCR=0)
902 : */
903 : static void autoconfig_8250(struct uart_8250_port *up)
904 : {
905 4 : unsigned char scratch, status1, status2;
906 4 :
907 8 : up->port.type = PORT_8250;
908 4 :
909 32 : scratch = serial_in(up, UART_SCR);
910 36 : serial_outp(up, UART_SCR, 0xa5);
911 28 : status1 = serial_in(up, UART_SCR);
912 32 : serial_outp(up, UART_SCR, 0x5a);
913 28 : status2 = serial_in(up, UART_SCR);
914 32 : serial_outp(up, UART_SCR, scratch);
915 :
916 16 : if (status1 == 0xa5 && status2 == 0x5a)
917 4 : up->port.type = PORT_16450;
918 4 : }
919 :
920 : static int broken_efr(struct uart_8250_port *up)
921 : {
922 4 : /*
923 4 : * Exar ST16C2550 "A2" devices incorrectly detect as
924 : * having an EFR, and report an ID of 0x0201. See
925 : * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
926 : */
927 32 : if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
928 4 : return 1;
929 :
930 8 : return 0;
931 : }
932 :
933 : /*
934 : * We know that the chip has FIFOs. Does it have an EFR? The
935 : * EFR is located in the same register position as the IIR and
936 : * we know the top two bits of the IIR are currently set. The
937 : * EFR should contain zero. Try to read the EFR.
938 : */
939 : static void autoconfig_16550a(struct uart_8250_port *up)
940 : {
941 4 : unsigned char status1, status2;
942 4 : unsigned int iersave;
943 4 :
944 8 : up->port.type = PORT_16550A;
945 12 : up->capabilities |= UART_CAP_FIFO;
946 4 :
947 4 : /*
948 4 : * Check for presence of the EFR when DLAB is set.
949 4 : * Only ST16C650V1 UARTs pass this test.
950 4 : */
951 36 : serial_outp(up, UART_LCR, UART_LCR_DLAB);
952 36 : if (serial_in(up, UART_EFR) == 0) {
953 36 : serial_outp(up, UART_EFR, 0xA8);
954 36 : if (serial_in(up, UART_EFR) != 0) {
955 4 : DEBUG_AUTOCONF("EFRv1 ");
956 8 : up->port.type = PORT_16650;
957 12 : up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
958 : } else {
959 : DEBUG_AUTOCONF("Motorola 8xxx DUART ");
960 : }
961 32 : serial_outp(up, UART_EFR, 0);
962 4 : return;
963 : }
964 :
965 : /*
966 : * Maybe it requires 0xbf to be written to the LCR.
967 : * (other ST16C650V2 UARTs, TI16C752A, etc)
968 : */
969 32 : serial_outp(up, UART_LCR, 0xBF);
970 52 : if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
971 : DEBUG_AUTOCONF("EFRv2 ");
972 16 : autoconfig_has_efr(up);
973 4 : return;
974 : }
975 :
976 : /*
977 : * Check for a National Semiconductor SuperIO chip.
978 : * Attempt to switch to bank 2, read the value of the LOOP bit
979 : * from EXCR1. Switch back to bank 0, change it in MCR. Then
980 : * switch back to bank 2, read it from EXCR1 again and check
981 : * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
982 : */
983 64 : serial_outp(up, UART_LCR, 0);
984 56 : status1 = serial_in(up, UART_MCR);
985 64 : serial_outp(up, UART_LCR, 0xE0);
986 56 : status2 = serial_in(up, 0x02); /* EXCR1 */
987 :
988 16 : if (!((status2 ^ status1) & UART_MCR_LOOP)) {
989 64 : serial_outp(up, UART_LCR, 0);
990 64 : serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
991 64 : serial_outp(up, UART_LCR, 0xE0);
992 56 : status2 = serial_in(up, 0x02); /* EXCR1 */
993 64 : serial_outp(up, UART_LCR, 0);
994 64 : serial_outp(up, UART_MCR, status1);
995 :
996 16 : if ((status2 ^ status1) & UART_MCR_LOOP) {
997 : unsigned short quot;
998 :
999 64 : serial_outp(up, UART_LCR, 0xE0);
1000 :
1001 20 : quot = serial_dl_read(up);
1002 4 : quot <<= 3;
1003 :
1004 28 : status1 = serial_in(up, 0x04); /* EXCR2 */
1005 4 : status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1006 4 : status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1007 32 : serial_outp(up, 0x04, status1);
1008 :
1009 8 : serial_dl_write(up, quot);
1010 :
1011 32 : serial_outp(up, UART_LCR, 0);
1012 :
1013 4 : up->port.uartclk = 921600*16;
1014 4 : up->port.type = PORT_NS16550A;
1015 8 : up->capabilities |= UART_NATSEMI;
1016 4 : return;
1017 : }
1018 : }
1019 :
1020 : /*
1021 : * No EFR. Try to detect a TI16750, which only sets bit 5 of
1022 : * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1023 : * Try setting it with and without DLAB set. Cheap clones
1024 : * set bit 5 without DLAB set.
1025 : */
1026 64 : serial_outp(up, UART_LCR, 0);
1027 64 : serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1028 56 : status1 = serial_in(up, UART_IIR) >> 5;
1029 64 : serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1030 64 : serial_outp(up, UART_LCR, UART_LCR_DLAB);
1031 64 : serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1032 56 : status2 = serial_in(up, UART_IIR) >> 5;
1033 64 : serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1034 64 : serial_outp(up, UART_LCR, 0);
1035 :
1036 : DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1037 :
1038 32 : if (status1 == 6 && status2 == 7) {
1039 8 : up->port.type = PORT_16750;
1040 16 : up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1041 8 : return;
1042 : }
1043 :
1044 : /*
1045 : * Try writing and reading the UART_IER_UUE bit (b6).
1046 : * If it works, this is probably one of the Xscale platform's
1047 : * internal UARTs.
1048 : * We're going to explicitly set the UUE bit to 0 before
1049 : * trying to write and read a 1 just to make sure it's not
1050 : * already a 1 and maybe locked there before we even start start.
1051 : */
1052 48 : iersave = serial_in(up, UART_IER);
1053 64 : serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1054 64 : if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1055 : /*
1056 : * OK it's in a known zero state, try writing and reading
1057 : * without disturbing the current state of the other bits.
1058 : */
1059 64 : serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1060 64 : if (serial_in(up, UART_IER) & UART_IER_UUE) {
1061 : /*
1062 : * It's an Xscale.
1063 : * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1064 : */
1065 : DEBUG_AUTOCONF("Xscale ");
1066 8 : up->port.type = PORT_XSCALE;
1067 16 : up->capabilities |= UART_CAP_UUE;
1068 8 : return;
1069 : }
1070 : } else {
1071 : /*
1072 : * If we got here we couldn't force the IER_UUE bit to 0.
1073 : * Log it and continue.
1074 : */
1075 : DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1076 : }
1077 64 : serial_outp(up, UART_IER, iersave);
1078 8 : }
1079 :
1080 : /*
1081 : * This routine is called by rs_init() to initialize a specific serial
1082 : * port. It determines what type of UART chip this serial port is
1083 : * using: 8250, 16450, 16550, 16550A. The important question is
1084 : * whether or not this UART is a 16550A or not, since this will
1085 : * determine whether or not we can use its FIFO features or not.
1086 : */
1087 : static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1088 : {
1089 4 : unsigned char status1, scratch, scratch2, scratch3;
1090 4 : unsigned char save_lcr, save_mcr;
1091 4 : unsigned long flags;
1092 4 :
1093 28 : if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1094 8 : return;
1095 4 :
1096 4 : DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1097 4 : serial_index(&up->port), up->port.iobase, up->port.membase);
1098 4 :
1099 4 : /*
1100 4 : * We really do need global IRQs disabled here - we're going to
1101 4 : * be frobbing the chips IRQ enable register to see if it exists.
1102 4 : */
1103 16 : spin_lock_irqsave(&up->port.lock, flags);
1104 4 :
1105 4 : up->capabilities = 0;
1106 4 : up->bugs = 0;
1107 :
1108 8 : if (!(up->port.flags & UPF_BUGGY_UART)) {
1109 : /*
1110 : * Do a simple existence test first; if we fail this,
1111 : * there's no point trying anything else.
1112 : *
1113 : * 0x80 is used as a nonsense port to prevent against
1114 : * false positives due to ISA bus float. The
1115 : * assumption is that 0x80 is a non-existent port;
1116 : * which should be safe since include/asm/io.h also
1117 : * makes this assumption.
1118 : *
1119 : * Note: this is safe as long as MCR bit 4 is clear
1120 : * and the device is in "PC" mode.
1121 : */
1122 28 : scratch = serial_inp(up, UART_IER);
1123 32 : serial_outp(up, UART_IER, 0);
1124 : #ifdef __i386__
1125 : outb(0xff, 0x080);
1126 : #endif
1127 : /*
1128 : * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1129 : * 16C754B) allow only to modify them if an EFR bit is set.
1130 : */
1131 28 : scratch2 = serial_inp(up, UART_IER) & 0x0f;
1132 32 : serial_outp(up, UART_IER, 0x0F);
1133 : #ifdef __i386__
1134 : outb(0, 0x080);
1135 : #endif
1136 28 : scratch3 = serial_inp(up, UART_IER) & 0x0f;
1137 32 : serial_outp(up, UART_IER, scratch);
1138 16 : if (scratch2 != 0 || scratch3 != 0x0F) {
1139 : /*
1140 : * We failed; there's nothing here
1141 : */
1142 : DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1143 : scratch2, scratch3);
1144 4 : goto out;
1145 : }
1146 : }
1147 :
1148 28 : save_mcr = serial_in(up, UART_MCR);
1149 28 : save_lcr = serial_in(up, UART_LCR);
1150 :
1151 : /*
1152 : * Check to see if a UART is really there. Certain broken
1153 : * internal modems based on the Rockwell chipset fail this
1154 : * test, because they apparently don't implement the loopback
1155 : * test mode. So this test is skipped on the COM 1 through
1156 : * COM 4 ports. This *should* be safe, since no board
1157 : * manufacturer would be stupid enough to design a board
1158 : * that conflicts with COM 1-4 --- we hope!
1159 : */
1160 8 : if (!(up->port.flags & UPF_SKIP_TEST)) {
1161 32 : serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1162 28 : status1 = serial_inp(up, UART_MSR) & 0xF0;
1163 32 : serial_outp(up, UART_MCR, save_mcr);
1164 8 : if (status1 != 0x90) {
1165 : DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1166 : status1);
1167 4 : goto out;
1168 : }
1169 : }
1170 :
1171 : /*
1172 : * We're pretty sure there's a port here. Lets find out what
1173 : * type of port it is. The IIR top two bits allows us to find
1174 : * out if it's 8250 or 16450, 16550, 16550A or later. This
1175 : * determines what we test for next.
1176 : *
1177 : * We also initialise the EFR (if any) to zero for later. The
1178 : * EFR occupies the same register location as the FCR and IIR.
1179 : */
1180 32 : serial_outp(up, UART_LCR, 0xBF);
1181 32 : serial_outp(up, UART_EFR, 0);
1182 32 : serial_outp(up, UART_LCR, 0);
1183 :
1184 32 : serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1185 28 : scratch = serial_in(up, UART_IIR) >> 6;
1186 :
1187 : DEBUG_AUTOCONF("iir=%d ", scratch);
1188 :
1189 4 : switch (scratch) {
1190 16 : case 0:
1191 8 : autoconfig_8250(up);
1192 4 : break;
1193 16 : case 1:
1194 4 : up->port.type = PORT_UNKNOWN;
1195 4 : break;
1196 16 : case 2:
1197 4 : up->port.type = PORT_16550;
1198 4 : break;
1199 16 : case 3:
1200 20 : autoconfig_16550a(up);
1201 4 : break;
1202 4 : }
1203 :
1204 4 : #ifdef CONFIG_SERIAL_8250_RSA
1205 : /*
1206 : * Only probe for RSA ports if we got the region.
1207 : */
1208 : if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1209 : int i;
1210 :
1211 : for (i = 0 ; i < probe_rsa_count; ++i) {
1212 : if (probe_rsa[i] == up->port.iobase &&
1213 : __enable_rsa(up)) {
1214 : up->port.type = PORT_RSA;
1215 : break;
1216 : }
1217 : }
1218 : }
1219 : #endif
1220 :
1221 : #ifdef CONFIG_SERIAL_8250_AU1X00
1222 : /* if access method is AU, it is a 16550 with a quirk */
1223 : if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1224 : up->bugs |= UART_BUG_NOMSR;
1225 : #endif
1226 :
1227 96 : serial_outp(up, UART_LCR, save_lcr);
1228 :
1229 36 : if (up->capabilities != uart_config[up->port.type].flags) {
1230 32 : printk(KERN_WARNING
1231 : "ttyS%d: detected caps %08x should be %08x\n",
1232 : serial_index(&up->port), up->capabilities,
1233 : uart_config[up->port.type].flags);
1234 : }
1235 :
1236 16 : up->port.fifosize = uart_config[up->port.type].fifo_size;
1237 16 : up->capabilities = uart_config[up->port.type].flags;
1238 16 : up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1239 :
1240 32 : if (up->port.type == PORT_UNKNOWN)
1241 16 : goto out;
1242 :
1243 : /*
1244 : * Reset the UART.
1245 : */
1246 : #ifdef CONFIG_SERIAL_8250_RSA
1247 : if (up->port.type == PORT_RSA)
1248 : serial_outp(up, UART_RSA_FRR, 0);
1249 : #endif
1250 128 : serial_outp(up, UART_MCR, save_mcr);
1251 32 : serial8250_clear_fifos(up);
1252 24 : serial_in(up, UART_RX);
1253 12 : if (up->capabilities & UART_CAP_UUE)
1254 32 : serial_outp(up, UART_IER, UART_IER_UUE);
1255 : else
1256 32 : serial_outp(up, UART_IER, 0);
1257 :
1258 : out:
1259 44 : spin_unlock_irqrestore(&up->port.lock, flags);
1260 4 : DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1261 : }
1262 :
1263 : static void autoconfig_irq(struct uart_8250_port *up)
1264 : {
1265 6 : unsigned char save_mcr, save_ier;
1266 12 : unsigned char save_ICP = 0;
1267 12 : unsigned int ICP = 0;
1268 6 : unsigned long irqs;
1269 6 : int irq;
1270 6 :
1271 18 : if (up->port.flags & UPF_FOURPORT) {
1272 12 : ICP = (up->port.iobase & 0xfe0) | 0x1f;
1273 18 : save_ICP = inb_p(ICP);
1274 12 : outb_p(0x80, ICP);
1275 12 : (void) inb_p(ICP);
1276 : }
1277 :
1278 : /* forget possible initially masked and pending IRQ */
1279 24 : probe_irq_off(probe_irq_on());
1280 84 : save_mcr = serial_inp(up, UART_MCR);
1281 84 : save_ier = serial_inp(up, UART_IER);
1282 96 : serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1283 :
1284 12 : irqs = probe_irq_on();
1285 96 : serial_outp(up, UART_MCR, 0);
1286 12 : udelay(10);
1287 24 : if (up->port.flags & UPF_FOURPORT) {
1288 96 : serial_outp(up, UART_MCR,
1289 : UART_MCR_DTR | UART_MCR_RTS);
1290 : } else {
1291 96 : serial_outp(up, UART_MCR,
1292 : UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1293 : }
1294 96 : serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1295 72 : (void)serial_inp(up, UART_LSR);
1296 72 : (void)serial_inp(up, UART_RX);
1297 72 : (void)serial_inp(up, UART_IIR);
1298 72 : (void)serial_inp(up, UART_MSR);
1299 96 : serial_outp(up, UART_TX, 0xFF);
1300 12 : udelay(20);
1301 12 : irq = probe_irq_off(irqs);
1302 :
1303 96 : serial_outp(up, UART_MCR, save_mcr);
1304 96 : serial_outp(up, UART_IER, save_ier);
1305 :
1306 24 : if (up->port.flags & UPF_FOURPORT)
1307 24 : outb_p(save_ICP, ICP);
1308 :
1309 108 : up->port.irq = (irq > 0) ? irq : 0;
1310 18 : }
1311 :
1312 : static inline void __stop_tx(struct uart_8250_port *p)
1313 : {
1314 228 : if (p->ier & UART_IER_THRI) {
1315 152 : p->ier &= ~UART_IER_THRI;
1316 684 : serial_out(p, UART_IER, p->ier);
1317 : }
1318 76 : }
1319 :
1320 : static void serial8250_stop_tx(struct uart_port *port)
1321 : {
1322 56 : struct uart_8250_port *up = (struct uart_8250_port *)port;
1323 :
1324 56 : __stop_tx(up);
1325 :
1326 : /*
1327 : * We really want to stop the transmitter from sending.
1328 : */
1329 56 : if (up->port.type == PORT_16C950) {
1330 56 : up->acr |= UART_ACR_TXDIS;
1331 84 : serial_icr_write(up, UART_ACR, up->acr);
1332 : }
1333 56 : }
1334 :
1335 : static void transmit_chars(struct uart_8250_port *up);
1336 :
1337 : static void serial8250_start_tx(struct uart_port *port)
1338 : {
1339 24 : struct uart_8250_port *up = (struct uart_8250_port *)port;
1340 12 :
1341 48 : if (!(up->ier & UART_IER_THRI)) {
1342 24 : up->ier |= UART_IER_THRI;
1343 108 : serial_out(up, UART_IER, up->ier);
1344 :
1345 36 : if (up->bugs & UART_BUG_TXEN) {
1346 : unsigned char lsr;
1347 84 : lsr = serial_in(up, UART_LSR);
1348 24 : up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1349 84 : if ((up->port.type == PORT_RM9000) ?
1350 : (lsr & UART_LSR_THRE) :
1351 : (lsr & UART_LSR_TEMT))
1352 72 : transmit_chars(up);
1353 : }
1354 : }
1355 :
1356 : /*
1357 : * Re-enable the transmitter if we disabled it.
1358 : */
1359 120 : if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1360 48 : up->acr &= ~UART_ACR_TXDIS;
1361 72 : serial_icr_write(up, UART_ACR, up->acr);
1362 : }
1363 36 : }
1364 :
1365 : static void serial8250_stop_rx(struct uart_port *port)
1366 : {
1367 8 : struct uart_8250_port *up = (struct uart_8250_port *)port;
1368 :
1369 8 : up->ier &= ~UART_IER_RLSI;
1370 4 : up->port.read_status_mask &= ~UART_LSR_DR;
1371 36 : serial_out(up, UART_IER, up->ier);
1372 4 : }
1373 :
1374 : static void serial8250_enable_ms(struct uart_port *port)
1375 : {
1376 4 : struct uart_8250_port *up = (struct uart_8250_port *)port;
1377 :
1378 : /* no MSR capabilities */
1379 6 : if (up->bugs & UART_BUG_NOMSR)
1380 2 : return;
1381 :
1382 4 : up->ier |= UART_IER_MSI;
1383 18 : serial_out(up, UART_IER, up->ier);
1384 2 : }
1385 :
1386 : static void
1387 : receive_chars(struct uart_8250_port *up, unsigned int *status)
1388 : {
1389 24 : struct tty_struct *tty = up->port.state->port.tty;
1390 24 : unsigned char ch, lsr = *status;
1391 24 : int max_count = 256;
1392 24 : char flag;
1393 12 :
1394 12 : do {
1395 60 : if (likely(lsr & UART_LSR_DR))
1396 96 : ch = serial_inp(up, UART_RX);
1397 12 : else
1398 12 : /*
1399 12 : * Intel 82571 has a Serial Over Lan device that will
1400 12 : * set UART_LSR_BI without setting UART_LSR_DR when
1401 : * it receives a break. To avoid reading from the
1402 : * receive buffer without UART_LSR_DR bit set, we
1403 : * just force the read character to be 0
1404 : */
1405 12 : ch = 0;
1406 :
1407 12 : flag = TTY_NORMAL;
1408 12 : up->port.icount.rx++;
1409 :
1410 24 : lsr |= up->lsr_saved_flags;
1411 12 : up->lsr_saved_flags = 0;
1412 :
1413 48 : if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1414 : /*
1415 : * For statistics only
1416 : */
1417 24 : if (lsr & UART_LSR_BI) {
1418 12 : lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1419 12 : up->port.icount.brk++;
1420 : /*
1421 : * We do the SysRQ and SAK checking
1422 : * here because otherwise the break
1423 : * may get masked by ignore_status_mask
1424 : * or read_status_mask.
1425 : */
1426 48 : if (uart_handle_break(&up->port))
1427 12 : goto ignore_char;
1428 24 : } else if (lsr & UART_LSR_PE)
1429 12 : up->port.icount.parity++;
1430 24 : else if (lsr & UART_LSR_FE)
1431 12 : up->port.icount.frame++;
1432 48 : if (lsr & UART_LSR_OE)
1433 24 : up->port.icount.overrun++;
1434 :
1435 : /*
1436 : * Mask off conditions which should be ignored.
1437 : */
1438 24 : lsr &= up->port.read_status_mask;
1439 :
1440 48 : if (lsr & UART_LSR_BI) {
1441 : DEBUG_INTR("handling break....");
1442 24 : flag = TTY_BREAK;
1443 48 : } else if (lsr & UART_LSR_PE)
1444 24 : flag = TTY_PARITY;
1445 48 : else if (lsr & UART_LSR_FE)
1446 24 : flag = TTY_FRAME;
1447 : }
1448 72 : if (uart_handle_sysrq_char(&up->port, ch))
1449 12 : goto ignore_char;
1450 :
1451 48 : uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1452 :
1453 12 : ignore_char:
1454 252 : lsr = serial_inp(up, UART_LSR);
1455 216 : } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1456 72 : spin_unlock(&up->port.lock);
1457 48 : tty_flip_buffer_push(tty);
1458 24 : spin_lock(&up->port.lock);
1459 12 : *status = lsr;
1460 48 : }
1461 :
1462 : static void transmit_chars(struct uart_8250_port *up)
1463 : {
1464 48 : struct circ_buf *xmit = &up->port.state->xmit;
1465 60 : int count;
1466 24 :
1467 48 : if (up->port.x_char) {
1468 192 : serial_outp(up, UART_TX, up->port.x_char);
1469 24 : up->port.icount.tx++;
1470 24 : up->port.x_char = 0;
1471 24 : return;
1472 : }
1473 96 : if (uart_tx_stopped(&up->port)) {
1474 72 : serial8250_stop_tx(&up->port);
1475 24 : return;
1476 : }
1477 48 : if (uart_circ_empty(xmit)) {
1478 48 : __stop_tx(up);
1479 24 : return;
1480 : }
1481 :
1482 48 : count = up->tx_loadsz;
1483 24 : do {
1484 216 : serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1485 24 : xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1486 24 : up->port.icount.tx++;
1487 48 : if (uart_circ_empty(xmit))
1488 24 : break;
1489 72 : } while (--count > 0);
1490 :
1491 72 : if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1492 24 : uart_write_wakeup(&up->port);
1493 :
1494 : DEBUG_INTR("THRE...");
1495 24 :
1496 48 : if (uart_circ_empty(xmit))
1497 48 : __stop_tx(up);
1498 48 : }
1499 :
1500 : static unsigned int check_modem_status(struct uart_8250_port *up)
1501 : {
1502 208 : unsigned int status = serial_in(up, UART_MSR);
1503 26 :
1504 52 : status |= up->msr_saved_flags;
1505 26 : up->msr_saved_flags = 0;
1506 182 : if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1507 : up->port.state != NULL) {
1508 52 : if (status & UART_MSR_TERI)
1509 26 : up->port.icount.rng++;
1510 52 : if (status & UART_MSR_DDSR)
1511 26 : up->port.icount.dsr++;
1512 52 : if (status & UART_MSR_DDCD)
1513 52 : uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1514 104 : if (status & UART_MSR_DCTS)
1515 104 : uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1516 :
1517 78 : wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1518 : }
1519 :
1520 78 : return status;
1521 : }
1522 :
1523 : /*
1524 : * This handles the interrupt from one port.
1525 : */
1526 : static void serial8250_handle_port(struct uart_8250_port *up)
1527 : {
1528 12 : unsigned int status;
1529 12 : unsigned long flags;
1530 12 :
1531 36 : spin_lock_irqsave(&up->port.lock, flags);
1532 :
1533 72 : status = serial_inp(up, UART_LSR);
1534 :
1535 : DEBUG_INTR("status = %x...", status);
1536 :
1537 24 : if (status & (UART_LSR_DR | UART_LSR_BI))
1538 24 : receive_chars(up, &status);
1539 96 : check_modem_status(up);
1540 24 : if (status & UART_LSR_THRE)
1541 72 : transmit_chars(up);
1542 :
1543 48 : spin_unlock_irqrestore(&up->port.lock, flags);
1544 12 : }
1545 :
1546 : /*
1547 : * This is the serial driver's interrupt routine.
1548 : *
1549 : * Arjan thinks the old way was overly complex, so it got simplified.
1550 : * Alan disagrees, saying that need the complexity to handle the weird
1551 : * nature of ISA shared interrupts. (This is a special exception.)
1552 : *
1553 : * In order to handle ISA shared interrupts properly, we need to check
1554 : * that all ports have been serviced, and therefore the ISA interrupt
1555 : * line has been de-asserted.
1556 : *
1557 : * This means we need to loop through all ports. checking that they
1558 : * don't have an interrupt pending.
1559 : */
1560 : static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1561 : {
1562 24 : struct irq_info *i = dev_id;
1563 24 : struct list_head *l, *end = NULL;
1564 36 : int pass_counter = 0, handled = 0;
1565 12 :
1566 12 : DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1567 12 :
1568 36 : spin_lock(&i->lock);
1569 12 :
1570 24 : l = i->head;
1571 12 : do {
1572 12 : struct uart_8250_port *up;
1573 : unsigned int iir;
1574 :
1575 24 : up = list_entry(l, struct uart_8250_port, list);
1576 :
1577 72 : iir = serial_in(up, UART_IIR);
1578 24 : if (!(iir & UART_IIR_NO_INT)) {
1579 24 : serial8250_handle_port(up);
1580 :
1581 12 : handled = 1;
1582 :
1583 12 : end = NULL;
1584 48 : } else if (up->port.iotype == UPIO_DWAPB &&
1585 : (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1586 : /* The DesignWare APB UART has an Busy Detect (0x07)
1587 : * interrupt meaning an LCR write attempt occured while the
1588 : * UART was busy. The interrupt must be cleared by reading
1589 : * the UART status register (USR) and the LCR re-written. */
1590 : unsigned int status;
1591 12 : status = *(volatile u32 *)up->port.private_data;
1592 108 : serial_out(up, UART_LCR, up->lcr);
1593 :
1594 12 : handled = 1;
1595 :
1596 12 : end = NULL;
1597 24 : } else if (end == NULL)
1598 12 : end = l;
1599 :
1600 24 : l = l->next;
1601 :
1602 168 : if (l == i->head && pass_counter++ > PASS_LIMIT) {
1603 : /* If we hit this, we're dead. */
1604 24 : printk(KERN_ERR "serial8250: too much work for "
1605 : "irq%d\n", irq);
1606 24 : break;
1607 : }
1608 48 : } while (l != end);
1609 :
1610 72 : spin_unlock(&i->lock);
1611 :
1612 : DEBUG_INTR("end.\n");
1613 :
1614 36 : return IRQ_RETVAL(handled);
1615 : }
1616 :
1617 : /*
1618 : * To support ISA shared interrupts, we need to have one interrupt
1619 : * handler that ensures that the IRQ line has been deasserted
1620 : * before returning. Failing to do this will result in the IRQ
1621 : * line being stuck active, and, since ISA irqs are edge triggered,
1622 : * no more IRQs will be seen.
1623 : */
1624 : static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1625 : {
1626 42 : spin_lock_irq(&i->lock);
1627 14 :
1628 70 : if (!list_empty(i->head)) {
1629 42 : if (i->head == &up->list)
1630 14 : i->head = i->head->next;
1631 28 : list_del(&up->list);
1632 : } else {
1633 98 : BUG_ON(i->head != &up->list);
1634 14 : i->head = NULL;
1635 : }
1636 56 : spin_unlock_irq(&i->lock);
1637 : /* List empty so throw away the hash node */
1638 42 : if (i->head == NULL) {
1639 28 : hlist_del(&i->node);
1640 14 : kfree(i);
1641 : }
1642 28 : }
1643 :
1644 : static int serial_link_irq_chain(struct uart_8250_port *up)
1645 : {
1646 6 : struct hlist_head *h;
1647 6 : struct hlist_node *n;
1648 6 : struct irq_info *i;
1649 42 : int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1650 6 :
1651 12 : mutex_lock(&hash_mutex);
1652 6 :
1653 12 : h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1654 :
1655 42 : hlist_for_each(n, h) {
1656 24 : i = hlist_entry(n, struct irq_info, node);
1657 24 : if (i->irq == up->port.irq)
1658 6 : break;
1659 : }
1660 :
1661 18 : if (n == NULL) {
1662 18 : i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1663 12 : if (i == NULL) {
1664 6 : mutex_unlock(&hash_mutex);
1665 6 : return -ENOMEM;
1666 : }
1667 24 : spin_lock_init(&i->lock);
1668 6 : i->irq = up->port.irq;
1669 12 : hlist_add_head(&i->node, h);
1670 : }
1671 12 : mutex_unlock(&hash_mutex);
1672 :
1673 24 : spin_lock_irq(&i->lock);
1674 :
1675 18 : if (i->head) {
1676 12 : list_add(&up->list, i->head);
1677 12 : spin_unlock_irq(&i->lock);
1678 :
1679 6 : ret = 0;
1680 : } else {
1681 12 : INIT_LIST_HEAD(&up->list);
1682 6 : i->head = &up->list;
1683 12 : spin_unlock_irq(&i->lock);
1684 6 : irq_flags |= up->port.irqflags;
1685 12 : ret = request_irq(up->port.irq, serial8250_interrupt,
1686 : irq_flags, "serial", i);
1687 12 : if (ret < 0)
1688 18 : serial_do_unlink(i, up);
1689 : }
1690 :
1691 18 : return ret;
1692 : }
1693 :
1694 : static void serial_unlink_irq_chain(struct uart_8250_port *up)
1695 : {
1696 4 : struct irq_info *i;
1697 4 : struct hlist_node *n;
1698 4 : struct hlist_head *h;
1699 4 :
1700 8 : mutex_lock(&hash_mutex);
1701 4 :
1702 8 : h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1703 :
1704 28 : hlist_for_each(n, h) {
1705 16 : i = hlist_entry(n, struct irq_info, node);
1706 16 : if (i->irq == up->port.irq)
1707 4 : break;
1708 : }
1709 :
1710 28 : BUG_ON(n == NULL);
1711 28 : BUG_ON(i->head == NULL);
1712 :
1713 20 : if (list_empty(i->head))
1714 8 : free_irq(up->port.irq, i);
1715 :
1716 24 : serial_do_unlink(i, up);
1717 4 : mutex_unlock(&hash_mutex);
1718 4 : }
1719 :
1720 : /* Base timer interval for polling */
1721 : static inline int poll_timeout(int timeout)
1722 : {
1723 60 : return timeout > 6 ? (timeout / 2 - 2) : 1;
1724 : }
1725 :
1726 : /*
1727 : * This function is used to handle ports that do not have an
1728 : * interrupt. This doesn't work very well for 16450's, but gives
1729 : * barely passable results for a 16550A. (Although at the expense
1730 : * of much CPU overhead).
1731 : */
1732 : static void serial8250_timeout(unsigned long data)
1733 : {
1734 0 : struct uart_8250_port *up = (struct uart_8250_port *)data;
1735 0 : unsigned int iir;
1736 0 :
1737 0 : iir = serial_in(up, UART_IIR);
1738 0 : if (!(iir & UART_IIR_NO_INT))
1739 0 : serial8250_handle_port(up);
1740 0 : mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1741 0 : }
1742 :
1743 : static void serial8250_backup_timeout(unsigned long data)
1744 : {
1745 0 : struct uart_8250_port *up = (struct uart_8250_port *)data;
1746 0 : unsigned int iir, ier = 0, lsr;
1747 0 : unsigned long flags;
1748 0 :
1749 0 : /*
1750 0 : * Must disable interrupts or else we risk racing with the interrupt
1751 0 : * based handler.
1752 : */
1753 0 : if (is_real_interrupt(up->port.irq)) {
1754 0 : ier = serial_in(up, UART_IER);
1755 0 : serial_out(up, UART_IER, 0);
1756 : }
1757 :
1758 0 : iir = serial_in(up, UART_IIR);
1759 :
1760 : /*
1761 : * This should be a safe test for anyone who doesn't trust the
1762 : * IIR bits on their UART, but it's specifically designed for
1763 : * the "Diva" UART used on the management processor on many HP
1764 : * ia64 and parisc boxes.
1765 : */
1766 0 : spin_lock_irqsave(&up->port.lock, flags);
1767 0 : lsr = serial_in(up, UART_LSR);
1768 0 : up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1769 0 : spin_unlock_irqrestore(&up->port.lock, flags);
1770 0 : if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1771 : (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1772 : (lsr & UART_LSR_THRE)) {
1773 0 : iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1774 0 : iir |= UART_IIR_THRI;
1775 : }
1776 :
1777 0 : if (!(iir & UART_IIR_NO_INT))
1778 0 : serial8250_handle_port(up);
1779 :
1780 0 : if (is_real_interrupt(up->port.irq))
1781 0 : serial_out(up, UART_IER, ier);
1782 :
1783 : /* Standard timer interval plus 0.2s to keep the port running */
1784 0 : mod_timer(&up->timer,
1785 : jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1786 0 : }
1787 :
1788 : static unsigned int serial8250_tx_empty(struct uart_port *port)
1789 : {
1790 4 : struct uart_8250_port *up = (struct uart_8250_port *)port;
1791 2 : unsigned long flags;
1792 2 : unsigned int lsr;
1793 2 :
1794 6 : spin_lock_irqsave(&up->port.lock, flags);
1795 12 : lsr = serial_in(up, UART_LSR);
1796 4 : up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1797 4 : spin_unlock_irqrestore(&up->port.lock, flags);
1798 :
1799 2 : return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1800 : }
1801 :
1802 : static unsigned int serial8250_get_mctrl(struct uart_port *port)
1803 : {
1804 4 : struct uart_8250_port *up = (struct uart_8250_port *)port;
1805 2 : unsigned int status;
1806 2 : unsigned int ret;
1807 :
1808 8 : status = check_modem_status(up);
1809 :
1810 2 : ret = 0;
1811 4 : if (status & UART_MSR_DCD)
1812 2 : ret |= TIOCM_CAR;
1813 4 : if (status & UART_MSR_RI)
1814 2 : ret |= TIOCM_RNG;
1815 4 : if (status & UART_MSR_DSR)
1816 2 : ret |= TIOCM_DSR;
1817 4 : if (status & UART_MSR_CTS)
1818 2 : ret |= TIOCM_CTS;
1819 2 : return ret;
1820 : }
1821 :
1822 : static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1823 : {
1824 44 : struct uart_8250_port *up = (struct uart_8250_port *)port;
1825 44 : unsigned char mcr = 0;
1826 :
1827 44 : if (mctrl & TIOCM_RTS)
1828 22 : mcr |= UART_MCR_RTS;
1829 44 : if (mctrl & TIOCM_DTR)
1830 22 : mcr |= UART_MCR_DTR;
1831 44 : if (mctrl & TIOCM_OUT1)
1832 22 : mcr |= UART_MCR_OUT1;
1833 44 : if (mctrl & TIOCM_OUT2)
1834 22 : mcr |= UART_MCR_OUT2;
1835 44 : if (mctrl & TIOCM_LOOP)
1836 22 : mcr |= UART_MCR_LOOP;
1837 :
1838 88 : mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1839 :
1840 176 : serial_out(up, UART_MCR, mcr);
1841 22 : }
1842 :
1843 : static void serial8250_break_ctl(struct uart_port *port, int break_state)
1844 : {
1845 4 : struct uart_8250_port *up = (struct uart_8250_port *)port;
1846 2 : unsigned long flags;
1847 2 :
1848 6 : spin_lock_irqsave(&up->port.lock, flags);
1849 4 : if (break_state == -1)
1850 4 : up->lcr |= UART_LCR_SBC;
1851 : else
1852 4 : up->lcr &= ~UART_LCR_SBC;
1853 18 : serial_out(up, UART_LCR, up->lcr);
1854 4 : spin_unlock_irqrestore(&up->port.lock, flags);
1855 2 : }
1856 :
1857 : /*
1858 : * Wait for transmitter & holding register to empty
1859 : */
1860 : static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1861 : {
1862 4 : unsigned int status, tmout = 10000;
1863 4 :
1864 2 : /* Wait up to 10ms for the character(s) to be sent. */
1865 2 : do {
1866 14 : status = serial_in(up, UART_LSR);
1867 :
1868 4 : up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1869 :
1870 6 : if (--tmout == 0)
1871 2 : break;
1872 2 : udelay(1);
1873 4 : } while ((status & bits) != bits);
1874 :
1875 2 : /* Wait up to 1s for flow control if necessary */
1876 4 : if (up->port.flags & UPF_CONS_FLOW) {
1877 : unsigned int tmout;
1878 10 : for (tmout = 1000000; tmout; tmout--) {
1879 18 : unsigned int msr = serial_in(up, UART_MSR);
1880 8 : up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1881 4 : if (msr & UART_MSR_CTS)
1882 2 : break;
1883 2 : udelay(1);
1884 4 : touch_nmi_watchdog();
1885 : }
1886 4 : }
1887 : }
1888 :
1889 : #ifdef CONFIG_CONSOLE_POLL
1890 : /*
1891 : * Console polling routines for writing and reading from the uart while
1892 : * in an interrupt or debug context.
1893 : */
1894 :
1895 : static int serial8250_get_poll_char(struct uart_port *port)
1896 : {
1897 : struct uart_8250_port *up = (struct uart_8250_port *)port;
1898 : unsigned char lsr = serial_inp(up, UART_LSR);
1899 :
1900 : while (!(lsr & UART_LSR_DR))
1901 : lsr = serial_inp(up, UART_LSR);
1902 :
1903 : return serial_inp(up, UART_RX);
1904 : }
1905 :
1906 :
1907 : static void serial8250_put_poll_char(struct uart_port *port,
1908 : unsigned char c)
1909 : {
1910 : unsigned int ier;
1911 : struct uart_8250_port *up = (struct uart_8250_port *)port;
1912 :
1913 : /*
1914 : * First save the IER then disable the interrupts
1915 : */
1916 : ier = serial_in(up, UART_IER);
1917 : if (up->capabilities & UART_CAP_UUE)
1918 : serial_out(up, UART_IER, UART_IER_UUE);
1919 : else
1920 : serial_out(up, UART_IER, 0);
1921 :
1922 : wait_for_xmitr(up, BOTH_EMPTY);
1923 : /*
1924 : * Send the character out.
1925 : * If a LF, also do CR...
1926 : */
1927 : serial_out(up, UART_TX, c);
1928 : if (c == 10) {
1929 : wait_for_xmitr(up, BOTH_EMPTY);
1930 : serial_out(up, UART_TX, 13);
1931 : }
1932 :
1933 : /*
1934 : * Finally, wait for transmitter to become empty
1935 : * and restore the IER
1936 : */
1937 : wait_for_xmitr(up, BOTH_EMPTY);
1938 : serial_out(up, UART_IER, ier);
1939 : }
1940 :
1941 : #endif /* CONFIG_CONSOLE_POLL */
1942 :
1943 : static int serial8250_startup(struct uart_port *port)
1944 : {
1945 4 : struct uart_8250_port *up = (struct uart_8250_port *)port;
1946 2 : unsigned long flags;
1947 2 : unsigned char lsr, iir;
1948 2 : int retval;
1949 2 :
1950 4 : up->capabilities = uart_config[up->port.type].flags;
1951 4 : up->mcr = 0;
1952 2 :
1953 8 : if (up->port.iotype != up->cur_iotype)
1954 6 : set_io_from_upio(port);
1955 2 :
1956 10 : if (up->port.type == PORT_16C950) {
1957 2 : /* Wake up and initialize UART */
1958 6 : up->acr = 0;
1959 34 : serial_outp(up, UART_LCR, 0xBF);
1960 34 : serial_outp(up, UART_EFR, UART_EFR_ECB);
1961 34 : serial_outp(up, UART_IER, 0);
1962 34 : serial_outp(up, UART_LCR, 0);
1963 10 : serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1964 16 : serial_outp(up, UART_LCR, 0xBF);
1965 16 : serial_outp(up, UART_EFR, UART_EFR_ECB);
1966 16 : serial_outp(up, UART_LCR, 0);
1967 : }
1968 :
1969 : #ifdef CONFIG_SERIAL_8250_RSA
1970 : /*
1971 : * If this is an RSA port, see if we can kick it up to the
1972 : * higher speed clock.
1973 : */
1974 : enable_rsa(up);
1975 : #endif
1976 :
1977 : /*
1978 : * Clear the FIFO buffers and disable them.
1979 : * (they will be reenabled in set_termios())
1980 : */
1981 12 : serial8250_clear_fifos(up);
1982 :
1983 : /*
1984 : * Clear the interrupt registers.
1985 : */
1986 12 : (void) serial_inp(up, UART_LSR);
1987 12 : (void) serial_inp(up, UART_RX);
1988 12 : (void) serial_inp(up, UART_IIR);
1989 12 : (void) serial_inp(up, UART_MSR);
1990 :
1991 : /*
1992 : * At this point, there's no way the LSR could still be 0xff;
1993 : * if it is, then bail out, because there's likely no UART
1994 : * here.
1995 : */
1996 20 : if (!(up->port.flags & UPF_BUGGY_UART) &&
1997 : (serial_inp(up, UART_LSR) == 0xff)) {
1998 6 : printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1999 : serial_index(&up->port));
2000 2 : return -ENODEV;
2001 : }
2002 :
2003 : /*
2004 : * For a XR16C850, we need to set the trigger levels
2005 : */
2006 4 : if (up->port.type == PORT_16850) {
2007 : unsigned char fctr;
2008 :
2009 16 : serial_outp(up, UART_LCR, 0xbf);
2010 :
2011 14 : fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2012 16 : serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2013 16 : serial_outp(up, UART_TRG, UART_TRG_96);
2014 16 : serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2015 16 : serial_outp(up, UART_TRG, UART_TRG_96);
2016 :
2017 16 : serial_outp(up, UART_LCR, 0);
2018 : }
2019 :
2020 4 : if (is_real_interrupt(up->port.irq)) {
2021 : unsigned char iir1;
2022 : /*
2023 : * Test for UARTs that do not reassert THRE when the
2024 : * transmitter is idle and the interrupt has already
2025 : * been cleared. Real 16550s should always reassert
2026 : * this interrupt whenever the transmitter is idle and
2027 : * the interrupt is enabled. Delays are necessary to
2028 : * allow register changes to become visible.
2029 : */
2030 6 : spin_lock_irqsave(&up->port.lock, flags);
2031 4 : if (up->port.irqflags & IRQF_SHARED)
2032 2 : disable_irq_nosync(up->port.irq);
2033 :
2034 6 : wait_for_xmitr(up, UART_LSR_THRE);
2035 4 : serial_out_sync(up, UART_IER, UART_IER_THRI);
2036 2 : udelay(1); /* allow THRE to set */
2037 14 : iir1 = serial_in(up, UART_IIR);
2038 16 : serial_out(up, UART_IER, 0);
2039 4 : serial_out_sync(up, UART_IER, UART_IER_THRI);
2040 2 : udelay(1); /* allow a working UART time to re-assert THRE */
2041 14 : iir = serial_in(up, UART_IIR);
2042 16 : serial_out(up, UART_IER, 0);
2043 :
2044 4 : if (up->port.irqflags & IRQF_SHARED)
2045 2 : enable_irq(up->port.irq);
2046 4 : spin_unlock_irqrestore(&up->port.lock, flags);
2047 :
2048 : /*
2049 : * If the interrupt is not reasserted, setup a timer to
2050 : * kick the UART on a regular basis.
2051 : */
2052 8 : if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2053 4 : up->bugs |= UART_BUG_THRE;
2054 : pr_debug("ttyS%d - using backup timer\n",
2055 : serial_index(port));
2056 : }
2057 : }
2058 :
2059 : /*
2060 : * The above check will only give an accurate result the first time
2061 : * the port is opened so this value needs to be preserved.
2062 : */
2063 12 : if (up->bugs & UART_BUG_THRE) {
2064 4 : up->timer.function = serial8250_backup_timeout;
2065 4 : up->timer.data = (unsigned long)up;
2066 12 : mod_timer(&up->timer, jiffies +
2067 : poll_timeout(up->port.timeout) + HZ / 5);
2068 : }
2069 :
2070 : /*
2071 : * If the "interrupt" for this port doesn't correspond with any
2072 : * hardware interrupt, we use a timer-based system. The original
2073 : * driver used to do this with IRQ0.
2074 : */
2075 12 : if (!is_real_interrupt(up->port.irq)) {
2076 6 : up->timer.data = (unsigned long)up;
2077 16 : mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
2078 : } else {
2079 30 : retval = serial_link_irq_chain(up);
2080 4 : if (retval)
2081 2 : return retval;
2082 : }
2083 :
2084 : /*
2085 : * Now, initialize the UART
2086 : */
2087 32 : serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2088 :
2089 10 : spin_lock_irqsave(&up->port.lock, flags);
2090 4 : if (up->port.flags & UPF_FOURPORT) {
2091 4 : if (!is_real_interrupt(up->port.irq))
2092 2 : up->port.mctrl |= TIOCM_OUT1;
2093 : } else
2094 : /*
2095 : * Most PC uarts need OUT2 raised to enable interrupts.
2096 : */
2097 4 : if (is_real_interrupt(up->port.irq))
2098 2 : up->port.mctrl |= TIOCM_OUT2;
2099 :
2100 4 : serial8250_set_mctrl(&up->port, up->port.mctrl);
2101 :
2102 : /* Serial over Lan (SoL) hack:
2103 : Intel 8257x Gigabit ethernet chips have a
2104 : 16550 emulation, to be used for Serial Over Lan.
2105 : Those chips take a longer time than a normal
2106 : serial device to signalize that a transmission
2107 : data was queued. Due to that, the above test generally
2108 : fails. One solution would be to delay the reading of
2109 : iir. However, this is not reliable, since the timeout
2110 : is variable. So, let's just don't test if we receive
2111 : TX irq. This way, we'll never enable UART_BUG_TXEN.
2112 : */
2113 8 : if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2114 2 : goto dont_test_tx_en;
2115 :
2116 : /*
2117 : * Do a quick test to see if we receive an
2118 : * interrupt when we enable the TX irq.
2119 : */
2120 16 : serial_outp(up, UART_IER, UART_IER_THRI);
2121 14 : lsr = serial_in(up, UART_LSR);
2122 14 : iir = serial_in(up, UART_IIR);
2123 16 : serial_outp(up, UART_IER, 0);
2124 :
2125 8 : if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2126 6 : if (!(up->bugs & UART_BUG_TXEN)) {
2127 4 : up->bugs |= UART_BUG_TXEN;
2128 : pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2129 : serial_index(port));
2130 : }
2131 : } else {
2132 4 : up->bugs &= ~UART_BUG_TXEN;
2133 : }
2134 2 :
2135 : dont_test_tx_en:
2136 4 : spin_unlock_irqrestore(&up->port.lock, flags);
2137 :
2138 : /*
2139 : * Clear the interrupt registers again for luck, and clear the
2140 : * saved flags to avoid getting false values from polling
2141 : * routines or the previous session.
2142 : */
2143 12 : serial_inp(up, UART_LSR);
2144 12 : serial_inp(up, UART_RX);
2145 12 : serial_inp(up, UART_IIR);
2146 12 : serial_inp(up, UART_MSR);
2147 2 : up->lsr_saved_flags = 0;
2148 2 : up->msr_saved_flags = 0;
2149 :
2150 : /*
2151 : * Finally, enable interrupts. Note: Modem status interrupts
2152 : * are set via set_termios(), which will be occurring imminently
2153 : * anyway, so we don't enable them here.
2154 : */
2155 2 : up->ier = UART_IER_RLSI | UART_IER_RDI;
2156 18 : serial_outp(up, UART_IER, up->ier);
2157 :
2158 4 : if (up->port.flags & UPF_FOURPORT) {
2159 : unsigned int icp;
2160 : /*
2161 : * Enable interrupts on the AST Fourport board
2162 : */
2163 2 : icp = (up->port.iobase & 0xfe0) | 0x01f;
2164 4 : outb_p(0x80, icp);
2165 4 : (void) inb_p(icp);
2166 : }
2167 :
2168 4 : return 0;
2169 : }
2170 :
2171 : static void serial8250_shutdown(struct uart_port *port)
2172 : {
2173 8 : struct uart_8250_port *up = (struct uart_8250_port *)port;
2174 4 : unsigned long flags;
2175 4 :
2176 4 : /*
2177 : * Disable interrupts from this port
2178 : */
2179 4 : up->ier = 0;
2180 32 : serial_outp(up, UART_IER, 0);
2181 :
2182 12 : spin_lock_irqsave(&up->port.lock, flags);
2183 8 : if (up->port.flags & UPF_FOURPORT) {
2184 : /* reset interrupts on the AST Fourport board */
2185 8 : inb((up->port.iobase & 0xfe0) | 0x1f);
2186 4 : up->port.mctrl |= TIOCM_OUT1;
2187 : } else
2188 4 : up->port.mctrl &= ~TIOCM_OUT2;
2189 :
2190 16 : serial8250_set_mctrl(&up->port, up->port.mctrl);
2191 8 : spin_unlock_irqrestore(&up->port.lock, flags);
2192 :
2193 : /*
2194 : * Disable break condition and FIFOs
2195 : */
2196 56 : serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2197 8 : serial8250_clear_fifos(up);
2198 :
2199 : #ifdef CONFIG_SERIAL_8250_RSA
2200 : /*
2201 : * Reset the RSA board back to 115kbps compat mode.
2202 : */
2203 : disable_rsa(up);
2204 : #endif
2205 :
2206 : /*
2207 : * Read data port to reset things, and then unlink from
2208 : * the IRQ chain.
2209 : */
2210 24 : (void) serial_in(up, UART_RX);
2211 :
2212 8 : del_timer_sync(&up->timer);
2213 4 : up->timer.function = serial8250_timeout;
2214 8 : if (is_real_interrupt(up->port.irq))
2215 8 : serial_unlink_irq_chain(up);
2216 8 : }
2217 :
2218 : static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2219 : {
2220 4 : unsigned int quot;
2221 :
2222 : /*
2223 : * Handle magic divisors for baud rates above baud_base on
2224 : * SMSC SuperIO chips.
2225 : */
2226 16 : if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2227 : baud == (port->uartclk/4))
2228 4 : quot = 0x8001;
2229 16 : else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2230 : baud == (port->uartclk/8))
2231 4 : quot = 0x8002;
2232 : else
2233 4 : quot = uart_get_divisor(port, baud);
2234 :
2235 4 : return quot;
2236 : }
2237 :
2238 : static void
2239 : serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2240 : struct ktermios *old)
2241 : {
2242 8 : struct uart_8250_port *up = (struct uart_8250_port *)port;
2243 8 : unsigned char cval, fcr = 0;
2244 4 : unsigned long flags;
2245 4 : unsigned int baud, quot;
2246 4 :
2247 4 : switch (termios->c_cflag & CSIZE) {
2248 16 : case CS5:
2249 8 : cval = UART_LCR_WLEN5;
2250 8 : break;
2251 16 : case CS6:
2252 4 : cval = UART_LCR_WLEN6;
2253 4 : break;
2254 16 : case CS7:
2255 4 : cval = UART_LCR_WLEN7;
2256 4 : break;
2257 4 : default:
2258 4 : case CS8:
2259 4 : cval = UART_LCR_WLEN8;
2260 4 : break;
2261 : }
2262 :
2263 8 : if (termios->c_cflag & CSTOPB)
2264 4 : cval |= UART_LCR_STOP;
2265 8 : if (termios->c_cflag & PARENB)
2266 4 : cval |= UART_LCR_PARITY;
2267 8 : if (!(termios->c_cflag & PARODD))
2268 4 : cval |= UART_LCR_EPAR;
2269 : #ifdef CMSPAR
2270 8 : if (termios->c_cflag & CMSPAR)
2271 4 : cval |= UART_LCR_SPAR;
2272 : #endif
2273 :
2274 : /*
2275 : * Ask the core to calculate the divisor for us.
2276 : */
2277 4 : baud = uart_get_baud_rate(port, termios, old,
2278 : port->uartclk / 16 / 0xffff,
2279 : port->uartclk / 16);
2280 8 : quot = serial8250_get_divisor(port, baud);
2281 :
2282 : /*
2283 : * Oxford Semi 952 rev B workaround
2284 : */
2285 20 : if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2286 4 : quot++;
2287 :
2288 20 : if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2289 8 : if (baud < 2400)
2290 4 : fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2291 : else
2292 4 : fcr = uart_config[up->port.type].fcr;
2293 : }
2294 :
2295 : /*
2296 : * MCR-based auto flow control. When AFE is enabled, RTS will be
2297 : * deasserted when the receive FIFO contains more characters than
2298 : * the trigger, or the MCR RTS bit is cleared. In the case where
2299 : * the remote UART is not using CTS auto flow control, we must
2300 : * have sufficient FIFO entries for the latency of the remote
2301 : * UART to respond. IOW, at least 32 bytes of FIFO.
2302 : */
2303 20 : if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2304 8 : up->mcr &= ~UART_MCR_AFE;
2305 12 : if (termios->c_cflag & CRTSCTS)
2306 8 : up->mcr |= UART_MCR_AFE;
2307 : }
2308 :
2309 : /*
2310 : * Ok, we're now changing the port state. Do it with
2311 : * interrupts disabled.
2312 : */
2313 12 : spin_lock_irqsave(&up->port.lock, flags);
2314 :
2315 : /*
2316 : * Update the per-port timeout.
2317 : */
2318 4 : uart_update_timeout(port, termios->c_cflag, baud);
2319 :
2320 4 : up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2321 8 : if (termios->c_iflag & INPCK)
2322 4 : up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2323 8 : if (termios->c_iflag & (BRKINT | PARMRK))
2324 4 : up->port.read_status_mask |= UART_LSR_BI;
2325 :
2326 : /*
2327 : * Characteres to ignore
2328 : */
2329 4 : up->port.ignore_status_mask = 0;
2330 8 : if (termios->c_iflag & IGNPAR)
2331 4 : up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2332 12 : if (termios->c_iflag & IGNBRK) {
2333 4 : up->port.ignore_status_mask |= UART_LSR_BI;
2334 : /*
2335 : * If we're ignoring parity and break indicators,
2336 : * ignore overruns too (for real raw support).
2337 : */
2338 8 : if (termios->c_iflag & IGNPAR)
2339 4 : up->port.ignore_status_mask |= UART_LSR_OE;
2340 : }
2341 :
2342 : /*
2343 : * ignore all characters if CREAD is not set
2344 : */
2345 8 : if ((termios->c_cflag & CREAD) == 0)
2346 4 : up->port.ignore_status_mask |= UART_LSR_DR;
2347 :
2348 : /*
2349 : * CTS flow control flag and modem status interrupts
2350 : */
2351 8 : up->ier &= ~UART_IER_MSI;
2352 40 : if (!(up->bugs & UART_BUG_NOMSR) &&
2353 : UART_ENABLE_MS(&up->port, termios->c_cflag))
2354 8 : up->ier |= UART_IER_MSI;
2355 12 : if (up->capabilities & UART_CAP_UUE)
2356 8 : up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2357 :
2358 36 : serial_out(up, UART_IER, up->ier);
2359 :
2360 12 : if (up->capabilities & UART_CAP_EFR) {
2361 4 : unsigned char efr = 0;
2362 : /*
2363 : * TI16C752/Startech hardware flow control. FIXME:
2364 : * - TI16C752 requires control thresholds to be set.
2365 : * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2366 : */
2367 12 : if (termios->c_cflag & CRTSCTS)
2368 4 : efr |= UART_EFR_CTS;
2369 :
2370 32 : serial_outp(up, UART_LCR, 0xBF);
2371 32 : serial_outp(up, UART_EFR, efr);
2372 : }
2373 :
2374 : #ifdef CONFIG_ARCH_OMAP
2375 : /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2376 : if (cpu_is_omap1510() && is_omap_port(up)) {
2377 : if (baud == 115200) {
2378 : quot = 1;
2379 : serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2380 : } else
2381 : serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2382 : }
2383 : #endif
2384 :
2385 12 : if (up->capabilities & UART_NATSEMI) {
2386 : /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2387 32 : serial_outp(up, UART_LCR, 0xe0);
2388 : } else {
2389 32 : serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2390 : }
2391 :
2392 8 : serial_dl_write(up, quot);
2393 :
2394 : /*
2395 : * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2396 : * is written without DLAB set, this mode will be disabled.
2397 : */
2398 8 : if (up->port.type == PORT_16750)
2399 32 : serial_outp(up, UART_FCR, fcr);
2400 :
2401 32 : serial_outp(up, UART_LCR, cval); /* reset DLAB */
2402 4 : up->lcr = cval; /* Save LCR */
2403 8 : if (up->port.type != PORT_16750) {
2404 8 : if (fcr & UART_FCR_ENABLE_FIFO) {
2405 : /* emulated UARTs (Lucent Venus 167x) need two steps */
2406 32 : serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2407 : }
2408 32 : serial_outp(up, UART_FCR, fcr); /* set fcr */
2409 : }
2410 8 : serial8250_set_mctrl(&up->port, up->port.mctrl);
2411 8 : spin_unlock_irqrestore(&up->port.lock, flags);
2412 : /* Don't rewrite B0 */
2413 12 : if (tty_termios_baud_rate(termios))
2414 4 : tty_termios_encode_baud_rate(termios, baud, baud);
2415 4 : }
2416 :
2417 : static void
2418 : serial8250_pm(struct uart_port *port, unsigned int state,
2419 : unsigned int oldstate)
2420 6 : {
2421 6 : struct uart_8250_port *p = (struct uart_8250_port *)port;
2422 :
2423 12 : serial8250_set_sleep(p, state != 0);
2424 :
2425 18 : if (p->pm)
2426 48 : p->pm(port, state, oldstate);
2427 6 : }
2428 :
2429 : static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2430 : {
2431 36 : if (pt->port.iotype == UPIO_AU)
2432 18 : return 0x100000;
2433 : #ifdef CONFIG_ARCH_OMAP
2434 : if (is_omap_port(pt))
2435 : return 0x16 << pt->port.regshift;
2436 : #endif
2437 18 : return 8 << pt->port.regshift;
2438 : }
2439 :
2440 : /*
2441 : * Resource handling.
2442 : */
2443 : static int serial8250_request_std_resource(struct uart_8250_port *up)
2444 : {
2445 16 : unsigned int size = serial8250_port_size(up);
2446 8 : int ret = 0;
2447 4 :
2448 8 : switch (up->port.iotype) {
2449 20 : case UPIO_AU:
2450 20 : case UPIO_TSI:
2451 16 : case UPIO_MEM32:
2452 16 : case UPIO_MEM:
2453 16 : case UPIO_DWAPB:
2454 8 : if (!up->port.mapbase)
2455 4 : break;
2456 :
2457 12 : if (!request_mem_region(up->port.mapbase, size, "serial")) {
2458 4 : ret = -EBUSY;
2459 4 : break;
2460 : }
2461 :
2462 8 : if (up->port.flags & UPF_IOREMAP) {
2463 8 : up->port.membase = ioremap_nocache(up->port.mapbase,
2464 : size);
2465 8 : if (!up->port.membase) {
2466 4 : release_mem_region(up->port.mapbase, size);
2467 4 : ret = -ENOMEM;
2468 : }
2469 : }
2470 4 : break;
2471 4 :
2472 16 : case UPIO_HUB6:
2473 12 : case UPIO_PORT:
2474 12 : if (!request_region(up->port.iobase, size, "serial"))
2475 4 : ret = -EBUSY;
2476 4 : break;
2477 4 : }
2478 4 : return ret;
2479 4 : }
2480 :
2481 : static void serial8250_release_std_resource(struct uart_8250_port *up)
2482 : {
2483 56 : unsigned int size = serial8250_port_size(up);
2484 14 :
2485 14 : switch (up->port.iotype) {
2486 56 : case UPIO_AU:
2487 56 : case UPIO_TSI:
2488 56 : case UPIO_MEM32:
2489 56 : case UPIO_MEM:
2490 56 : case UPIO_DWAPB:
2491 28 : if (!up->port.mapbase)
2492 14 : break;
2493 :
2494 28 : if (up->port.flags & UPF_IOREMAP) {
2495 14 : iounmap(up->port.membase);
2496 14 : up->port.membase = NULL;
2497 : }
2498 :
2499 14 : release_mem_region(up->port.mapbase, size);
2500 14 : break;
2501 14 :
2502 56 : case UPIO_HUB6:
2503 42 : case UPIO_PORT:
2504 14 : release_region(up->port.iobase, size);
2505 14 : break;
2506 14 : }
2507 : }
2508 28 :
2509 : static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2510 : {
2511 8 : unsigned long start = UART_RSA_BASE << up->port.regshift;
2512 8 : unsigned int size = 8 << up->port.regshift;
2513 8 : int ret = -EINVAL;
2514 4 :
2515 4 : switch (up->port.iotype) {
2516 16 : case UPIO_HUB6:
2517 16 : case UPIO_PORT:
2518 4 : start += up->port.iobase;
2519 12 : if (request_region(start, size, "serial-rsa"))
2520 4 : ret = 0;
2521 : else
2522 4 : ret = -EBUSY;
2523 4 : break;
2524 4 : }
2525 :
2526 8 : return ret;
2527 : }
2528 :
2529 : static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2530 : {
2531 20 : unsigned long offset = UART_RSA_BASE << up->port.regshift;
2532 20 : unsigned int size = 8 << up->port.regshift;
2533 :
2534 10 : switch (up->port.iotype) {
2535 40 : case UPIO_HUB6:
2536 40 : case UPIO_PORT:
2537 10 : release_region(up->port.iobase + offset, size);
2538 10 : break;
2539 10 : }
2540 : }
2541 20 :
2542 : static void serial8250_release_port(struct uart_port *port)
2543 : {
2544 4 : struct uart_8250_port *up = (struct uart_8250_port *)port;
2545 :
2546 4 : serial8250_release_std_resource(up);
2547 4 : if (up->port.type == PORT_RSA)
2548 4 : serial8250_release_rsa_resource(up);
2549 4 : }
2550 :
2551 : static int serial8250_request_port(struct uart_port *port)
2552 : {
2553 4 : struct uart_8250_port *up = (struct uart_8250_port *)port;
2554 4 : int ret = 0;
2555 :
2556 4 : ret = serial8250_request_std_resource(up);
2557 8 : if (ret == 0 && up->port.type == PORT_RSA) {
2558 4 : ret = serial8250_request_rsa_resource(up);
2559 4 : if (ret < 0)
2560 4 : serial8250_release_std_resource(up);
2561 : }
2562 :
2563 6 : return ret;
2564 : }
2565 :
2566 : static void serial8250_config_port(struct uart_port *port, int flags)
2567 : {
2568 4 : struct uart_8250_port *up = (struct uart_8250_port *)port;
2569 4 : int probeflags = PROBE_ANY;
2570 2 : int ret;
2571 :
2572 : /*
2573 : * Find the region that we can probe for. This in turn
2574 : * tells us whether we can probe for the type of port.
2575 : */
2576 4 : ret = serial8250_request_std_resource(up);
2577 4 : if (ret < 0)
2578 2 : return;
2579 :
2580 4 : ret = serial8250_request_rsa_resource(up);
2581 4 : if (ret < 0)
2582 2 : probeflags &= ~PROBE_RSA;
2583 :
2584 6 : if (up->port.iotype != up->cur_iotype)
2585 4 : set_io_from_upio(port);
2586 :
2587 8 : if (flags & UART_CONFIG_TYPE)
2588 12 : autoconfig(up, probeflags);
2589 24 : if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2590 24 : autoconfig_irq(up);
2591 :
2592 32 : if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2593 16 : serial8250_release_rsa_resource(up);
2594 20 : if (up->port.type == PORT_UNKNOWN)
2595 20 : serial8250_release_std_resource(up);
2596 12 : }
2597 :
2598 : static int
2599 : serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2600 : {
2601 30 : if (ser->irq >= nr_irqs || ser->irq < 0 ||
2602 : ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2603 : ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2604 : ser->type == PORT_STARTECH)
2605 2 : return -EINVAL;
2606 2 : return 0;
2607 : }
2608 :
2609 : static const char *
2610 : serial8250_type(struct uart_port *port)
2611 : {
2612 6 : int type = port->type;
2613 :
2614 4 : if (type >= ARRAY_SIZE(uart_config))
2615 2 : type = 0;
2616 2 : return uart_config[type].name;
2617 : }
2618 :
2619 1 : static struct uart_ops serial8250_pops = {
2620 : .tx_empty = serial8250_tx_empty,
2621 : .set_mctrl = serial8250_set_mctrl,
2622 : .get_mctrl = serial8250_get_mctrl,
2623 : .stop_tx = serial8250_stop_tx,
2624 : .start_tx = serial8250_start_tx,
2625 : .stop_rx = serial8250_stop_rx,
2626 : .enable_ms = serial8250_enable_ms,
2627 : .break_ctl = serial8250_break_ctl,
2628 : .startup = serial8250_startup,
2629 : .shutdown = serial8250_shutdown,
2630 : .set_termios = serial8250_set_termios,
2631 : .pm = serial8250_pm,
2632 : .type = serial8250_type,
2633 : .release_port = serial8250_release_port,
2634 : .request_port = serial8250_request_port,
2635 : .config_port = serial8250_config_port,
2636 : .verify_port = serial8250_verify_port,
2637 : #ifdef CONFIG_CONSOLE_POLL
2638 : .poll_get_char = serial8250_get_poll_char,
2639 : .poll_put_char = serial8250_put_poll_char,
2640 : #endif
2641 : };
2642 :
2643 1 : static struct uart_8250_port serial8250_ports[UART_NR];
2644 :
2645 : static void __init serial8250_isa_init_ports(void)
2646 : {
2647 1 : struct uart_8250_port *up;
2648 2 : static int first = 1;
2649 2 : int i, irqflag = 0;
2650 1 :
2651 3 : if (!first)
2652 2 : return;
2653 2 : first = 0;
2654 :
2655 5 : for (i = 0; i < nr_uarts; i++) {
2656 2 : struct uart_8250_port *up = &serial8250_ports[i];
2657 2 :
2658 1 : up->port.line = i;
2659 4 : spin_lock_init(&up->port.lock);
2660 :
2661 1 : init_timer(&up->timer);
2662 1 : up->timer.function = serial8250_timeout;
2663 :
2664 : /*
2665 : * ALPHA_KLUDGE_MCR needs to be killed.
2666 : */
2667 1 : up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2668 1 : up->mcr_force = ALPHA_KLUDGE_MCR;
2669 :
2670 1 : up->port.ops = &serial8250_pops;
2671 : }
2672 :
2673 2 : if (share_irqs)
2674 1 : irqflag = IRQF_SHARED;
2675 :
2676 7 : for (i = 0, up = serial8250_ports;
2677 1 : i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2678 2 : i++, up++) {
2679 2 : up->port.iobase = old_serial_port[i].port;
2680 4 : up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2681 1 : up->port.irqflags = old_serial_port[i].irqflags;
2682 1 : up->port.uartclk = old_serial_port[i].baud_base * 16;
2683 1 : up->port.flags = old_serial_port[i].flags;
2684 2 : up->port.hub6 = old_serial_port[i].hub6;
2685 1 : up->port.membase = old_serial_port[i].iomem_base;
2686 1 : up->port.iotype = old_serial_port[i].io_type;
2687 1 : up->port.regshift = old_serial_port[i].iomem_reg_shift;
2688 2 : set_io_from_upio(&up->port);
2689 1 : up->port.irqflags |= irqflag;
2690 : }
2691 : }
2692 :
2693 : static void __init
2694 : serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2695 : {
2696 1 : int i;
2697 1 :
2698 6 : for (i = 0; i < nr_uarts; i++) {
2699 3 : struct uart_8250_port *up = &serial8250_ports[i];
2700 2 : up->cur_iotype = 0xFF;
2701 : }
2702 :
2703 3 : serial8250_isa_init_ports();
2704 :
2705 5 : for (i = 0; i < nr_uarts; i++) {
2706 2 : struct uart_8250_port *up = &serial8250_ports[i];
2707 2 :
2708 1 : up->port.dev = dev;
2709 2 : uart_add_one_port(drv, &up->port);
2710 : }
2711 : }
2712 1 :
2713 : #ifdef CONFIG_SERIAL_8250_CONSOLE
2714 :
2715 : static void serial8250_console_putchar(struct uart_port *port, int ch)
2716 : {
2717 : struct uart_8250_port *up = (struct uart_8250_port *)port;
2718 :
2719 : wait_for_xmitr(up, UART_LSR_THRE);
2720 : serial_out(up, UART_TX, ch);
2721 : }
2722 :
2723 : /*
2724 : * Print a string to the serial port trying not to disturb
2725 : * any possible real use of the port...
2726 : *
2727 : * The console_lock must be held when we get here.
2728 : */
2729 : static void
2730 : serial8250_console_write(struct console *co, const char *s, unsigned int count)
2731 : {
2732 : struct uart_8250_port *up = &serial8250_ports[co->index];
2733 : unsigned long flags;
2734 : unsigned int ier;
2735 : int locked = 1;
2736 :
2737 : touch_nmi_watchdog();
2738 :
2739 : local_irq_save(flags);
2740 : if (up->port.sysrq) {
2741 : /* serial8250_handle_port() already took the lock */
2742 : locked = 0;
2743 : } else if (oops_in_progress) {
2744 : locked = spin_trylock(&up->port.lock);
2745 : } else
2746 : spin_lock(&up->port.lock);
2747 :
2748 : /*
2749 : * First save the IER then disable the interrupts
2750 : */
2751 : ier = serial_in(up, UART_IER);
2752 :
2753 : if (up->capabilities & UART_CAP_UUE)
2754 : serial_out(up, UART_IER, UART_IER_UUE);
2755 : else
2756 : serial_out(up, UART_IER, 0);
2757 :
2758 : uart_console_write(&up->port, s, count, serial8250_console_putchar);
2759 :
2760 : /*
2761 : * Finally, wait for transmitter to become empty
2762 : * and restore the IER
2763 : */
2764 : wait_for_xmitr(up, BOTH_EMPTY);
2765 : serial_out(up, UART_IER, ier);
2766 :
2767 : /*
2768 : * The receive handling will happen properly because the
2769 : * receive ready bit will still be set; it is not cleared
2770 : * on read. However, modem control will not, we must
2771 : * call it if we have saved something in the saved flags
2772 : * while processing with interrupts off.
2773 : */
2774 : if (up->msr_saved_flags)
2775 : check_modem_status(up);
2776 :
2777 : if (locked)
2778 : spin_unlock(&up->port.lock);
2779 : local_irq_restore(flags);
2780 : }
2781 :
2782 : static int __init serial8250_console_setup(struct console *co, char *options)
2783 : {
2784 : struct uart_port *port;
2785 : int baud = 9600;
2786 : int bits = 8;
2787 : int parity = 'n';
2788 : int flow = 'n';
2789 :
2790 : /*
2791 : * Check whether an invalid uart number has been specified, and
2792 : * if so, search for the first available port that does have
2793 : * console support.
2794 : */
2795 : if (co->index >= nr_uarts)
2796 : co->index = 0;
2797 : port = &serial8250_ports[co->index].port;
2798 : if (!port->iobase && !port->membase)
2799 : return -ENODEV;
2800 :
2801 : if (options)
2802 : uart_parse_options(options, &baud, &parity, &bits, &flow);
2803 :
2804 : return uart_set_options(port, co, baud, parity, bits, flow);
2805 : }
2806 :
2807 : static int serial8250_console_early_setup(void)
2808 : {
2809 : return serial8250_find_port_for_earlycon();
2810 : }
2811 :
2812 : static struct console serial8250_console = {
2813 : .name = "ttyS",
2814 : .write = serial8250_console_write,
2815 : .device = uart_console_device,
2816 : .setup = serial8250_console_setup,
2817 : .early_setup = serial8250_console_early_setup,
2818 : .flags = CON_PRINTBUFFER,
2819 : .index = -1,
2820 : .data = &serial8250_reg,
2821 : };
2822 :
2823 : static int __init serial8250_console_init(void)
2824 : {
2825 : if (nr_uarts > UART_NR)
2826 : nr_uarts = UART_NR;
2827 :
2828 : serial8250_isa_init_ports();
2829 : register_console(&serial8250_console);
2830 : return 0;
2831 : }
2832 : console_initcall(serial8250_console_init);
2833 :
2834 : int serial8250_find_port(struct uart_port *p)
2835 : {
2836 : int line;
2837 : struct uart_port *port;
2838 :
2839 : for (line = 0; line < nr_uarts; line++) {
2840 : port = &serial8250_ports[line].port;
2841 : if (uart_match_port(p, port))
2842 : return line;
2843 : }
2844 : return -ENODEV;
2845 : }
2846 :
2847 : #define SERIAL8250_CONSOLE &serial8250_console
2848 : #else
2849 : #define SERIAL8250_CONSOLE NULL
2850 : #endif
2851 :
2852 1 : static struct uart_driver serial8250_reg = {
2853 : .owner = THIS_MODULE,
2854 : .driver_name = "serial",
2855 : .dev_name = "ttyS",
2856 : .major = TTY_MAJOR,
2857 : .minor = 64,
2858 : .cons = SERIAL8250_CONSOLE,
2859 : };
2860 :
2861 : /*
2862 : * early_serial_setup - early registration for 8250 ports
2863 : *
2864 : * Setup an 8250 port structure prior to console initialisation. Use
2865 : * after console initialisation will cause undefined behaviour.
2866 : */
2867 : int __init early_serial_setup(struct uart_port *port)
2868 : {
2869 0 : struct uart_port *p;
2870 :
2871 0 : if (port->line >= ARRAY_SIZE(serial8250_ports))
2872 0 : return -ENODEV;
2873 :
2874 0 : serial8250_isa_init_ports();
2875 0 : p = &serial8250_ports[port->line].port;
2876 0 : p->iobase = port->iobase;
2877 0 : p->membase = port->membase;
2878 0 : p->irq = port->irq;
2879 0 : p->irqflags = port->irqflags;
2880 0 : p->uartclk = port->uartclk;
2881 0 : p->fifosize = port->fifosize;
2882 0 : p->regshift = port->regshift;
2883 0 : p->iotype = port->iotype;
2884 0 : p->flags = port->flags;
2885 0 : p->mapbase = port->mapbase;
2886 0 : p->private_data = port->private_data;
2887 0 : p->type = port->type;
2888 0 : p->line = port->line;
2889 :
2890 0 : set_io_from_upio(p);
2891 0 : if (port->serial_in)
2892 0 : p->serial_in = port->serial_in;
2893 0 : if (port->serial_out)
2894 0 : p->serial_out = port->serial_out;
2895 :
2896 0 : return 0;
2897 : }
2898 :
2899 : /**
2900 : * serial8250_suspend_port - suspend one serial port
2901 : * @line: serial line number
2902 : *
2903 : * Suspend one serial port.
2904 : */
2905 : void serial8250_suspend_port(int line)
2906 : {
2907 0 : uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2908 0 : }
2909 :
2910 : /**
2911 : * serial8250_resume_port - resume one serial port
2912 : * @line: serial line number
2913 : *
2914 : * Resume one serial port.
2915 : */
2916 : void serial8250_resume_port(int line)
2917 : {
2918 2 : struct uart_8250_port *up = &serial8250_ports[line];
2919 1 :
2920 4 : if (up->capabilities & UART_NATSEMI) {
2921 : unsigned char tmp;
2922 :
2923 : /* Ensure it's still in high speed mode */
2924 8 : serial_outp(up, UART_LCR, 0xE0);
2925 :
2926 7 : tmp = serial_in(up, 0x04); /* EXCR2 */
2927 1 : tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2928 1 : tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2929 8 : serial_outp(up, 0x04, tmp);
2930 :
2931 8 : serial_outp(up, UART_LCR, 0);
2932 : }
2933 1 : uart_resume_port(&serial8250_reg, &up->port);
2934 1 : }
2935 :
2936 : /*
2937 : * Register a set of serial devices attached to a platform device. The
2938 : * list is terminated with a zero flags entry, which means we expect
2939 : * all entries to have at least UPF_BOOT_AUTOCONF set.
2940 : */
2941 : static int __devinit serial8250_probe(struct platform_device *dev)
2942 : {
2943 2 : struct plat_serial8250_port *p = dev->dev.platform_data;
2944 1 : struct uart_port port;
2945 2 : int ret, i, irqflag = 0;
2946 1 :
2947 2 : memset(&port, 0, sizeof(struct uart_port));
2948 1 :
2949 3 : if (share_irqs)
2950 1 : irqflag = IRQF_SHARED;
2951 :
2952 10 : for (i = 0; p && p->flags != 0; p++, i++) {
2953 4 : port.iobase = p->iobase;
2954 3 : port.membase = p->membase;
2955 1 : port.irq = p->irq;
2956 1 : port.irqflags = p->irqflags;
2957 1 : port.uartclk = p->uartclk;
2958 1 : port.regshift = p->regshift;
2959 1 : port.iotype = p->iotype;
2960 1 : port.flags = p->flags;
2961 1 : port.mapbase = p->mapbase;
2962 1 : port.hub6 = p->hub6;
2963 1 : port.private_data = p->private_data;
2964 1 : port.type = p->type;
2965 1 : port.serial_in = p->serial_in;
2966 1 : port.serial_out = p->serial_out;
2967 1 : port.dev = &dev->dev;
2968 1 : port.irqflags |= irqflag;
2969 4 : ret = serial8250_register_port(&port);
2970 2 : if (ret < 0) {
2971 4 : dev_err(&dev->dev, "unable to register port at index %d "
2972 : "(IO%lx MEM%llx IRQ%d): %d\n", i,
2973 : p->iobase, (unsigned long long)p->mapbase,
2974 : p->irq, ret);
2975 : }
2976 : }
2977 1 : return 0;
2978 : }
2979 :
2980 : /*
2981 : * Remove serial ports registered against a platform device.
2982 : */
2983 : static int __devexit serial8250_remove(struct platform_device *dev)
2984 : {
2985 : int i;
2986 :
2987 : for (i = 0; i < nr_uarts; i++) {
2988 : struct uart_8250_port *up = &serial8250_ports[i];
2989 :
2990 : if (up->port.dev == &dev->dev)
2991 : serial8250_unregister_port(i);
2992 : }
2993 : return 0;
2994 : }
2995 :
2996 : static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2997 : {
2998 1 : int i;
2999 1 :
3000 5 : for (i = 0; i < UART_NR; i++) {
3001 3 : struct uart_8250_port *up = &serial8250_ports[i];
3002 1 :
3003 4 : if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3004 1 : uart_suspend_port(&serial8250_reg, &up->port);
3005 : }
3006 :
3007 1 : return 0;
3008 : }
3009 :
3010 : static int serial8250_resume(struct platform_device *dev)
3011 : {
3012 1 : int i;
3013 1 :
3014 6 : for (i = 0; i < UART_NR; i++) {
3015 4 : struct uart_8250_port *up = &serial8250_ports[i];
3016 1 :
3017 4 : if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3018 2 : serial8250_resume_port(i);
3019 : }
3020 :
3021 1 : return 0;
3022 : }
3023 :
3024 1 : static struct platform_driver serial8250_isa_driver = {
3025 : .probe = serial8250_probe,
3026 : .remove = __devexit_p(serial8250_remove),
3027 : .suspend = serial8250_suspend,
3028 : .resume = serial8250_resume,
3029 : .driver = {
3030 : .name = "serial8250",
3031 : .owner = THIS_MODULE,
3032 : },
3033 : };
3034 :
3035 : /*
3036 : * This "device" covers _all_ ISA 8250-compatible serial devices listed
3037 : * in the table in include/asm/serial.h
3038 : */
3039 1 : static struct platform_device *serial8250_isa_devs;
3040 :
3041 : /*
3042 : * serial8250_register_port and serial8250_unregister_port allows for
3043 : * 16x50 serial ports to be configured at run-time, to support PCMCIA
3044 : * modems and PCI multiport cards.
3045 : */
3046 1 : static DEFINE_MUTEX(serial_mutex);
3047 :
3048 : static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3049 : {
3050 1 : int i;
3051 1 :
3052 : /*
3053 : * First, find a port entry which matches.
3054 : */
3055 5 : for (i = 0; i < nr_uarts; i++)
3056 5 : if (uart_match_port(&serial8250_ports[i].port, port))
3057 2 : return &serial8250_ports[i];
3058 :
3059 : /*
3060 : * We didn't find a matching entry, so look for the first
3061 : * free entry. We look for one which hasn't been previously
3062 : * used (indicated by zero iobase).
3063 : */
3064 5 : for (i = 0; i < nr_uarts; i++)
3065 6 : if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3066 1 : serial8250_ports[i].port.iobase == 0)
3067 1 : return &serial8250_ports[i];
3068 :
3069 : /*
3070 : * That also failed. Last resort is to find any entry which
3071 : * doesn't have a real port associated with it.
3072 : */
3073 5 : for (i = 0; i < nr_uarts; i++)
3074 4 : if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3075 2 : return &serial8250_ports[i];
3076 :
3077 1 : return NULL;
3078 : }
3079 :
3080 : /**
3081 : * serial8250_register_port - register a serial port
3082 : * @port: serial port template
3083 : *
3084 : * Configure the serial port specified by the request. If the
3085 : * port exists and is in use, it is hung up and unregistered
3086 : * first.
3087 : *
3088 : * The port is then probed and if necessary the IRQ is autodetected
3089 : * If this fails an error is returned.
3090 : *
3091 : * On success the port is ready to use and the line number is returned.
3092 : */
3093 : int serial8250_register_port(struct uart_port *port)
3094 : {
3095 1 : struct uart_8250_port *uart;
3096 2 : int ret = -ENOSPC;
3097 :
3098 2 : if (port->uartclk == 0)
3099 1 : return -EINVAL;
3100 :
3101 1 : mutex_lock(&serial_mutex);
3102 :
3103 4 : uart = serial8250_find_match_or_unused(port);
3104 2 : if (uart) {
3105 2 : uart_remove_one_port(&serial8250_reg, &uart->port);
3106 :
3107 1 : uart->port.iobase = port->iobase;
3108 1 : uart->port.membase = port->membase;
3109 1 : uart->port.irq = port->irq;
3110 1 : uart->port.irqflags = port->irqflags;
3111 1 : uart->port.uartclk = port->uartclk;
3112 1 : uart->port.fifosize = port->fifosize;
3113 1 : uart->port.regshift = port->regshift;
3114 1 : uart->port.iotype = port->iotype;
3115 1 : uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3116 1 : uart->port.mapbase = port->mapbase;
3117 1 : uart->port.private_data = port->private_data;
3118 3 : if (port->dev)
3119 1 : uart->port.dev = port->dev;
3120 :
3121 2 : if (port->flags & UPF_FIXED_TYPE) {
3122 1 : uart->port.type = port->type;
3123 1 : uart->port.fifosize = uart_config[port->type].fifo_size;
3124 1 : uart->capabilities = uart_config[port->type].flags;
3125 1 : uart->tx_loadsz = uart_config[port->type].tx_loadsz;
3126 : }
3127 :
3128 2 : set_io_from_upio(&uart->port);
3129 : /* Possibly override default I/O functions. */
3130 3 : if (port->serial_in)
3131 1 : uart->port.serial_in = port->serial_in;
3132 3 : if (port->serial_out)
3133 1 : uart->port.serial_out = port->serial_out;
3134 :
3135 2 : ret = uart_add_one_port(&serial8250_reg, &uart->port);
3136 2 : if (ret == 0)
3137 1 : ret = uart->port.line;
3138 : }
3139 2 : mutex_unlock(&serial_mutex);
3140 :
3141 2 : return ret;
3142 : }
3143 : EXPORT_SYMBOL(serial8250_register_port);
3144 :
3145 : /**
3146 : * serial8250_unregister_port - remove a 16x50 serial port at runtime
3147 : * @line: serial line number
3148 : *
3149 : * Remove one serial port. This may not be called from interrupt
3150 : * context. We hand the port back to the our control.
3151 : */
3152 : void serial8250_unregister_port(int line)
3153 : {
3154 0 : struct uart_8250_port *uart = &serial8250_ports[line];
3155 :
3156 0 : mutex_lock(&serial_mutex);
3157 0 : uart_remove_one_port(&serial8250_reg, &uart->port);
3158 0 : if (serial8250_isa_devs) {
3159 0 : uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3160 0 : uart->port.type = PORT_UNKNOWN;
3161 0 : uart->port.dev = &serial8250_isa_devs->dev;
3162 0 : uart_add_one_port(&serial8250_reg, &uart->port);
3163 : } else {
3164 0 : uart->port.dev = NULL;
3165 : }
3166 0 : mutex_unlock(&serial_mutex);
3167 0 : }
3168 : EXPORT_SYMBOL(serial8250_unregister_port);
3169 :
3170 : static int __init serial8250_init(void)
3171 : {
3172 1 : int ret;
3173 :
3174 2 : if (nr_uarts > UART_NR)
3175 1 : nr_uarts = UART_NR;
3176 :
3177 2 : printk(KERN_INFO "Serial: 8250/16550 driver, "
3178 4 : "%d ports, IRQ sharing %sabled\n", nr_uarts,
3179 : share_irqs ? "en" : "dis");
3180 :
3181 : #ifdef CONFIG_SPARC
3182 : ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3183 : #else
3184 1 : serial8250_reg.nr = UART_NR;
3185 1 : ret = uart_register_driver(&serial8250_reg);
3186 : #endif
3187 2 : if (ret)
3188 1 : goto out;
3189 :
3190 1 : serial8250_isa_devs = platform_device_alloc("serial8250",
3191 : PLAT8250_DEV_LEGACY);
3192 2 : if (!serial8250_isa_devs) {
3193 1 : ret = -ENOMEM;
3194 1 : goto unreg_uart_drv;
3195 : }
3196 :
3197 1 : ret = platform_device_add(serial8250_isa_devs);
3198 2 : if (ret)
3199 1 : goto put_dev;
3200 :
3201 2 : serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3202 :
3203 2 : ret = platform_driver_register(&serial8250_isa_driver);
3204 2 : if (ret == 0)
3205 1 : goto out;
3206 :
3207 1 : platform_device_del(serial8250_isa_devs);
3208 : put_dev:
3209 3 : platform_device_put(serial8250_isa_devs);
3210 : unreg_uart_drv:
3211 2 : #ifdef CONFIG_SPARC
3212 : sunserial_unregister_minors(&serial8250_reg, UART_NR);
3213 : #else
3214 2 : uart_unregister_driver(&serial8250_reg);
3215 : #endif
3216 2 : out:
3217 2 : return ret;
3218 : }
3219 :
3220 : static void __exit serial8250_exit(void)
3221 : {
3222 4 : struct platform_device *isa_dev = serial8250_isa_devs;
3223 :
3224 : /*
3225 : * This tells serial8250_unregister_port() not to re-register
3226 : * the ports (thereby making serial8250_isa_driver permanently
3227 : * in use.)
3228 : */
3229 2 : serial8250_isa_devs = NULL;
3230 :
3231 4 : platform_driver_unregister(&serial8250_isa_driver);
3232 2 : platform_device_unregister(isa_dev);
3233 :
3234 : #ifdef CONFIG_SPARC
3235 : sunserial_unregister_minors(&serial8250_reg, UART_NR);
3236 : #else
3237 2 : uart_unregister_driver(&serial8250_reg);
3238 2 : #endif
3239 : }
3240 :
3241 : module_init(serial8250_init);
3242 : module_exit(serial8250_exit);
3243 :
3244 : EXPORT_SYMBOL(serial8250_suspend_port);
3245 : EXPORT_SYMBOL(serial8250_resume_port);
3246 :
3247 : MODULE_LICENSE("GPL");
3248 : MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3249 :
3250 : module_param(share_irqs, uint, 0644);
3251 : MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3252 : " (unsafe)");
3253 :
3254 : module_param(nr_uarts, uint, 0644);
3255 : MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3256 :
3257 : module_param(skip_txen_test, uint, 0644);
3258 1 : MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3259 :
3260 : #ifdef CONFIG_SERIAL_8250_RSA
3261 : module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3262 : MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3263 : #endif
3264 : MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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