LCOV - code coverage report
Current view: top level - drivers/usb/host - ehci-pci.c (source / functions) Hit Total Coverage
Test: coverage.info Lines: 142 142 100.0 %
Date: 2017-01-25 Functions: 2 2 100.0 %

          Line data    Source code
       1             : /*
       2             :  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
       3             :  *
       4             :  * Copyright (c) 2000-2004 by David Brownell
       5             :  *
       6             :  * This program is free software; you can redistribute it and/or modify it
       7             :  * under the terms of the GNU General Public License as published by the
       8             :  * Free Software Foundation; either version 2 of the License, or (at your
       9             :  * option) any later version.
      10             :  *
      11             :  * This program is distributed in the hope that it will be useful, but
      12             :  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
      13             :  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
      14             :  * for more details.
      15             :  *
      16             :  * You should have received a copy of the GNU General Public License
      17             :  * along with this program; if not, write to the Free Software Foundation,
      18             :  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
      19             :  */
      20             : 
      21             : #ifndef CONFIG_PCI
      22             : #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
      23             : #endif
      24             : 
      25             : /*-------------------------------------------------------------------------*/
      26             : 
      27             : /* called after powerup, by probe or system-pm "wakeup" */
      28             : static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
      29             : {
      30           1 :         int                     retval;
      31             : 
      32             :         /* we expect static quirk code to handle the "extended capabilities"
      33             :          * (currently just BIOS handoff) allowed starting with EHCI 0.96
      34             :          */
      35             : 
      36             :         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
      37           1 :         retval = pci_set_mwi(pdev);
      38             :         if (!retval)
      39             :                 ehci_dbg(ehci, "MWI active\n");
      40             : 
      41           1 :         return 0;
      42             : }
      43             : 
      44             : /* called during probe() after chip reset completes */
      45             : static int ehci_pci_setup(struct usb_hcd *hcd)
      46             : {
      47           4 :         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
      48           3 :         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
      49           1 :         struct pci_dev          *p_smbus;
      50           1 :         u8                      rev;
      51           1 :         u32                     temp;
      52           1 :         int                     retval;
      53           1 : 
      54           2 :         switch (pdev->vendor) {
      55           6 :         case PCI_VENDOR_ID_TOSHIBA_2:
      56           1 :                 /* celleb's companion chip */
      57           4 :                 if (pdev->device == 0x01b5) {
      58           1 : #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
      59           1 :                         ehci->big_endian_mmio = 1;
      60           1 : #else
      61           9 :                         ehci_warn(ehci,
      62           1 :                                   "unsupported big endian Toshiba quirk\n");
      63           1 : #endif
      64           1 :                 }
      65           3 :                 break;
      66           2 :         }
      67           1 : 
      68           6 :         ehci->caps = hcd->regs;
      69           6 :         ehci->regs = hcd->regs +
      70           1 :                 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
      71           1 : 
      72           3 :         dbg_hcs_params(ehci, "reset");
      73           3 :         dbg_hcc_params(ehci, "reset");
      74           1 : 
      75           1 :         /* ehci_init() causes memory for DMA transfers to be
      76           1 :          * allocated.  Thus, any vendor-specific workarounds based on
      77           1 :          * limiting the type of memory used for DMA transfers must
      78           1 :          * happen before ehci_init() is called. */
      79           2 :         switch (pdev->vendor) {
      80           6 :         case PCI_VENDOR_ID_NVIDIA:
      81           1 :                 /* NVidia reports that certain chips don't handle
      82           1 :                  * QH, ITD, or SITD addresses above 2GB.  (But TD,
      83           1 :                  * data buffer, and periodic schedule are normal.)
      84           1 :                  */
      85           2 :                 switch (pdev->device) {
      86           6 :                 case 0x003c:    /* MCP04 */
      87           6 :                 case 0x005b:    /* CK804 */
      88           6 :                 case 0x00d8:    /* CK8 */
      89           5 :                 case 0x00e8:    /* CK8S */
      90           3 :                         if (pci_set_consistent_dma_mask(pdev,
      91             :                                                 DMA_BIT_MASK(31)) < 0)
      92           8 :                                 ehci_warn(ehci, "can't enable NVidia "
      93             :                                         "workaround for >2GB RAM\n");
      94           2 :                         break;
      95           1 :                 }
      96           2 :                 break;
      97           2 :         }
      98             : 
      99           1 :         /* cache this readonly data; minimize chip reads */
     100           4 :         ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
     101             : 
     102           3 :         retval = ehci_halt(ehci);
     103           2 :         if (retval)
     104           1 :                 return retval;
     105             : 
     106             :         /* data structure init */
     107           3 :         retval = ehci_init(hcd);
     108           2 :         if (retval)
     109           1 :                 return retval;
     110             : 
     111           1 :         switch (pdev->vendor) {
     112           5 :         case PCI_VENDOR_ID_INTEL:
     113           1 :                 ehci->need_io_watchdog = 0;
     114           3 :                 if (pdev->device == 0x27cc) {
     115           1 :                         ehci->broken_periodic = 1;
     116           8 :                         ehci_info(ehci, "using broken periodic workaround\n");
     117             :                 }
     118           2 :                 break;
     119           5 :         case PCI_VENDOR_ID_TDI:
     120           3 :                 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
     121           1 :                         hcd->has_tt = 1;
     122           2 :                         tdi_reset(ehci);
     123             :                 }
     124           2 :                 break;
     125           5 :         case PCI_VENDOR_ID_AMD:
     126             :                 /* AMD8111 EHCI doesn't work, according to AMD errata */
     127           3 :                 if (pdev->device == 0x7463) {
     128           8 :                         ehci_info(ehci, "ignoring AMD8111 (errata)\n");
     129           1 :                         retval = -EIO;
     130           1 :                         goto done;
     131             :                 }
     132           1 :                 break;
     133           5 :         case PCI_VENDOR_ID_NVIDIA:
     134           1 :                 switch (pdev->device) {
     135           1 :                 /* Some NForce2 chips have problems with selective suspend;
     136             :                  * fixed in newer silicon.
     137             :                  */
     138           4 :                 case 0x0068:
     139           3 :                         if (pdev->revision < 0xa4)
     140           1 :                                 ehci->no_selective_suspend = 1;
     141           1 :                         break;
     142           1 :                 }
     143           1 :                 break;
     144           6 :         case PCI_VENDOR_ID_VIA:
     145           6 :                 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
     146             :                         u8 tmp;
     147             : 
     148             :                         /* The VT6212 defaults to a 1 usec EHCI sleep time which
     149             :                          * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
     150             :                          * that sleep time use the conventional 10 usec.
     151             :                          */
     152           2 :                         pci_read_config_byte(pdev, 0x4b, &tmp);
     153           2 :                         if (tmp & 0x20)
     154           1 :                                 break;
     155           2 :                         pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
     156             :                 }
     157           2 :                 break;
     158           5 :         case PCI_VENDOR_ID_ATI:
     159             :                 /* SB600 and old version of SB700 have a bug in EHCI controller,
     160             :                  * which causes usb devices lose response in some cases.
     161             :                  */
     162           6 :                 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
     163           1 :                         p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
     164             :                                                  PCI_DEVICE_ID_ATI_SBX00_SMBUS,
     165             :                                                  NULL);
     166           2 :                         if (!p_smbus)
     167           1 :                                 break;
     168           1 :                         rev = p_smbus->revision;
     169           7 :                         if ((pdev->device == 0x4386) || (rev == 0x3a)
     170             :                             || (rev == 0x3b)) {
     171             :                                 u8 tmp;
     172           8 :                                 ehci_info(ehci, "applying AMD SB600/SB700 USB "
     173             :                                         "freeze workaround\n");
     174           2 :                                 pci_read_config_byte(pdev, 0x53, &tmp);
     175           2 :                                 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
     176             :                         }
     177           2 :                         pci_dev_put(p_smbus);
     178             :                 }
     179           2 :                 break;
     180           1 :         }
     181             : 
     182           1 :         /* optional debug port, normally in the first BAR */
     183          12 :         temp = pci_find_capability(pdev, 0x0a);
     184          12 :         if (temp) {
     185          12 :                 pci_read_config_dword(pdev, temp, &temp);
     186           1 :                 temp >>= 16;
     187           2 :                 if ((temp & (3 << 13)) == (1 << 13)) {
     188           1 :                         temp &= 0x1fff;
     189           3 :                         ehci->debug = ehci_to_hcd(ehci)->regs + temp;
     190           2 :                         temp = ehci_readl(ehci, &ehci->debug->control);
     191           9 :                         ehci_info(ehci, "debug port %d%s\n",
     192           4 :                                 HCS_DEBUG_PORT(ehci->hcs_params),
     193             :                                 (temp & DBGP_ENABLED)
     194             :                                         ? " IN USE"
     195             :                                         : "");
     196           2 :                         if (!(temp & DBGP_ENABLED))
     197           1 :                                 ehci->debug = NULL;
     198             :                 }
     199             :         }
     200             : 
     201          48 :         ehci_reset(ehci);
     202             : 
     203             :         /* at least the Genesys GL880S needs fixup here */
     204           1 :         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
     205           1 :         temp &= 0x0f;
     206           4 :         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
     207             :                 ehci_dbg(ehci, "bogus port configuration: "
     208             :                         "cc=%d x pcc=%d < ports=%d\n",
     209             :                         HCS_N_CC(ehci->hcs_params),
     210             :                         HCS_N_PCC(ehci->hcs_params),
     211             :                         HCS_N_PORTS(ehci->hcs_params));
     212             : 
     213           1 :                 switch (pdev->vendor) {
     214           5 :                 case 0x17a0:            /* GENESYS */
     215             :                         /* GL880S: should be PORTS=2 */
     216           1 :                         temp |= (ehci->hcs_params & ~0xf);
     217           1 :                         ehci->hcs_params = temp;
     218           1 :                         break;
     219           1 :                 case PCI_VENDOR_ID_NVIDIA:
     220             :                         /* NF4: should be PCC=10 */
     221             :                         break;
     222             :                 }
     223             :         }
     224             : 
     225             :         /* Serial Bus Release Number is at PCI 0x60 offset */
     226           2 :         pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
     227             : 
     228             :         /* Keep this around for a while just in case some EHCI
     229             :          * implementation uses legacy PCI PM support.  This test
     230             :          * can be removed on 17 Dec 2009 if the dev_warn() hasn't
     231             :          * been triggered by then.
     232             :          */
     233           4 :         if (!device_can_wakeup(&pdev->dev)) {
     234             :                 u16     port_wake;
     235             : 
     236           2 :                 pci_read_config_word(pdev, 0x62, &port_wake);
     237           2 :                 if (port_wake & 0x0001) {
     238           4 :                         dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
     239           2 :                         device_set_wakeup_capable(&pdev->dev, 1);
     240             :                 }
     241             :         }
     242             : 
     243             : #ifdef  CONFIG_USB_SUSPEND
     244             :         /* REVISIT: the controller works fine for wakeup iff the root hub
     245             :          * itself is "globally" suspended, but usbcore currently doesn't
     246             :          * understand such things.
     247             :          *
     248             :          * System suspend currently expects to be able to suspend the entire
     249             :          * device tree, device-at-a-time.  If we failed selective suspend
     250             :          * reports, system suspend would fail; so the root hub code must claim
     251             :          * success.  That's lying to usbcore, and it matters for runtime
     252             :          * PM scenarios with selective suspend and remote wakeup...
     253             :          */
     254             :         if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
     255             :                 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
     256             : #endif
     257             : 
     258           9 :         ehci_port_power(ehci, 1);
     259           2 :         retval = ehci_pci_reinit(ehci, pdev);
     260             : done:
     261           3 :         return retval;
     262             : }
     263             : 
     264             : /*-------------------------------------------------------------------------*/
     265             : 
     266             : #ifdef  CONFIG_PM
     267             : 
     268             : /* suspend/resume, section 4.3 */
     269             : 
     270             : /* These routines rely on the PCI bus glue
     271             :  * to handle powerdown and wakeup, and currently also on
     272             :  * transceivers that don't need any software attention to set up
     273             :  * the right sort of wakeup.
     274             :  * Also they depend on separate root hub suspend/resume.
     275             :  */
     276             : 
     277             : static int ehci_pci_suspend(struct usb_hcd *hcd)
     278             : {
     279             :         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
     280             :         unsigned long           flags;
     281             :         int                     rc = 0;
     282             : 
     283             :         if (time_before(jiffies, ehci->next_statechange))
     284             :                 msleep(10);
     285             : 
     286             :         /* Root hub was already suspended. Disable irq emission and
     287             :          * mark HW unaccessible, bail out if RH has been resumed. Use
     288             :          * the spinlock to properly synchronize with possible pending
     289             :          * RH suspend or resume activity.
     290             :          *
     291             :          * This is still racy as hcd->state is manipulated outside of
     292             :          * any locks =P But that will be a different fix.
     293             :          */
     294             :         spin_lock_irqsave (&ehci->lock, flags);
     295             :         if (hcd->state != HC_STATE_SUSPENDED) {
     296             :                 rc = -EINVAL;
     297             :                 goto bail;
     298             :         }
     299             :         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
     300             :         (void)ehci_readl(ehci, &ehci->regs->intr_enable);
     301             : 
     302             :         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
     303             :  bail:
     304             :         spin_unlock_irqrestore (&ehci->lock, flags);
     305             : 
     306             :         // could save FLADJ in case of Vaux power loss
     307             :         // ... we'd only use it to handle clock skew
     308             : 
     309             :         return rc;
     310             : }
     311             : 
     312             : static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
     313             : {
     314             :         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
     315             :         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
     316             : 
     317             :         // maybe restore FLADJ
     318             : 
     319             :         if (time_before(jiffies, ehci->next_statechange))
     320             :                 msleep(100);
     321             : 
     322             :         /* Mark hardware accessible again as we are out of D3 state by now */
     323             :         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
     324             : 
     325             :         /* If CF is still set and we aren't resuming from hibernation
     326             :          * then we maintained PCI Vaux power.
     327             :          * Just undo the effect of ehci_pci_suspend().
     328             :          */
     329             :         if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
     330             :                                 !hibernated) {
     331             :                 int     mask = INTR_MASK;
     332             : 
     333             :                 if (!hcd->self.root_hub->do_remote_wakeup)
     334             :                         mask &= ~STS_PCD;
     335             :                 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
     336             :                 ehci_readl(ehci, &ehci->regs->intr_enable);
     337             :                 return 0;
     338             :         }
     339             : 
     340             :         usb_root_hub_lost_power(hcd->self.root_hub);
     341             : 
     342             :         /* Else reset, to cope with power loss or flush-to-storage
     343             :          * style "resume" having let BIOS kick in during reboot.
     344             :          */
     345             :         (void) ehci_halt(ehci);
     346             :         (void) ehci_reset(ehci);
     347             :         (void) ehci_pci_reinit(ehci, pdev);
     348             : 
     349             :         /* emptying the schedule aborts any urbs */
     350             :         spin_lock_irq(&ehci->lock);
     351             :         if (ehci->reclaim)
     352             :                 end_unlink_async(ehci);
     353             :         ehci_work(ehci);
     354             :         spin_unlock_irq(&ehci->lock);
     355             : 
     356             :         ehci_writel(ehci, ehci->command, &ehci->regs->command);
     357             :         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
     358             :         ehci_readl(ehci, &ehci->regs->command);       /* unblock posted writes */
     359             : 
     360             :         /* here we "know" root ports should always stay powered */
     361             :         ehci_port_power(ehci, 1);
     362             : 
     363             :         hcd->state = HC_STATE_SUSPENDED;
     364             :         return 0;
     365             : }
     366             : #endif
     367             : 
     368           1 : static const struct hc_driver ehci_pci_hc_driver = {
     369             :         .description =          hcd_name,
     370             :         .product_desc =         "EHCI Host Controller",
     371             :         .hcd_priv_size =        sizeof(struct ehci_hcd),
     372             : 
     373             :         /*
     374             :          * generic hardware linkage
     375             :          */
     376             :         .irq =                  ehci_irq,
     377             :         .flags =                HCD_MEMORY | HCD_USB2,
     378             : 
     379             :         /*
     380             :          * basic lifecycle operations
     381             :          */
     382             :         .reset =                ehci_pci_setup,
     383             :         .start =                ehci_run,
     384             : #ifdef  CONFIG_PM
     385             :         .pci_suspend =          ehci_pci_suspend,
     386             :         .pci_resume =           ehci_pci_resume,
     387             : #endif
     388             :         .stop =                 ehci_stop,
     389             :         .shutdown =             ehci_shutdown,
     390             : 
     391             :         /*
     392             :          * managing i/o requests and associated device resources
     393             :          */
     394             :         .urb_enqueue =          ehci_urb_enqueue,
     395             :         .urb_dequeue =          ehci_urb_dequeue,
     396             :         .endpoint_disable =     ehci_endpoint_disable,
     397             :         .endpoint_reset =       ehci_endpoint_reset,
     398             : 
     399             :         /*
     400             :          * scheduling support
     401             :          */
     402             :         .get_frame_number =     ehci_get_frame,
     403             : 
     404             :         /*
     405             :          * root hub support
     406             :          */
     407             :         .hub_status_data =      ehci_hub_status_data,
     408             :         .hub_control =          ehci_hub_control,
     409             :         .bus_suspend =          ehci_bus_suspend,
     410             :         .bus_resume =           ehci_bus_resume,
     411             :         .relinquish_port =      ehci_relinquish_port,
     412             :         .port_handed_over =     ehci_port_handed_over,
     413             : 
     414             :         .clear_tt_buffer_complete       = ehci_clear_tt_buffer_complete,
     415             : };
     416             : 
     417             : /*-------------------------------------------------------------------------*/
     418             : 
     419             : /* PCI driver selection metadata; PCI hotplugging uses this */
     420           1 : static const struct pci_device_id pci_ids [] = { {
     421             :         /* handle any USB 2.0 EHCI controller */
     422             :         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
     423             :         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
     424             :         },
     425             :         { /* end: all zeroes */ }
     426             : };
     427             : MODULE_DEVICE_TABLE(pci, pci_ids);
     428             : 
     429             : /* pci driver glue; this is a "new style" PCI driver module */
     430           1 : static struct pci_driver ehci_pci_driver = {
     431             :         .name =         (char *) hcd_name,
     432             :         .id_table =     pci_ids,
     433             : 
     434             :         .probe =        usb_hcd_pci_probe,
     435             :         .remove =       usb_hcd_pci_remove,
     436             :         .shutdown =     usb_hcd_pci_shutdown,
     437             : 
     438             : #ifdef CONFIG_PM_SLEEP
     439             :         .driver =       {
     440             :                 .pm =   &usb_hcd_pci_pm_ops
     441             :         },
     442             : #endif
     443             : };

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