Line data Source code
1 : /*
2 : * Copyright (c) 2000-2004 by David Brownell
3 : *
4 : * This program is free software; you can redistribute it and/or modify it
5 : * under the terms of the GNU General Public License as published by the
6 : * Free Software Foundation; either version 2 of the License, or (at your
7 : * option) any later version.
8 : *
9 : * This program is distributed in the hope that it will be useful, but
10 : * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 : * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 : * for more details.
13 : *
14 : * You should have received a copy of the GNU General Public License
15 : * along with this program; if not, write to the Free Software Foundation,
16 : * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 : */
18 :
19 : #include <linux/module.h>
20 : #include <linux/pci.h>
21 : #include <linux/dmapool.h>
22 : #include <linux/kernel.h>
23 : #include <linux/delay.h>
24 : #include <linux/ioport.h>
25 : #include <linux/sched.h>
26 : #include <linux/slab.h>
27 : #include <linux/vmalloc.h>
28 : #include <linux/errno.h>
29 : #include <linux/init.h>
30 : #include <linux/timer.h>
31 : #include <linux/ktime.h>
32 : #include <linux/list.h>
33 : #include <linux/interrupt.h>
34 : #include <linux/usb.h>
35 : #include <linux/moduleparam.h>
36 : #include <linux/dma-mapping.h>
37 : #include <linux/debugfs.h>
38 :
39 : #include "../core/hcd.h"
40 :
41 : #include <asm/byteorder.h>
42 : #include <asm/io.h>
43 : #include <asm/irq.h>
44 : #include <asm/system.h>
45 : #include <asm/unaligned.h>
46 :
47 : /*-------------------------------------------------------------------------*/
48 :
49 : /*
50 : * EHCI hc_driver implementation ... experimental, incomplete.
51 : * Based on the final 1.0 register interface specification.
52 : *
53 : * USB 2.0 shows up in upcoming www.pcmcia.org technology.
54 : * First was PCMCIA, like ISA; then CardBus, which is PCI.
55 : * Next comes "CardBay", using USB 2.0 signals.
56 : *
57 : * Contains additional contributions by Brad Hards, Rory Bolt, and others.
58 : * Special thanks to Intel and VIA for providing host controllers to
59 : * test this driver on, and Cypress (including In-System Design) for
60 : * providing early devices for those host controllers to talk to!
61 : */
62 :
63 : #define DRIVER_AUTHOR "David Brownell"
64 : #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
65 :
66 1 : static const char hcd_name [] = "ehci_hcd";
67 :
68 :
69 : #undef VERBOSE_DEBUG
70 : #undef EHCI_URB_TRACE
71 :
72 : #ifdef DEBUG
73 : #define EHCI_STATS
74 : #endif
75 :
76 : /* magic numbers that can affect system performance */
77 : #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
78 : #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
79 : #define EHCI_TUNE_RL_TT 0
80 : #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
81 : #define EHCI_TUNE_MULT_TT 1
82 : #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
83 :
84 : #define EHCI_IAA_MSECS 10 /* arbitrary */
85 : #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
86 : #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
87 : #define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */
88 :
89 : /* Initial IRQ latency: faster than hw default */
90 1 : static int log2_irq_thresh = 0; // 0 to 6
91 : module_param (log2_irq_thresh, int, S_IRUGO);
92 : MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
93 :
94 : /* initial park setting: slower than hw default */
95 1 : static unsigned park = 0;
96 : module_param (park, uint, S_IRUGO);
97 : MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
98 :
99 : /* for flakey hardware, ignore overcurrent indicators */
100 1 : static int ignore_oc = 0;
101 : module_param (ignore_oc, bool, S_IRUGO);
102 : MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
103 :
104 : #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
105 :
106 : /*-------------------------------------------------------------------------*/
107 :
108 : #include "ehci.h"
109 : #include "ehci-dbg.c"
110 :
111 : /*-------------------------------------------------------------------------*/
112 :
113 : static void
114 : timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
115 : {
116 38 : /* Don't override timeouts which shrink or (later) disable
117 38 : * the async ring; just the I/O watchdog. Note that if a
118 38 : * SHRINK were pending, OFF would never be requested.
119 : */
120 228 : if (timer_pending(&ehci->watchdog)
121 : && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
122 : & ehci->actions))
123 38 : return;
124 :
125 152 : if (!test_and_set_bit(action, &ehci->actions)) {
126 : unsigned long t;
127 :
128 : switch (action) {
129 114 : case TIMER_IO_WATCHDOG:
130 76 : if (!ehci->need_io_watchdog)
131 38 : return;
132 38 : t = EHCI_IO_JIFFIES;
133 38 : break;
134 152 : case TIMER_ASYNC_OFF:
135 38 : t = EHCI_ASYNC_JIFFIES;
136 38 : break;
137 38 : /* case TIMER_ASYNC_SHRINK: */
138 38 : default:
139 38 : /* add a jiffie since we synch against the
140 : * 8 KHz uframe counter.
141 : */
142 38 : t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1;
143 38 : break;
144 : }
145 76 : mod_timer(&ehci->watchdog, t + jiffies);
146 : }
147 76 : }
148 :
149 : /*-------------------------------------------------------------------------*/
150 :
151 : /*
152 : * handshake - spin reading hc until handshake completes or fails
153 : * @ptr: address of hc register to be read
154 : * @mask: bits to look at in result of read
155 : * @done: value of those bits when handshake succeeds
156 : * @usec: timeout in microseconds
157 : *
158 : * Returns negative errno, or zero on success
159 : *
160 : * Success happens when the "mask" bits have the specified value (hardware
161 : * handshake done). There are two failure modes: "usec" have passed (major
162 : * hardware flakeout), or the register reads as all-ones (hardware removed).
163 : *
164 : * That last failure should_only happen in cases like physical cardbus eject
165 : * before driver shutdown. But it also seems to be caused by bugs in cardbus
166 : * bridge shutdown: shutting down the bridge before the devices using it.
167 : */
168 : static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
169 : u32 mask, u32 done, int usec)
170 207 : {
171 : u32 result;
172 :
173 207 : do {
174 414 : result = ehci_readl(ehci, ptr);
175 414 : if (result == ~(u32)0) /* card removed */
176 207 : return -ENODEV;
177 207 : result &= mask;
178 414 : if (result == done)
179 207 : return 0;
180 207 : udelay (1);
181 207 : usec--;
182 414 : } while (usec > 0);
183 207 : return -ETIMEDOUT;
184 207 : }
185 :
186 : /* force HC to halt state from unknown (EHCI spec section 2.3) */
187 : static int ehci_halt (struct ehci_hcd *ehci)
188 : {
189 340 : u32 temp = ehci_readl(ehci, &ehci->regs->status);
190 85 :
191 85 : /* disable any irqs left enabled by previous code */
192 170 : ehci_writel(ehci, 0, &ehci->regs->intr_enable);
193 :
194 170 : if ((temp & STS_HALT) != 0)
195 85 : return 0;
196 :
197 170 : temp = ehci_readl(ehci, &ehci->regs->command);
198 85 : temp &= ~CMD_RUN;
199 170 : ehci_writel(ehci, temp, &ehci->regs->command);
200 255 : return handshake (ehci, &ehci->regs->status,
201 : STS_HALT, STS_HALT, 16 * 125);
202 : }
203 :
204 : static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
205 : u32 mask, u32 done, int usec)
206 : {
207 76 : int error;
208 76 :
209 228 : error = handshake(ehci, ptr, mask, done, usec);
210 228 : if (error) {
211 304 : ehci_halt(ehci);
212 304 : ehci_to_hcd(ehci)->state = HC_STATE_HALT;
213 608 : ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n",
214 : ptr, mask, done, error);
215 : }
216 :
217 152 : return error;
218 : }
219 :
220 : /* put TDI/ARC silicon into EHCI mode */
221 : static void tdi_reset (struct ehci_hcd *ehci)
222 : {
223 13 : u32 __iomem *reg_ptr;
224 13 : u32 tmp;
225 :
226 13 : reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
227 26 : tmp = ehci_readl(ehci, reg_ptr);
228 13 : tmp |= USBMODE_CM_HC;
229 : /* The default byte access to MMR space is LE after
230 : * controller reset. Set the required endian mode
231 : * for transfer buffers to match the host microprocessor
232 : */
233 : if (ehci_big_endian_mmio(ehci))
234 : tmp |= USBMODE_BE;
235 26 : ehci_writel(ehci, tmp, reg_ptr);
236 13 : }
237 :
238 : /* reset a non-running (STS_HALT == 1) controller */
239 : static int ehci_reset (struct ehci_hcd *ehci)
240 : {
241 12 : int retval;
242 48 : u32 command = ehci_readl(ehci, &ehci->regs->command);
243 12 :
244 12 : /* If the EHCI debug controller is active, special care must be
245 12 : * taken before and after a host controller reset */
246 96 : if (ehci->debug && !dbgp_reset_prep())
247 24 : ehci->debug = NULL;
248 :
249 24 : command |= CMD_RESET;
250 48 : dbg_cmd (ehci, "reset", command);
251 24 : ehci_writel(ehci, command, &ehci->regs->command);
252 36 : ehci_to_hcd(ehci)->state = HC_STATE_HALT;
253 12 : ehci->next_statechange = jiffies;
254 24 : retval = handshake (ehci, &ehci->regs->command,
255 : CMD_RESET, 0, 250 * 1000);
256 :
257 24 : if (ehci->has_hostpc) {
258 24 : ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
259 : (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX));
260 24 : ehci_writel(ehci, TXFIFO_DEFAULT,
261 : (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));
262 : }
263 48 : if (retval)
264 24 : return retval;
265 :
266 72 : if (ehci_is_TDI(ehci))
267 24 : tdi_reset (ehci);
268 :
269 72 : if (ehci->debug)
270 48 : dbgp_external_startup();
271 :
272 36 : return retval;
273 : }
274 :
275 : /* idle the controller (from running) */
276 : static void ehci_quiesce (struct ehci_hcd *ehci)
277 : {
278 5 : u32 temp;
279 5 :
280 5 : #ifdef DEBUG
281 : if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
282 : BUG ();
283 : #endif
284 :
285 : /* wait for any schedule enables/disables to take effect */
286 15 : temp = ehci_readl(ehci, &ehci->regs->command) << 10;
287 5 : temp &= STS_ASS | STS_PSS;
288 25 : if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
289 : STS_ASS | STS_PSS, temp, 16 * 125))
290 5 : return;
291 :
292 : /* then disable anything that's still active */
293 10 : temp = ehci_readl(ehci, &ehci->regs->command);
294 5 : temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
295 10 : ehci_writel(ehci, temp, &ehci->regs->command);
296 :
297 : /* hardware can take 16 microframes to turn off ... */
298 15 : handshake_on_error_set_halt(ehci, &ehci->regs->status,
299 5 : STS_ASS | STS_PSS, 0, 16 * 125);
300 : }
301 :
302 : /*-------------------------------------------------------------------------*/
303 :
304 : static void end_unlink_async(struct ehci_hcd *ehci);
305 : static void ehci_work(struct ehci_hcd *ehci);
306 :
307 : #include "ehci-hub.c"
308 : #include "ehci-mem.c"
309 : #include "ehci-q.c"
310 : #include "ehci-sched.c"
311 :
312 : /*-------------------------------------------------------------------------*/
313 :
314 : static void ehci_iaa_watchdog(unsigned long param)
315 : {
316 0 : struct ehci_hcd *ehci = (struct ehci_hcd *) param;
317 0 : unsigned long flags;
318 0 :
319 0 : spin_lock_irqsave (&ehci->lock, flags);
320 0 :
321 0 : /* Lost IAA irqs wedge things badly; seen first with a vt8235.
322 0 : * So we need this watchdog, but must protect it against both
323 : * (a) SMP races against real IAA firing and retriggering, and
324 : * (b) clean HC shutdown, when IAA watchdog was pending.
325 : */
326 0 : if (ehci->reclaim
327 : && !timer_pending(&ehci->iaa_watchdog)
328 : && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
329 : u32 cmd, status;
330 :
331 : /* If we get here, IAA is *REALLY* late. It's barely
332 : * conceivable that the system is so busy that CMD_IAAD
333 : * is still legitimately set, so let's be sure it's
334 : * clear before we read STS_IAA. (The HC should clear
335 : * CMD_IAAD when it sets STS_IAA.)
336 : */
337 0 : cmd = ehci_readl(ehci, &ehci->regs->command);
338 0 : if (cmd & CMD_IAAD)
339 0 : ehci_writel(ehci, cmd & ~CMD_IAAD,
340 : &ehci->regs->command);
341 :
342 : /* If IAA is set here it either legitimately triggered
343 : * before we cleared IAAD above (but _way_ late, so we'll
344 : * still count it as lost) ... or a silicon erratum:
345 : * - VIA seems to set IAA without triggering the IRQ;
346 : * - IAAD potentially cleared without setting IAA.
347 : */
348 0 : status = ehci_readl(ehci, &ehci->regs->status);
349 0 : if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
350 : COUNT (ehci->stats.lost_iaa);
351 0 : ehci_writel(ehci, STS_IAA, &ehci->regs->status);
352 : }
353 :
354 : ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
355 : status, cmd);
356 0 : end_unlink_async(ehci);
357 : }
358 :
359 0 : spin_unlock_irqrestore(&ehci->lock, flags);
360 0 : }
361 :
362 : static void ehci_watchdog(unsigned long param)
363 : {
364 0 : struct ehci_hcd *ehci = (struct ehci_hcd *) param;
365 0 : unsigned long flags;
366 0 :
367 0 : spin_lock_irqsave(&ehci->lock, flags);
368 :
369 : /* stop async processing after it's idled a bit */
370 0 : if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
371 0 : start_unlink_async (ehci, ehci->async);
372 :
373 : /* ehci could run by timer, without IRQs ... */
374 0 : ehci_work (ehci);
375 :
376 0 : spin_unlock_irqrestore (&ehci->lock, flags);
377 0 : }
378 :
379 : /* On some systems, leaving remote wakeup enabled prevents system shutdown.
380 : * The firmware seems to think that powering off is a wakeup event!
381 : * This routine turns off remote wakeup and everything else, on all ports.
382 : */
383 : static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
384 : {
385 9 : int port = HCS_N_PORTS(ehci->hcs_params);
386 3 :
387 15 : while (port--)
388 9 : ehci_writel(ehci, PORT_RWC_BITS,
389 3 : &ehci->regs->port_status[port]);
390 3 : }
391 :
392 : /*
393 : * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
394 3 : * Should be called with ehci->lock held.
395 : */
396 : static void ehci_silence_controller(struct ehci_hcd *ehci)
397 : {
398 9 : ehci_halt(ehci);
399 6 : ehci_turn_off_all_ports(ehci);
400 :
401 : /* make BIOS/etc use companion controller during reboot */
402 6 : ehci_writel(ehci, 0, &ehci->regs->configured_flag);
403 :
404 : /* unblock posted writes */
405 6 : ehci_readl(ehci, &ehci->regs->configured_flag);
406 3 : }
407 :
408 : /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
409 : * This forcibly disables dma and IRQs, helping kexec and other cases
410 : * where the next system software may expect clean state.
411 : */
412 : static void ehci_shutdown(struct usb_hcd *hcd)
413 : {
414 4 : struct ehci_hcd *ehci = hcd_to_ehci(hcd);
415 1 :
416 2 : del_timer_sync(&ehci->watchdog);
417 2 : del_timer_sync(&ehci->iaa_watchdog);
418 :
419 2 : spin_lock_irq(&ehci->lock);
420 2 : ehci_silence_controller(ehci);
421 2 : spin_unlock_irq(&ehci->lock);
422 1 : }
423 :
424 : static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
425 : {
426 3 : unsigned port;
427 3 :
428 9 : if (!HCS_PPC (ehci->hcs_params))
429 3 : return;
430 :
431 : ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
432 12 : for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
433 36 : (void) ehci_hub_control(ehci_to_hcd(ehci),
434 3 : is_on ? SetPortFeature : ClearPortFeature,
435 : USB_PORT_FEAT_POWER,
436 3 : port--, NULL, 0);
437 : /* Flush those writes */
438 6 : ehci_readl(ehci, &ehci->regs->command);
439 3 : msleep(20);
440 3 : }
441 :
442 : /*-------------------------------------------------------------------------*/
443 :
444 : /*
445 : * ehci_work is called from some interrupts, timers, and so on.
446 : * it calls driver completion functions, after dropping ehci->lock.
447 : */
448 : static void ehci_work (struct ehci_hcd *ehci)
449 : {
450 9 : timer_action_done (ehci, TIMER_IO_WATCHDOG);
451 :
452 : /* another CPU may drop ehci->lock during a schedule scan while
453 : * it reports urb completions. this flag guards against bogus
454 : * attempts at re-entrant schedule scanning.
455 : */
456 6 : if (ehci->scanning)
457 3 : return;
458 3 : ehci->scanning = 1;
459 15 : scan_async (ehci);
460 6 : if (ehci->next_uframe != -1)
461 12 : scan_periodic (ehci);
462 6 : ehci->scanning = 0;
463 :
464 : /* the IO watchdog guards against hardware or driver bugs that
465 : * misplace IRQs, and should let us run completely without IRQs.
466 : * such lossage has been observed on both VT6202 and VT8235.
467 : */
468 30 : if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
469 : (ehci->async->qh_next.ptr != NULL ||
470 : ehci->periodic_sched != 0))
471 12 : timer_action (ehci, TIMER_IO_WATCHDOG);
472 6 : }
473 :
474 : /*
475 : * Called when the ehci_hcd module is removed.
476 : */
477 : static void ehci_stop (struct usb_hcd *hcd)
478 : {
479 4 : struct ehci_hcd *ehci = hcd_to_ehci (hcd);
480 1 :
481 1 : ehci_dbg (ehci, "stop\n");
482 1 :
483 : /* no more interrupts ... */
484 2 : del_timer_sync (&ehci->watchdog);
485 2 : del_timer_sync(&ehci->iaa_watchdog);
486 :
487 2 : spin_lock_irq(&ehci->lock);
488 2 : if (HC_IS_RUNNING (hcd->state))
489 3 : ehci_quiesce (ehci);
490 :
491 4 : ehci_silence_controller(ehci);
492 6 : ehci_reset (ehci);
493 2 : spin_unlock_irq(&ehci->lock);
494 :
495 3 : remove_companion_file(ehci);
496 2 : remove_debug_files (ehci);
497 :
498 : /* root hub is shut down separately (first, when possible) */
499 2 : spin_lock_irq (&ehci->lock);
500 3 : if (ehci->async)
501 4 : ehci_work (ehci);
502 4 : spin_unlock_irq (&ehci->lock);
503 4 : ehci_mem_cleanup (ehci);
504 :
505 : #ifdef EHCI_STATS
506 : ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
507 : ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
508 : ehci->stats.lost_iaa);
509 : ehci_dbg (ehci, "complete %ld unlink %ld\n",
510 : ehci->stats.complete, ehci->stats.unlink);
511 : #endif
512 :
513 4 : dbg_status (ehci, "ehci_stop completed",
514 : ehci_readl(ehci, &ehci->regs->status));
515 : }
516 1 :
517 : /* one-time init, only for memory state */
518 : static int ehci_init(struct usb_hcd *hcd)
519 : {
520 4 : struct ehci_hcd *ehci = hcd_to_ehci(hcd);
521 1 : u32 temp;
522 1 : int retval;
523 1 : u32 hcc_params;
524 1 : struct ehci_qh_hw *hw;
525 1 :
526 5 : spin_lock_init(&ehci->lock);
527 1 :
528 1 : /*
529 : * keep io watchdog by default, those good HCDs could turn off it later
530 : */
531 1 : ehci->need_io_watchdog = 1;
532 1 : init_timer(&ehci->watchdog);
533 1 : ehci->watchdog.function = ehci_watchdog;
534 1 : ehci->watchdog.data = (unsigned long) ehci;
535 :
536 1 : init_timer(&ehci->iaa_watchdog);
537 1 : ehci->iaa_watchdog.function = ehci_iaa_watchdog;
538 1 : ehci->iaa_watchdog.data = (unsigned long) ehci;
539 :
540 2 : hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
541 :
542 : /*
543 : * hw default: 1K periodic list heads, one per frame.
544 : * periodic_size can shrink by USBCMD update if hcc_params allows.
545 : */
546 1 : ehci->periodic_size = DEFAULT_I_TDPS;
547 2 : INIT_LIST_HEAD(&ehci->cached_itd_list);
548 2 : INIT_LIST_HEAD(&ehci->cached_sitd_list);
549 :
550 2 : if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
551 : /* periodic schedule size can be smaller than default */
552 : switch (EHCI_TUNE_FLS) {
553 1 : case 0: ehci->periodic_size = 1024; break;
554 1 : case 1: ehci->periodic_size = 512; break;
555 5 : case 2: ehci->periodic_size = 256; break;
556 : default: BUG();
557 : }
558 : }
559 5 : if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
560 1 : return retval;
561 :
562 : /* controllers may cache some of the periodic schedule ... */
563 2 : if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
564 1 : ehci->i_thresh = 2 + 8;
565 : else // N microframes cached
566 1 : ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
567 :
568 1 : ehci->reclaim = NULL;
569 1 : ehci->next_uframe = -1;
570 1 : ehci->clock_frame = -1;
571 :
572 : /*
573 : * dedicate a qh for the async ring head, since we couldn't unlink
574 : * a 'real' qh without stopping the async schedule [4.8]. use it
575 : * as the 'reclamation list head' too.
576 : * its dummy is used in hw_alt_next of many tds, to prevent the qh
577 : * from automatically advancing to the next td after short reads.
578 : */
579 1 : ehci->async->qh_next.qh = NULL;
580 1 : hw = ehci->async->hw;
581 3 : hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
582 2 : hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
583 2 : hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
584 2 : hw->hw_qtd_next = EHCI_LIST_END(ehci);
585 1 : ehci->async->qh_state = QH_STATE_LINKED;
586 3 : hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
587 :
588 : /* clear interrupt enables, set irq latency */
589 2 : if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
590 1 : log2_irq_thresh = 0;
591 1 : temp = 1 << (16 + log2_irq_thresh);
592 2 : if (HCC_CANPARK(hcc_params)) {
593 : /* HW default park == 3, on hardware that supports it (like
594 : * NVidia and ALI silicon), maximizes throughput on the async
595 : * schedule by avoiding QH fetches between transfers.
596 : *
597 : * With fast usb storage devices and NForce2, "park" seems to
598 : * make problems: throughput reduction (!), data errors...
599 : */
600 2 : if (park) {
601 8 : park = min(park, (unsigned) 3);
602 1 : temp |= CMD_PARK;
603 1 : temp |= park << 8;
604 : }
605 : ehci_dbg(ehci, "park %d\n", park);
606 : }
607 2 : if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
608 : /* periodic schedule size can be smaller than default */
609 1 : temp &= ~(3 << 2);
610 1 : temp |= (EHCI_TUNE_FLS << 2);
611 : }
612 1 : ehci->command = temp;
613 :
614 : /* Accept arbitrarily long scatter-gather lists */
615 1 : hcd->self.sg_tablesize = ~0;
616 1 : return 0;
617 : }
618 :
619 : /* start HC running; it's halted, ehci_init() has been run (once) */
620 : static int ehci_run (struct usb_hcd *hcd)
621 : {
622 4 : struct ehci_hcd *ehci = hcd_to_ehci (hcd);
623 1 : int retval;
624 1 : u32 temp;
625 1 : u32 hcc_params;
626 1 :
627 2 : hcd->uses_new_polling = 1;
628 2 : hcd->poll_rh = 0;
629 1 :
630 1 : /* EHCI spec section 4.1 */
631 9 : if ((retval = ehci_reset(ehci)) != 0) {
632 5 : ehci_mem_cleanup(ehci);
633 1 : return retval;
634 : }
635 3 : ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
636 3 : ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
637 :
638 : /*
639 : * hcc_params controls whether ehci->regs->segment must (!!!)
640 : * be used; it constrains QH/ITD/SITD and QTD locations.
641 : * pci_pool consistent memory always uses segment zero.
642 : * streaming mappings for I/O buffers, like pci_map_single(),
643 : * can return segments above 4GB, if the device allows.
644 : *
645 : * NOTE: the dma mask is visible through dma_supported(), so
646 : * drivers can pass this info along ... like NETIF_F_HIGHDMA,
647 : * Scsi_Host.highmem_io, and so forth. It's readonly to all
648 : * host side drivers though.
649 : */
650 2 : hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
651 2 : if (HCC_64BIT_ADDR(hcc_params)) {
652 2 : ehci_writel(ehci, 0, &ehci->regs->segment);
653 : #if 0
654 : // this is deeply broken on almost all architectures
655 : if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
656 : ehci_info(ehci, "enabled 64bit DMA\n");
657 : #endif
658 : }
659 :
660 :
661 : // Philips, Intel, and maybe others need CMD_RUN before the
662 : // root hub will detect new devices (why?); NEC doesn't
663 2 : ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
664 2 : ehci->command |= CMD_RUN;
665 4 : ehci_writel(ehci, ehci->command, &ehci->regs->command);
666 2 : dbg_cmd (ehci, "init", ehci->command);
667 :
668 : /*
669 : * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
670 : * are explicitly handed to companion controller(s), so no TT is
671 : * involved with the root hub. (Except where one is integrated,
672 : * and there's no companion controller unless maybe for USB OTG.)
673 : *
674 : * Turning on the CF flag will transfer ownership of all ports
675 : * from the companions to the EHCI controller. If any of the
676 : * companions are in the middle of a port reset at the time, it
677 : * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
678 : * guarantees that no resets are in progress. After we set CF,
679 : * a short delay lets the hardware catch up; new resets shouldn't
680 : * be started before the port switching actions could complete.
681 : */
682 1 : down_write(&ehci_cf_port_reset_rwsem);
683 1 : hcd->state = HC_STATE_RUNNING;
684 2 : ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
685 2 : ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
686 1 : msleep(5);
687 1 : up_write(&ehci_cf_port_reset_rwsem);
688 1 : ehci->last_periodic_enable = ktime_get_real();
689 :
690 3 : temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
691 11 : ehci_info (ehci,
692 4 : "USB %x.%x started, EHCI %x.%02x%s\n",
693 : ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
694 : temp >> 8, temp & 0xff,
695 : ignore_oc ? ", overcurrent ignored" : "");
696 :
697 2 : ehci_writel(ehci, INTR_MASK,
698 : &ehci->regs->intr_enable); /* Turn On Interrupts */
699 :
700 : /* GRR this is run-once init(), being done every time the HC starts.
701 : * So long as they're part of class devices, we can't do it init()
702 : * since the class device isn't created that early.
703 : */
704 2 : create_debug_files(ehci);
705 3 : create_companion_file(ehci);
706 :
707 1 : return 0;
708 : }
709 :
710 : /*-------------------------------------------------------------------------*/
711 :
712 : static irqreturn_t ehci_irq (struct usb_hcd *hcd)
713 : {
714 4 : struct ehci_hcd *ehci = hcd_to_ehci (hcd);
715 2 : u32 status, masked_status, pcd_status = 0, cmd;
716 1 : int bh;
717 1 :
718 3 : spin_lock (&ehci->lock);
719 1 :
720 3 : status = ehci_readl(ehci, &ehci->regs->status);
721 1 :
722 1 : /* e.g. cardbus physical eject */
723 3 : if (status == ~(u32) 0) {
724 1 : ehci_dbg (ehci, "device removed\n");
725 2 : goto dead;
726 1 : }
727 1 :
728 2 : masked_status = status & INTR_MASK;
729 3 : if (!masked_status) { /* irq sharing? */
730 3 : spin_unlock(&ehci->lock);
731 2 : return IRQ_NONE;
732 1 : }
733 1 :
734 1 : /* clear (just) interrupts */
735 3 : ehci_writel(ehci, masked_status, &ehci->regs->status);
736 2 : cmd = ehci_readl(ehci, &ehci->regs->command);
737 1 : bh = 0;
738 :
739 : #ifdef VERBOSE_DEBUG
740 : /* unrequested/ignored: Frame List Rollover */
741 : dbg_status (ehci, "irq", status);
742 : #endif
743 :
744 : /* INT, ERR, and IAA interrupt rates can be throttled */
745 :
746 : /* normal [4.15.1.2] or error [4.15.1.1] completion */
747 4 : if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
748 2 : if (likely ((status & STS_ERR) == 0))
749 : COUNT (ehci->stats.normal);
750 : else
751 : COUNT (ehci->stats.error);
752 1 : bh = 1;
753 : }
754 :
755 : /* complete the unlinking of some qh [4.15.2.3] */
756 4 : if (status & STS_IAA) {
757 : /* guard against (alleged) silicon errata */
758 4 : if (cmd & CMD_IAAD) {
759 4 : ehci_writel(ehci, cmd & ~CMD_IAAD,
760 : &ehci->regs->command);
761 : ehci_dbg(ehci, "IAA with IAAD still set?\n");
762 : }
763 9 : if (ehci->reclaim) {
764 : COUNT(ehci->stats.reclaim);
765 9 : end_unlink_async(ehci);
766 : } else
767 : ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
768 : }
769 :
770 : /* remote wakeup [4.3.1] */
771 8 : if (status & STS_PCD) {
772 4 : unsigned i = HCS_N_PORTS (ehci->hcs_params);
773 :
774 : /* kick root hub later */
775 4 : pcd_status = status;
776 :
777 : /* resume root hub? */
778 8 : if (!(cmd & CMD_RUN))
779 8 : usb_hcd_resume_root_hub(hcd);
780 :
781 9 : while (i--) {
782 4 : int pstatus = ehci_readl(ehci,
783 1 : &ehci->regs->port_status [i]);
784 :
785 2 : if (pstatus & PORT_OWNER)
786 1 : continue;
787 10 : if (!(test_bit(i, &ehci->suspended_ports) &&
788 : ((pstatus & PORT_RESUME) ||
789 : !(pstatus & PORT_SUSPEND)) &&
790 : (pstatus & PORT_PE) &&
791 : ehci->reset_done[i] == 0))
792 1 : continue;
793 :
794 : /* start 20 msec resume signaling from this port,
795 : * and make khubd collect PORT_STAT_C_SUSPEND to
796 : * stop that signaling. Use 5 ms extra for safety,
797 : * like usb_port_resume() does.
798 : */
799 2 : ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
800 : ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
801 2 : mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
802 : }
803 1 : }
804 :
805 : /* PCI errors [4.15.2.4] */
806 12 : if (unlikely ((status & STS_FATAL) != 0)) {
807 8 : ehci_err(ehci, "fatal error\n");
808 2 : dbg_cmd(ehci, "fatal", cmd);
809 2 : dbg_status(ehci, "fatal", status);
810 3 : ehci_halt(ehci);
811 : dead:
812 13 : ehci_reset(ehci);
813 2 : ehci_writel(ehci, 0, &ehci->regs->configured_flag);
814 : /* generic layer kills/unlinks all urbs, then
815 : * uses ehci_stop to clean up the rest
816 : */
817 1 : bh = 1;
818 : }
819 :
820 4 : if (bh)
821 8 : ehci_work (ehci);
822 6 : spin_unlock (&ehci->lock);
823 2 : if (pcd_status)
824 1 : usb_hcd_poll_rh_status(hcd);
825 1 : return IRQ_HANDLED;
826 : }
827 :
828 : /*-------------------------------------------------------------------------*/
829 :
830 : /*
831 : * non-error returns are a promise to giveback() the urb later
832 : * we drop ownership so next owner (or urb unlink) can get it
833 : *
834 : * urb + dev is in hcd.self.controller.urb_list
835 : * we're queueing TDs onto software and hardware lists
836 : *
837 : * hcd-specific init for hcpriv hasn't been done yet
838 : *
839 : * NOTE: control, bulk, and interrupt share the same code to append TDs
840 : * to a (possibly active) QH, and the same QH scanning code.
841 : */
842 : static int ehci_urb_enqueue (
843 : struct usb_hcd *hcd,
844 1 : struct urb *urb,
845 1 : gfp_t mem_flags
846 1 : ) {
847 4 : struct ehci_hcd *ehci = hcd_to_ehci (hcd);
848 1 : struct list_head qtd_list;
849 1 :
850 3 : INIT_LIST_HEAD (&qtd_list);
851 1 :
852 1 : switch (usb_pipetype (urb->pipe)) {
853 3 : case PIPE_CONTROL:
854 : /* qh_completions() code doesn't handle all the fault cases
855 : * in multi-TD control transfers. Even 1KB is rare anyway.
856 : */
857 2 : if (urb->transfer_buffer_length > (16 * 1024))
858 1 : return -EMSGSIZE;
859 : /* FALLTHROUGH */
860 : /* case PIPE_BULK: */
861 1 : default:
862 9 : if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
863 1 : return -ENOMEM;
864 4 : return submit_async(ehci, urb, &qtd_list, mem_flags);
865 1 :
866 3 : case PIPE_INTERRUPT:
867 7 : if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
868 1 : return -ENOMEM;
869 4 : return intr_submit(ehci, urb, &qtd_list, mem_flags);
870 1 :
871 3 : case PIPE_ISOCHRONOUS:
872 3 : if (urb->dev->speed == USB_SPEED_HIGH)
873 5 : return itd_submit (ehci, urb, mem_flags);
874 : else
875 6 : return sitd_submit (ehci, urb, mem_flags);
876 : }
877 : }
878 :
879 : static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
880 : {
881 6 : /* failfast */
882 48 : if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim)
883 18 : end_unlink_async(ehci);
884 :
885 : /* If the QH isn't linked then there's nothing we can do
886 : * unless we were called during a giveback, in which case
887 : * qh_completions() has to deal with it.
888 : */
889 36 : if (qh->qh_state != QH_STATE_LINKED) {
890 36 : if (qh->qh_state == QH_STATE_COMPLETING)
891 12 : qh->needs_rescan = 1;
892 12 : return;
893 : }
894 :
895 : /* defer till later if busy */
896 36 : if (ehci->reclaim) {
897 : struct ehci_qh *last;
898 :
899 42 : for (last = ehci->reclaim;
900 6 : last->reclaim;
901 6 : last = last->reclaim)
902 18 : continue;
903 12 : qh->qh_state = QH_STATE_UNLINK_WAIT;
904 6 : last->reclaim = qh;
905 :
906 : /* start IAA cycle */
907 : } else
908 60 : start_unlink_async (ehci, qh);
909 12 : }
910 :
911 : /* remove from hardware lists
912 : * completions normally happen asynchronously
913 : */
914 :
915 : static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
916 : {
917 4 : struct ehci_hcd *ehci = hcd_to_ehci (hcd);
918 1 : struct ehci_qh *qh;
919 1 : unsigned long flags;
920 1 : int rc;
921 1 :
922 4 : spin_lock_irqsave (&ehci->lock, flags);
923 1 : rc = usb_hcd_check_unlink_urb(hcd, urb, status);
924 2 : if (rc)
925 1 : goto done;
926 :
927 : switch (usb_pipetype (urb->pipe)) {
928 : // case PIPE_CONTROL:
929 : // case PIPE_BULK:
930 1 : default:
931 3 : qh = (struct ehci_qh *) urb->hcpriv;
932 2 : if (!qh)
933 1 : break;
934 1 : switch (qh->qh_state) {
935 5 : case QH_STATE_LINKED:
936 5 : case QH_STATE_COMPLETING:
937 5 : unlink_async(ehci, qh);
938 1 : break;
939 5 : case QH_STATE_UNLINK:
940 5 : case QH_STATE_UNLINK_WAIT:
941 : /* already started */
942 1 : break;
943 5 : case QH_STATE_IDLE:
944 : /* QH might be waiting for a Clear-TT-Buffer */
945 5 : qh_completions(ehci, qh);
946 1 : break;
947 1 : }
948 3 : break;
949 2 :
950 3 : case PIPE_INTERRUPT:
951 2 : qh = (struct ehci_qh *) urb->hcpriv;
952 2 : if (!qh)
953 1 : break;
954 : switch (qh->qh_state) {
955 4 : case QH_STATE_LINKED:
956 4 : case QH_STATE_COMPLETING:
957 6 : intr_deschedule (ehci, qh);
958 1 : break;
959 5 : case QH_STATE_IDLE:
960 5 : qh_completions (ehci, qh);
961 1 : break;
962 2 : default:
963 1 : ehci_dbg (ehci, "bogus qh %p state %d\n",
964 1 : qh, qh->qh_state);
965 1 : goto done;
966 : }
967 2 : break;
968 1 :
969 3 : case PIPE_ISOCHRONOUS:
970 : // itd or sitd ...
971 :
972 : // wait till next completion, do it then.
973 : // completion irqs can wait up to 1024 msec,
974 1 : break;
975 : }
976 : done:
977 10 : spin_unlock_irqrestore (&ehci->lock, flags);
978 6 : return rc;
979 : }
980 :
981 : /*-------------------------------------------------------------------------*/
982 :
983 : // bulk qh holds the data toggle
984 :
985 : static void
986 : ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
987 : {
988 4 : struct ehci_hcd *ehci = hcd_to_ehci (hcd);
989 1 : unsigned long flags;
990 2 : struct ehci_qh *qh, *tmp;
991 1 :
992 1 : /* ASSERT: any requests/urbs are being unlinked */
993 1 : /* ASSERT: nobody can be submitting urbs for this any more */
994 1 :
995 1 : rescan:
996 4 : spin_lock_irqsave (&ehci->lock, flags);
997 3 : qh = ep->hcpriv;
998 3 : if (!qh)
999 2 : goto done;
1000 :
1001 : /* endpoints can be iso streams. for now, we don't
1002 : * accelerate iso completions ... so spin a while.
1003 : */
1004 3 : if (qh->hw == NULL) {
1005 : ehci_vdbg (ehci, "iso delay\n");
1006 1 : goto idle_timeout;
1007 : }
1008 :
1009 2 : if (!HC_IS_RUNNING (hcd->state))
1010 1 : qh->qh_state = QH_STATE_IDLE;
1011 : switch (qh->qh_state) {
1012 4 : case QH_STATE_LINKED:
1013 4 : case QH_STATE_COMPLETING:
1014 6 : for (tmp = ehci->async->qh_next.qh;
1015 1 : tmp && tmp != qh;
1016 1 : tmp = tmp->qh_next.qh)
1017 3 : continue;
1018 1 : /* periodic qh self-unlinks on empty, and a COMPLETING qh
1019 : * may already be unlinked.
1020 : */
1021 2 : if (tmp)
1022 5 : unlink_async(ehci, qh);
1023 : /* FALL THROUGH */
1024 4 : case QH_STATE_UNLINK: /* wait for hw to finish? */
1025 4 : case QH_STATE_UNLINK_WAIT:
1026 : idle_timeout:
1027 8 : spin_unlock_irqrestore (&ehci->lock, flags);
1028 4 : schedule_timeout_uninterruptible(1);
1029 4 : goto rescan;
1030 5 : case QH_STATE_IDLE: /* fully unlinked */
1031 2 : if (qh->clearing_tt)
1032 1 : goto idle_timeout;
1033 4 : if (list_empty (&qh->qtd_list)) {
1034 3 : qh_put (qh);
1035 1 : break;
1036 : }
1037 : /* else FALL THROUGH */
1038 1 : default:
1039 2 : /* caller was supposed to have unlinked any requests;
1040 1 : * that's not our job. just leak this memory.
1041 : */
1042 14 : ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1043 4 : qh, ep->desc.bEndpointAddress, qh->qh_state,
1044 : list_empty (&qh->qtd_list) ? "" : "(has tds)");
1045 1 : break;
1046 : }
1047 2 : ep->hcpriv = NULL;
1048 2 : done:
1049 6 : spin_unlock_irqrestore (&ehci->lock, flags);
1050 1 : return;
1051 : }
1052 :
1053 : static void
1054 : ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1055 : {
1056 4 : struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1057 1 : struct ehci_qh *qh;
1058 4 : int eptype = usb_endpoint_type(&ep->desc);
1059 4 : int epnum = usb_endpoint_num(&ep->desc);
1060 4 : int is_out = usb_endpoint_dir_out(&ep->desc);
1061 1 : unsigned long flags;
1062 1 :
1063 3 : if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1064 2 : return;
1065 1 :
1066 4 : spin_lock_irqsave(&ehci->lock, flags);
1067 3 : qh = ep->hcpriv;
1068 1 :
1069 1 : /* For Bulk and Interrupt endpoints we maintain the toggle state
1070 1 : * in the hardware; the toggle bits in udev aren't used at all.
1071 1 : * When an endpoint is reset by usb_clear_halt() we must reset
1072 1 : * the toggle bit in the QH.
1073 1 : */
1074 2 : if (qh) {
1075 1 : usb_settoggle(qh->dev, epnum, is_out, 0);
1076 4 : if (!list_empty(&qh->qtd_list)) {
1077 20 : WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1078 6 : } else if (qh->qh_state == QH_STATE_LINKED ||
1079 : qh->qh_state == QH_STATE_COMPLETING) {
1080 :
1081 : /* The toggle value in the QH can't be updated
1082 : * while the QH is active. Unlink it now;
1083 : * re-linking will call qh_refresh().
1084 : */
1085 2 : if (eptype == USB_ENDPOINT_XFER_BULK)
1086 5 : unlink_async(ehci, qh);
1087 : else
1088 6 : intr_deschedule(ehci, qh);
1089 : }
1090 : }
1091 10 : spin_unlock_irqrestore(&ehci->lock, flags);
1092 1 : }
1093 :
1094 : static int ehci_get_frame (struct usb_hcd *hcd)
1095 : {
1096 4 : struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1097 4 : return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) %
1098 1 : ehci->periodic_size;
1099 : }
1100 :
1101 : /*-------------------------------------------------------------------------*/
1102 :
1103 : MODULE_DESCRIPTION(DRIVER_DESC);
1104 : MODULE_AUTHOR (DRIVER_AUTHOR);
1105 : MODULE_LICENSE ("GPL");
1106 :
1107 : #ifdef CONFIG_PCI
1108 : #include "ehci-pci.c"
1109 : #define PCI_DRIVER ehci_pci_driver
1110 : #endif
1111 :
1112 : #ifdef CONFIG_USB_EHCI_FSL
1113 : #include "ehci-fsl.c"
1114 : #define PLATFORM_DRIVER ehci_fsl_driver
1115 : #endif
1116 :
1117 : #ifdef CONFIG_USB_EHCI_MXC
1118 : #include "ehci-mxc.c"
1119 : #define PLATFORM_DRIVER ehci_mxc_driver
1120 : #endif
1121 :
1122 : #ifdef CONFIG_SOC_AU1200
1123 : #include "ehci-au1xxx.c"
1124 : #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1125 : #endif
1126 :
1127 : #ifdef CONFIG_ARCH_OMAP34XX
1128 : #include "ehci-omap.c"
1129 : #define PLATFORM_DRIVER ehci_hcd_omap_driver
1130 : #endif
1131 :
1132 : #ifdef CONFIG_PPC_PS3
1133 : #include "ehci-ps3.c"
1134 : #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1135 : #endif
1136 :
1137 : #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1138 : #include "ehci-ppc-of.c"
1139 : #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1140 : #endif
1141 :
1142 : #ifdef CONFIG_XPS_USB_HCD_XILINX
1143 : #include "ehci-xilinx-of.c"
1144 : #define OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
1145 : #endif
1146 :
1147 : #ifdef CONFIG_PLAT_ORION
1148 : #include "ehci-orion.c"
1149 : #define PLATFORM_DRIVER ehci_orion_driver
1150 : #endif
1151 :
1152 : #ifdef CONFIG_ARCH_IXP4XX
1153 : #include "ehci-ixp4xx.c"
1154 : #define PLATFORM_DRIVER ixp4xx_ehci_driver
1155 : #endif
1156 :
1157 : #ifdef CONFIG_USB_W90X900_EHCI
1158 : #include "ehci-w90x900.c"
1159 : #define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1160 : #endif
1161 :
1162 : #ifdef CONFIG_ARCH_AT91
1163 : #include "ehci-atmel.c"
1164 : #define PLATFORM_DRIVER ehci_atmel_driver
1165 : #endif
1166 :
1167 : #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1168 : !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
1169 : #error "missing bus glue for ehci-hcd"
1170 : #endif
1171 :
1172 : static int __init ehci_hcd_init(void)
1173 : {
1174 2 : int retval = 0;
1175 1 :
1176 4 : if (usb_disabled())
1177 2 : return -ENODEV;
1178 :
1179 1 : printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1180 2 : set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1181 8 : if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1182 : test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1183 2 : printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1184 : " before uhci_hcd and ohci_hcd, not after\n");
1185 :
1186 : pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1187 : hcd_name,
1188 : sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1189 : sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1190 :
1191 : #ifdef DEBUG
1192 : ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1193 : if (!ehci_debug_root) {
1194 : retval = -ENOENT;
1195 : goto err_debug;
1196 : }
1197 : #endif
1198 :
1199 : #ifdef PLATFORM_DRIVER
1200 : retval = platform_driver_register(&PLATFORM_DRIVER);
1201 : if (retval < 0)
1202 : goto clean0;
1203 : #endif
1204 :
1205 : #ifdef PCI_DRIVER
1206 4 : retval = pci_register_driver(&PCI_DRIVER);
1207 2 : if (retval < 0)
1208 1 : goto clean1;
1209 : #endif
1210 :
1211 : #ifdef PS3_SYSTEM_BUS_DRIVER
1212 : retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1213 : if (retval < 0)
1214 : goto clean2;
1215 : #endif
1216 :
1217 : #ifdef OF_PLATFORM_DRIVER
1218 : retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
1219 : if (retval < 0)
1220 : goto clean3;
1221 : #endif
1222 1 : return retval;
1223 :
1224 : #ifdef OF_PLATFORM_DRIVER
1225 : /* of_unregister_platform_driver(&OF_PLATFORM_DRIVER); */
1226 : clean3:
1227 : #endif
1228 : #ifdef PS3_SYSTEM_BUS_DRIVER
1229 : ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1230 : clean2:
1231 : #endif
1232 : #ifdef PCI_DRIVER
1233 : pci_unregister_driver(&PCI_DRIVER);
1234 : clean1:
1235 1 : #endif
1236 : #ifdef PLATFORM_DRIVER
1237 : platform_driver_unregister(&PLATFORM_DRIVER);
1238 : clean0:
1239 : #endif
1240 : #ifdef DEBUG
1241 : debugfs_remove(ehci_debug_root);
1242 : ehci_debug_root = NULL;
1243 : err_debug:
1244 : #endif
1245 2 : clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1246 1 : return retval;
1247 : }
1248 : module_init(ehci_hcd_init);
1249 :
1250 : static void __exit ehci_hcd_cleanup(void)
1251 : {
1252 : #ifdef OF_PLATFORM_DRIVER
1253 : of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1254 : #endif
1255 : #ifdef PLATFORM_DRIVER
1256 : platform_driver_unregister(&PLATFORM_DRIVER);
1257 : #endif
1258 : #ifdef PCI_DRIVER
1259 4 : pci_unregister_driver(&PCI_DRIVER);
1260 : #endif
1261 : #ifdef PS3_SYSTEM_BUS_DRIVER
1262 : ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1263 : #endif
1264 : #ifdef DEBUG
1265 : debugfs_remove(ehci_debug_root);
1266 : #endif
1267 4 : clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1268 2 : }
1269 : module_exit(ehci_hcd_cleanup);
1270 1 :
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