LCOV - code coverage report
Current view: top level - include/linux/usb - ehci_def.h (source / functions) Hit Total Coverage
Test: coverage.info Lines: 5 5 100.0 %
Date: 2017-01-25 Functions: 2 2 100.0 %

          Line data    Source code
       1             : /*
       2             :  * Copyright (c) 2001-2002 by David Brownell
       3             :  *
       4             :  * This program is free software; you can redistribute it and/or modify it
       5             :  * under the terms of the GNU General Public License as published by the
       6             :  * Free Software Foundation; either version 2 of the License, or (at your
       7             :  * option) any later version.
       8             :  *
       9             :  * This program is distributed in the hope that it will be useful, but
      10             :  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
      11             :  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
      12             :  * for more details.
      13             :  *
      14             :  * You should have received a copy of the GNU General Public License
      15             :  * along with this program; if not, write to the Free Software Foundation,
      16             :  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
      17             :  */
      18             : 
      19             : #ifndef __LINUX_USB_EHCI_DEF_H
      20             : #define __LINUX_USB_EHCI_DEF_H
      21             : 
      22             : /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
      23             : 
      24             : /* Section 2.2 Host Controller Capability Registers */
      25             : struct ehci_caps {
      26             :         /* these fields are specified as 8 and 16 bit registers,
      27             :          * but some hosts can't perform 8 or 16 bit PCI accesses.
      28             :          */
      29             :         u32             hc_capbase;
      30             : #define HC_LENGTH(p)            (((p)>>00)&0x00ff)    /* bits 7:0 */
      31             : #define HC_VERSION(p)           (((p)>>16)&0xffff)    /* bits 31:16 */
      32             :         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
      33             : #define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf)       /* bits 23:20, debug port? */
      34             : #define HCS_INDICATOR(p)        ((p)&(1 << 16))       /* true: has port indicators */
      35             : #define HCS_N_CC(p)             (((p)>>12)&0xf)       /* bits 15:12, #companion HCs */
      36             : #define HCS_N_PCC(p)            (((p)>>8)&0xf)        /* bits 11:8, ports per CC */
      37             : #define HCS_PORTROUTED(p)       ((p)&(1 << 7))        /* true: port routing */
      38             : #define HCS_PPC(p)              ((p)&(1 << 4))        /* true: port power control */
      39             : #define HCS_N_PORTS(p)          (((p)>>0)&0xf)        /* bits 3:0, ports on HC */
      40             : 
      41             :         u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
      42             : #define HCC_EXT_CAPS(p)         (((p)>>8)&0xff)       /* for pci extended caps */
      43             : #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
      44             : #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
      45             : #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
      46             : #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
      47             : #define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
      48             :         u8              portroute [8];   /* nibbles for routing - offset 0xC */
      49             : } __attribute__ ((packed));
      50           1 : 
      51             : 
      52             : /* Section 2.3 Host Controller Operational Registers */
      53             : struct ehci_regs {
      54             : 
      55             :         /* USBCMD: offset 0x00 */
      56             :         u32             command;
      57             : /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
      58             : #define CMD_PARK        (1<<11)           /* enable "park" on async qh */
      59             : #define CMD_PARK_CNT(c) (((c)>>8)&3)  /* how many transfers to park for */
      60             : #define CMD_LRESET      (1<<7)            /* partial reset (no ports, etc) */
      61             : #define CMD_IAAD        (1<<6)            /* "doorbell" interrupt async advance */
      62             : #define CMD_ASE         (1<<5)            /* async schedule enable */
      63             : #define CMD_PSE         (1<<4)            /* periodic schedule enable */
      64             : /* 3:2 is periodic frame list size */
      65             : #define CMD_RESET       (1<<1)            /* reset HC not bus */
      66             : #define CMD_RUN         (1<<0)            /* start/stop HC */
      67             : 
      68             :         /* USBSTS: offset 0x04 */
      69             :         u32             status;
      70             : #define STS_ASS         (1<<15)           /* Async Schedule Status */
      71             : #define STS_PSS         (1<<14)           /* Periodic Schedule Status */
      72             : #define STS_RECL        (1<<13)           /* Reclamation */
      73             : #define STS_HALT        (1<<12)           /* Not running (any reason) */
      74             : /* some bits reserved */
      75             :         /* these STS_* flags are also intr_enable bits (USBINTR) */
      76             : #define STS_IAA         (1<<5)            /* Interrupted on async advance */
      77             : #define STS_FATAL       (1<<4)            /* such as some PCI access errors */
      78             : #define STS_FLR         (1<<3)            /* frame list rolled over */
      79             : #define STS_PCD         (1<<2)            /* port change detect */
      80             : #define STS_ERR         (1<<1)            /* "error" completion (overflow, ...) */
      81             : #define STS_INT         (1<<0)            /* "normal" completion (short, ...) */
      82             : 
      83             :         /* USBINTR: offset 0x08 */
      84             :         u32             intr_enable;
      85             : 
      86             :         /* FRINDEX: offset 0x0C */
      87             :         u32             frame_index;    /* current microframe number */
      88             :         /* CTRLDSSEGMENT: offset 0x10 */
      89             :         u32             segment;        /* address bits 63:32 if needed */
      90             :         /* PERIODICLISTBASE: offset 0x14 */
      91             :         u32             frame_list;     /* points to periodic list */
      92             :         /* ASYNCLISTADDR: offset 0x18 */
      93             :         u32             async_next;     /* address of next async queue head */
      94             : 
      95             :         u32             reserved [9];
      96             : 
      97             :         /* CONFIGFLAG: offset 0x40 */
      98             :         u32             configured_flag;
      99             : #define FLAG_CF         (1<<0)            /* true: we'll support "high speed" */
     100             : 
     101             :         /* PORTSC: offset 0x44 */
     102             :         u32             port_status [0];        /* up to N_PORTS */
     103             : /* 31:23 reserved */
     104           1 : #define PORT_WKOC_E     (1<<22)           /* wake on overcurrent (enable) */
     105             : #define PORT_WKDISC_E   (1<<21)           /* wake on disconnect (enable) */
     106             : #define PORT_WKCONN_E   (1<<20)           /* wake on connect (enable) */
     107             : /* 19:16 for port testing */
     108             : #define PORT_TEST_PKT   (0x4<<16) /* Port Test Control - packet test */
     109             : #define PORT_LED_OFF    (0<<14)
     110             : #define PORT_LED_AMBER  (1<<14)
     111             : #define PORT_LED_GREEN  (2<<14)
     112             : #define PORT_LED_MASK   (3<<14)
     113             : #define PORT_OWNER      (1<<13)           /* true: companion hc owns this port */
     114             : #define PORT_POWER      (1<<12)           /* true: has power (see PPC) */
     115             : #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10))        /* USB 1.1 device */
     116             : /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
     117             : /* 9 reserved */
     118             : #define PORT_RESET      (1<<8)            /* reset port */
     119             : #define PORT_SUSPEND    (1<<7)            /* suspend port */
     120             : #define PORT_RESUME     (1<<6)            /* resume it */
     121             : #define PORT_OCC        (1<<5)            /* over current change */
     122             : #define PORT_OC         (1<<4)            /* over current active */
     123             : #define PORT_PEC        (1<<3)            /* port enable change */
     124             : #define PORT_PE         (1<<2)            /* port enable */
     125             : #define PORT_CSC        (1<<1)            /* connect status change */
     126             : #define PORT_CONNECT    (1<<0)            /* device connected */
     127             : #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
     128             : } __attribute__ ((packed));
     129             : 
     130             : #define USBMODE         0x68            /* USB Device mode */
     131             : #define USBMODE_SDIS    (1<<3)            /* Stream disable */
     132             : #define USBMODE_BE      (1<<2)            /* BE/LE endianness select */
     133             : #define USBMODE_CM_HC   (3<<0)            /* host controller mode */
     134             : #define USBMODE_CM_IDLE (0<<0)            /* idle state */
     135             : 
     136             : /* Moorestown has some non-standard registers, partially due to the fact that
     137             :  * its EHCI controller has both TT and LPM support. HOSTPCx are extentions to
     138             :  * PORTSCx
     139             :  */
     140             : #define HOSTPC0         0x84            /* HOSTPC extension */
     141             : #define HOSTPC_PHCD     (1<<22)           /* Phy clock disable */
     142             : #define HOSTPC_PSPD     (3<<25)           /* Port speed detection */
     143             : #define USBMODE_EX      0xc8            /* USB Device mode extension */
     144             : #define USBMODE_EX_VBPS (1<<5)            /* VBus Power Select On */
     145             : #define USBMODE_EX_HC   (3<<0)            /* host controller mode */
     146             : #define TXFILLTUNING    0x24            /* TX FIFO Tuning register */
     147             : #define TXFIFO_DEFAULT  (8<<16)           /* FIFO burst threshold 8 */
     148             : 
     149             : /* Appendix C, Debug port ... intended for use with special "debug devices"
     150             :  * that can help if there's no serial console.  (nonstandard enumeration.)
     151             :  */
     152             : struct ehci_dbg_port {
     153             :         u32     control;
     154             : #define DBGP_OWNER      (1<<30)
     155             : #define DBGP_ENABLED    (1<<28)
     156             : #define DBGP_DONE       (1<<16)
     157             : #define DBGP_INUSE      (1<<10)
     158             : #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
     159             : #       define DBGP_ERR_BAD     1
     160             : #       define DBGP_ERR_SIGNAL  2
     161             : #define DBGP_ERROR      (1<<6)
     162             : #define DBGP_GO         (1<<5)
     163             : #define DBGP_OUT        (1<<4)
     164             : #define DBGP_LEN(x)     (((x)>>0)&0x0f)
     165             :         u32     pids;
     166             : #define DBGP_PID_GET(x)         (((x)>>16)&0xff)
     167             : #define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
     168             :         u32     data03;
     169             :         u32     data47;
     170             :         u32     address;
     171             : #define DBGP_EPADDR(dev, ep)    (((dev)<<8)|(ep))
     172             : } __attribute__ ((packed));
     173             : 
     174             : #ifdef CONFIG_EARLY_PRINTK_DBGP
     175             : #include <linux/init.h>
     176             : extern int __init early_dbgp_init(char *s);
     177             : extern struct console early_dbgp_console;
     178             : #endif /* CONFIG_EARLY_PRINTK_DBGP */
     179             : 
     180             : #ifdef CONFIG_EARLY_PRINTK_DBGP
     181             : /* Call backs from ehci host driver to ehci debug driver */
     182             : extern int dbgp_external_startup(void);
     183             : extern int dbgp_reset_prep(void);
     184             : #else
     185             : static inline int dbgp_reset_prep(void)
     186             : {
     187          12 :         return 1;
     188             : }
     189             : static inline int dbgp_external_startup(void)
     190             : {
     191          24 :         return -1;
     192             : }
     193           1 : #endif
     194             : 
     195             : #endif /* __LINUX_USB_EHCI_DEF_H */

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