Line data Source code
1 : /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2 : /*
3 : Written 1996-1999 by Donald Becker.
4 :
5 : This software may be used and distributed according to the terms
6 : of the GNU General Public License, incorporated herein by reference.
7 :
8 : This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 : Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 : and the EtherLink XL 3c900 and 3c905 cards.
11 :
12 : Problem reports and questions should be directed to
13 : vortex@scyld.com
14 :
15 : The author may be reached as becker@scyld.com, or C/O
16 : Scyld Computing Corporation
17 : 410 Severn Ave., Suite 210
18 : Annapolis MD 21403
19 :
20 : */
21 :
22 : /*
23 : * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 : * as well as other drivers
25 : *
26 : * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 : * due to dead code elimination. There will be some performance benefits from this due to
28 : * elimination of all the tests and reduced cache footprint.
29 : */
30 :
31 :
32 : #define DRV_NAME "3c59x"
33 :
34 :
35 :
36 : /* A few values that may be tweaked. */
37 : /* Keep the ring sizes a power of two for efficiency. */
38 : #define TX_RING_SIZE 16
39 : #define RX_RING_SIZE 32
40 : #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41 :
42 : /* "Knobs" that adjust features and parameters. */
43 : /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 : Setting to > 1512 effectively disables this feature. */
45 : #ifndef __arm__
46 1 : static int rx_copybreak = 200;
47 : #else
48 : /* ARM systems perform better by disregarding the bus-master
49 : transfer capability of these cards. -- rmk */
50 : static int rx_copybreak = 1513;
51 : #endif
52 : /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53 1 : static const int mtu = 1500;
54 : /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 1 : static int max_interrupt_work = 32;
56 : /* Tx timeout interval (millisecs) */
57 1 : static int watchdog = 5000;
58 :
59 : /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 : * of possible Tx stalls if the system is blocking interrupts
61 : * somewhere else. Undefine this to disable.
62 : */
63 : #define tx_interrupt_mitigation 1
64 :
65 : /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66 : #define vortex_debug debug
67 : #ifdef VORTEX_DEBUG
68 : static int vortex_debug = VORTEX_DEBUG;
69 : #else
70 1 : static int vortex_debug = 1;
71 1 : #endif
72 :
73 : #include <linux/module.h>
74 : #include <linux/kernel.h>
75 : #include <linux/string.h>
76 : #include <linux/timer.h>
77 : #include <linux/errno.h>
78 : #include <linux/in.h>
79 : #include <linux/ioport.h>
80 : #include <linux/slab.h>
81 : #include <linux/interrupt.h>
82 : #include <linux/pci.h>
83 : #include <linux/mii.h>
84 : #include <linux/init.h>
85 : #include <linux/netdevice.h>
86 : #include <linux/etherdevice.h>
87 : #include <linux/skbuff.h>
88 : #include <linux/ethtool.h>
89 : #include <linux/highmem.h>
90 : #include <linux/eisa.h>
91 : #include <linux/bitops.h>
92 : #include <linux/jiffies.h>
93 : #include <asm/irq.h> /* For nr_irqs only. */
94 : #include <asm/io.h>
95 : #include <asm/uaccess.h>
96 :
97 : /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 : This is only in the support-all-kernels source code. */
99 :
100 : #define RUN_AT(x) (jiffies + (x))
101 :
102 : #include <linux/delay.h>
103 :
104 :
105 1 : static const char version[] __devinitconst =
106 : DRV_NAME ": Donald Becker and others.\n";
107 :
108 : MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109 : MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110 : MODULE_LICENSE("GPL");
111 :
112 :
113 : /* Operational parameter that usually are not changed. */
114 :
115 : /* The Vortex size is twice that of the original EtherLinkIII series: the
116 : runtime register window, window 1, is now always mapped in.
117 : The Boomerang size is twice as large as the Vortex -- it has additional
118 : bus master control registers. */
119 : #define VORTEX_TOTAL_SIZE 0x20
120 : #define BOOMERANG_TOTAL_SIZE 0x40
121 :
122 : /* Set iff a MII transceiver on any interface requires mdio preamble.
123 : This only set with the original DP83840 on older 3c905 boards, so the extra
124 : code size of a per-interface flag is not worthwhile. */
125 1 : static char mii_preamble_required;
126 :
127 : #define PFX DRV_NAME ": "
128 :
129 :
130 :
131 : /*
132 : Theory of Operation
133 :
134 : I. Board Compatibility
135 :
136 : This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137 : XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138 : versions of the FastEtherLink cards. The supported product IDs are
139 : 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140 :
141 : The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142 : with the kernel source or available from
143 : cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144 :
145 : II. Board-specific settings
146 :
147 : PCI bus devices are configured by the system at boot time, so no jumpers
148 : need to be set on the board. The system BIOS should be set to assign the
149 : PCI INTA signal to an otherwise unused system IRQ line.
150 :
151 : The EEPROM settings for media type and forced-full-duplex are observed.
152 : The EEPROM media type should be left at the default "autoselect" unless using
153 : 10base2 or AUI connections which cannot be reliably detected.
154 :
155 : III. Driver operation
156 :
157 : The 3c59x series use an interface that's very similar to the previous 3c5x9
158 : series. The primary interface is two programmed-I/O FIFOs, with an
159 : alternate single-contiguous-region bus-master transfer (see next).
160 :
161 : The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162 : lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163 : DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164 : programmed-I/O interface that has been removed in 'B' and subsequent board
165 : revisions.
166 :
167 : One extension that is advertised in a very large font is that the adapters
168 : are capable of being bus masters. On the Vortex chip this capability was
169 : only for a single contiguous region making it far less useful than the full
170 : bus master capability. There is a significant performance impact of taking
171 : an extra interrupt or polling for the completion of each transfer, as well
172 : as difficulty sharing the single transfer engine between the transmit and
173 : receive threads. Using DMA transfers is a win only with large blocks or
174 : with the flawed versions of the Intel Orion motherboard PCI controller.
175 :
176 : The Boomerang chip's full-bus-master interface is useful, and has the
177 : currently-unused advantages over other similar chips that queued transmit
178 : packets may be reordered and receive buffer groups are associated with a
179 : single frame.
180 :
181 : With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182 : Rather than a fixed intermediate receive buffer, this scheme allocates
183 : full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184 : the copying breakpoint: it is chosen to trade-off the memory wasted by
185 : passing the full-sized skbuff to the queue layer for all frames vs. the
186 : copying cost of copying a frame to a correctly-sized skbuff.
187 :
188 : IIIC. Synchronization
189 : The driver runs as two independent, single-threaded flows of control. One
190 : is the send-packet routine, which enforces single-threaded use by the
191 : dev->tbusy flag. The other thread is the interrupt handler, which is single
192 1 : threaded by the hardware and other software.
193 :
194 : IV. Notes
195 :
196 : Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
197 : 3c590, 3c595, and 3c900 boards.
198 : The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199 : the EISA version is called "Demon". According to Terry these names come
200 : from rides at the local amusement park.
201 :
202 : The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203 : This driver only supports ethernet packets because of the skbuff allocation
204 : limit of 4K.
205 : */
206 :
207 : /* This table drives the PCI probe routines. It's mostly boilerplate in all
208 : of the drivers, and will likely be provided by some future kernel.
209 : */
210 : enum pci_flags_bit {
211 : PCI_USES_MASTER=4,
212 : };
213 :
214 : enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 : EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 : HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 : INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 : EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 : EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220 :
221 : enum vortex_chips {
222 : CH_3C590 = 0,
223 : CH_3C592,
224 : CH_3C597,
225 : CH_3C595_1,
226 : CH_3C595_2,
227 :
228 : CH_3C595_3,
229 : CH_3C900_1,
230 : CH_3C900_2,
231 : CH_3C900_3,
232 : CH_3C900_4,
233 :
234 : CH_3C900_5,
235 : CH_3C900B_FL,
236 : CH_3C905_1,
237 : CH_3C905_2,
238 : CH_3C905B_TX,
239 : CH_3C905B_1,
240 :
241 : CH_3C905B_2,
242 : CH_3C905B_FX,
243 : CH_3C905C,
244 : CH_3C9202,
245 : CH_3C980,
246 : CH_3C9805,
247 :
248 : CH_3CSOHO100_TX,
249 : CH_3C555,
250 : CH_3C556,
251 : CH_3C556B,
252 : CH_3C575,
253 :
254 : CH_3C575_1,
255 : CH_3CCFE575,
256 : CH_3CCFE575CT,
257 : CH_3CCFE656,
258 : CH_3CCFEM656,
259 :
260 : CH_3CCFEM656_1,
261 : CH_3C450,
262 : CH_3C920,
263 : CH_3C982A,
264 : CH_3C982B,
265 :
266 : CH_905BT4,
267 : CH_920B_EMB_WNM,
268 : };
269 :
270 :
271 : /* note: this array directly indexed by above enums, and MUST
272 : * be kept in sync with both the enums above, and the PCI device
273 : * table below
274 : */
275 : static struct vortex_chip_info {
276 : const char *name;
277 : int flags;
278 : int drv_flags;
279 : int io_size;
280 1 : } vortex_info_tbl[] __devinitdata = {
281 : {"3c590 Vortex 10Mbps",
282 : PCI_USES_MASTER, IS_VORTEX, 32, },
283 : {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
284 : PCI_USES_MASTER, IS_VORTEX, 32, },
285 : {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
286 : PCI_USES_MASTER, IS_VORTEX, 32, },
287 : {"3c595 Vortex 100baseTx",
288 : PCI_USES_MASTER, IS_VORTEX, 32, },
289 : {"3c595 Vortex 100baseT4",
290 : PCI_USES_MASTER, IS_VORTEX, 32, },
291 :
292 : {"3c595 Vortex 100base-MII",
293 : PCI_USES_MASTER, IS_VORTEX, 32, },
294 : {"3c900 Boomerang 10baseT",
295 : PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
296 : {"3c900 Boomerang 10Mbps Combo",
297 : PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
298 : {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
299 : PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
300 : {"3c900 Cyclone 10Mbps Combo",
301 : PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
302 :
303 : {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
304 : PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
305 : {"3c900B-FL Cyclone 10base-FL",
306 : PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
307 : {"3c905 Boomerang 100baseTx",
308 : PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
309 : {"3c905 Boomerang 100baseT4",
310 : PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
311 : {"3C905B-TX Fast Etherlink XL PCI",
312 : PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 : {"3c905B Cyclone 100baseTx",
314 : PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
315 :
316 : {"3c905B Cyclone 10/100/BNC",
317 : PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
318 : {"3c905B-FX Cyclone 100baseFx",
319 : PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
320 : {"3c905C Tornado",
321 : PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
322 : {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
323 : PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
324 : {"3c980 Cyclone",
325 : PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
326 :
327 : {"3c980C Python-T",
328 : PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
329 : {"3cSOHO100-TX Hurricane",
330 : PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
331 : {"3c555 Laptop Hurricane",
332 : PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
333 : {"3c556 Laptop Tornado",
334 : PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
335 : HAS_HWCKSM, 128, },
336 : {"3c556B Laptop Hurricane",
337 : PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
338 : WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339 :
340 : {"3c575 [Megahertz] 10/100 LAN CardBus",
341 : PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
342 : {"3c575 Boomerang CardBus",
343 : PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
344 : {"3CCFE575BT Cyclone CardBus",
345 : PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
346 : INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 : {"3CCFE575CT Tornado CardBus",
348 : PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 : MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 : {"3CCFE656 Cyclone CardBus",
351 : PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
352 : INVERT_LED_PWR|HAS_HWCKSM, 128, },
353 :
354 : {"3CCFEM656B Cyclone+Winmodem CardBus",
355 : PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 : INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 : {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
358 : PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
359 : MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 : {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
361 : PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
362 : {"3c920 Tornado",
363 : PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
364 : {"3c982 Hydra Dual Port A",
365 : PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
366 :
367 : {"3c982 Hydra Dual Port B",
368 : PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
369 : {"3c905B-T4",
370 : PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
371 : {"3c920B-EMB-WNM Tornado",
372 : PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
373 :
374 : {NULL,}, /* NULL terminated list. */
375 : };
376 :
377 :
378 1 : static struct pci_device_id vortex_pci_tbl[] = {
379 : { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 : { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 : { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 : { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 : { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384 :
385 : { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 : { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 : { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 : { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 : { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390 :
391 : { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 : { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 : { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 : { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 : { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
396 : { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397 :
398 : { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 : { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 : { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 : { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 : { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 : { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404 :
405 : { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 : { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 : { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 : { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 : { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410 :
411 : { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 : { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 : { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 : { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 : { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416 :
417 : { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 : { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 : { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 : { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 : { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422 :
423 : { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 : { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425 :
426 : {0,} /* 0 terminated list. */
427 : };
428 : MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429 :
430 :
431 : /* Operational definitions.
432 : These are not used by other compilation units and thus are not
433 : exported in a ".h" file.
434 :
435 : First the windows. There are eight register windows, with the command
436 : and status registers available in each.
437 : */
438 : #define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
439 : #define EL3_CMD 0x0e
440 : #define EL3_STATUS 0x0e
441 :
442 : /* The top five bits written to EL3_CMD are a command, the lower
443 : 11 bits are the parameter, if applicable.
444 : Note that 11 parameters bits was fine for ethernet, but the new chip
445 : can handle FDDI length frames (~4500 octets) and now parameters count
446 : 32-bit 'Dwords' rather than octets. */
447 :
448 : enum vortex_cmd {
449 : TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
450 : RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
451 : UpStall = 6<<11, UpUnstall = (6<<11)+1,
452 : DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
453 : RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
454 : FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
455 : SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
456 : SetTxThreshold = 18<<11, SetTxStart = 19<<11,
457 : StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
458 : StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
459 :
460 : /* The SetRxFilter command accepts the following classes: */
461 : enum RxFilter {
462 : RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
463 :
464 : /* Bits in the general status register. */
465 : enum vortex_status {
466 : IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
467 : TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
468 : IntReq = 0x0040, StatsFull = 0x0080,
469 : DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
470 : DMAInProgress = 1<<11, /* DMA controller is still busy.*/
471 : CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
472 : };
473 :
474 : /* Register window 1 offsets, the window used in normal operation.
475 : On the Vortex this window is always mapped at offsets 0x10-0x1f. */
476 : enum Window1 {
477 : TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
478 : RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
479 : TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
480 : };
481 : enum Window0 {
482 : Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
483 : Wn0EepromData = 12, /* Window 0: EEPROM results register. */
484 : IntrStatus=0x0E, /* Valid in all windows. */
485 : };
486 : enum Win0_EEPROM_bits {
487 : EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
488 : EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
489 : EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
490 : };
491 : /* EEPROM locations. */
492 : enum eeprom_offset {
493 : PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
494 : EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
495 : NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
496 : DriverTune=13, Checksum=15};
497 :
498 : enum Window2 { /* Window 2. */
499 : Wn2_ResetOptions=12,
500 : };
501 : enum Window3 { /* Window 3: MAC/config bits. */
502 : Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
503 : };
504 :
505 : #define BFEXT(value, offset, bitcount) \
506 : ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
507 :
508 : #define BFINS(lhs, rhs, offset, bitcount) \
509 : (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
510 : (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
511 :
512 : #define RAM_SIZE(v) BFEXT(v, 0, 3)
513 : #define RAM_WIDTH(v) BFEXT(v, 3, 1)
514 1 : #define RAM_SPEED(v) BFEXT(v, 4, 2)
515 : #define ROM_SIZE(v) BFEXT(v, 6, 2)
516 : #define RAM_SPLIT(v) BFEXT(v, 16, 2)
517 : #define XCVR(v) BFEXT(v, 20, 4)
518 : #define AUTOSELECT(v) BFEXT(v, 24, 1)
519 :
520 : enum Window4 { /* Window 4: Xcvr/media bits. */
521 : Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
522 : };
523 : enum Win4_Media_bits {
524 : Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
525 : Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
526 : Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
527 : Media_LnkBeat = 0x0800,
528 : };
529 : enum Window7 { /* Window 7: Bus Master control. */
530 : Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
531 : Wn7_MasterStatus = 12,
532 : };
533 : /* Boomerang bus master control registers. */
534 : enum MasterCtrl {
535 : PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
536 : TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
537 : };
538 :
539 : /* The Rx and Tx descriptor lists.
540 : Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
541 : alignment contraint on tx_ring[] and rx_ring[]. */
542 : #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
543 : #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
544 : struct boom_rx_desc {
545 : __le32 next; /* Last entry points to 0. */
546 : __le32 status;
547 : __le32 addr; /* Up to 63 addr/len pairs possible. */
548 : __le32 length; /* Set LAST_FRAG to indicate last pair. */
549 : };
550 : /* Values for the Rx status entry. */
551 : enum rx_desc_status {
552 : RxDComplete=0x00008000, RxDError=0x4000,
553 : /* See boomerang_rx() for actual error bits */
554 : IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
555 : IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
556 : };
557 :
558 : #ifdef MAX_SKB_FRAGS
559 : #define DO_ZEROCOPY 1
560 : #else
561 2 : #define DO_ZEROCOPY 0
562 : #endif
563 :
564 : struct boom_tx_desc {
565 : __le32 next; /* Last entry points to 0. */
566 : __le32 status; /* bits 0:12 length, others see below. */
567 : #if DO_ZEROCOPY
568 : struct {
569 : __le32 addr;
570 : __le32 length;
571 : } frag[1+MAX_SKB_FRAGS];
572 : #else
573 : __le32 addr;
574 : __le32 length;
575 : #endif
576 : };
577 :
578 : /* Values for the Tx status entry. */
579 : enum tx_desc_status {
580 : CRCDisable=0x2000, TxDComplete=0x8000,
581 : AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
582 : TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
583 : };
584 :
585 : /* Chip features we care about in vp->capabilities, read from the EEPROM. */
586 : enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
587 1 :
588 : struct vortex_extra_stats {
589 : unsigned long tx_deferred;
590 : unsigned long tx_max_collisions;
591 : unsigned long tx_multiple_collisions;
592 : unsigned long tx_single_collisions;
593 : unsigned long rx_bad_ssd;
594 : };
595 1 :
596 : struct vortex_private {
597 : /* The Rx and Tx rings should be quad-word-aligned. */
598 : struct boom_rx_desc* rx_ring;
599 : struct boom_tx_desc* tx_ring;
600 : dma_addr_t rx_ring_dma;
601 : dma_addr_t tx_ring_dma;
602 : /* The addresses of transmit- and receive-in-place skbuffs. */
603 : struct sk_buff* rx_skbuff[RX_RING_SIZE];
604 : struct sk_buff* tx_skbuff[TX_RING_SIZE];
605 : unsigned int cur_rx, cur_tx; /* The next free ring entry */
606 : unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
607 : struct vortex_extra_stats xstats; /* NIC-specific extra stats */
608 : struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
609 : dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
610 :
611 : /* PCI configuration space information. */
612 : struct device *gendev;
613 : void __iomem *ioaddr; /* IO address space */
614 : void __iomem *cb_fn_base; /* CardBus function status addr space. */
615 :
616 : /* Some values here only for performance evaluation and path-coverage */
617 : int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
618 : int card_idx;
619 :
620 : /* The remainder are related to chip state, mostly media selection. */
621 : struct timer_list timer; /* Media selection timer. */
622 : struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
623 : int options; /* User-settable misc. driver options. */
624 : unsigned int media_override:4, /* Passed-in media type. */
625 : default_media:4, /* Read from the EEPROM/Wn3_Config. */
626 : full_duplex:1, autoselect:1,
627 : bus_master:1, /* Vortex can only do a fragment bus-m. */
628 : full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
629 : flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
630 : partner_flow_ctrl:1, /* Partner supports flow control */
631 : has_nway:1,
632 : enable_wol:1, /* Wake-on-LAN is enabled */
633 : pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
634 : open:1,
635 : medialock:1,
636 : must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
637 : large_frames:1; /* accept large frames */
638 : int drv_flags;
639 : u16 status_enable;
640 : u16 intr_enable;
641 : u16 available_media; /* From Wn3_Options. */
642 : u16 capabilities, info1, info2; /* Various, from EEPROM. */
643 : u16 advertising; /* NWay media advertisement */
644 : unsigned char phys[2]; /* MII device addresses. */
645 : u16 deferred; /* Resend these interrupts when we
646 : * bale from the ISR */
647 : u16 io_size; /* Size of PCI region (for release_region) */
648 : spinlock_t lock; /* Serialise access to device & its vortex_private */
649 : struct mii_if_info mii; /* MII lib hooks/info */
650 : };
651 :
652 : #ifdef CONFIG_PCI
653 : #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
654 : #else
655 : #define DEVICE_PCI(dev) NULL
656 : #endif
657 :
658 : #define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
659 :
660 : #ifdef CONFIG_EISA
661 : #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
662 : #else
663 : #define DEVICE_EISA(dev) NULL
664 1 : #endif
665 :
666 : #define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
667 :
668 : /* The action to take with a media selection timer tick.
669 : Note that we deviate from the 3Com order by checking 10base2 before AUI.
670 : */
671 : enum xcvr_types {
672 : XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
673 : XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
674 : };
675 :
676 : static const struct media_table {
677 : char *name;
678 : unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
679 : mask:8, /* The transceiver-present bit in Wn3_Config.*/
680 : next:8; /* The media type to try next. */
681 : int wait; /* Time before we check media status. */
682 1 : } media_tbl[] = {
683 : { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
684 : { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
685 : { "undefined", 0, 0x80, XCVR_10baseT, 10000},
686 : { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
687 : { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
688 : { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
689 : { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
690 : { "undefined", 0, 0x01, XCVR_10baseT, 10000},
691 : { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
692 : { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
693 : { "Default", 0, 0xFF, XCVR_10baseT, 10000},
694 : };
695 :
696 : static struct {
697 : const char str[ETH_GSTRING_LEN];
698 2 : } ethtool_stats_keys[] = {
699 : { "tx_deferred" },
700 : { "tx_max_collisions" },
701 : { "tx_multiple_collisions" },
702 : { "tx_single_collisions" },
703 : { "rx_bad_ssd" },
704 : };
705 :
706 : /* number of ETHTOOL_GSTATS u64's */
707 : #define VORTEX_NUM_STATS 5
708 :
709 : static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
710 : int chip_idx, int card_idx);
711 : static int vortex_up(struct net_device *dev);
712 : static void vortex_down(struct net_device *dev, int final);
713 : static int vortex_open(struct net_device *dev);
714 : static void mdio_sync(void __iomem *ioaddr, int bits);
715 : static int mdio_read(struct net_device *dev, int phy_id, int location);
716 : static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
717 : static void vortex_timer(unsigned long arg);
718 : static void rx_oom_timer(unsigned long arg);
719 : static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
720 : struct net_device *dev);
721 : static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
722 : struct net_device *dev);
723 : static int vortex_rx(struct net_device *dev);
724 : static int boomerang_rx(struct net_device *dev);
725 : static irqreturn_t vortex_interrupt(int irq, void *dev_id);
726 : static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
727 : static int vortex_close(struct net_device *dev);
728 : static void dump_tx_ring(struct net_device *dev);
729 : static void update_stats(void __iomem *ioaddr, struct net_device *dev);
730 : static struct net_device_stats *vortex_get_stats(struct net_device *dev);
731 : static void set_rx_mode(struct net_device *dev);
732 : #ifdef CONFIG_PCI
733 : static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
734 : #endif
735 : static void vortex_tx_timeout(struct net_device *dev);
736 : static void acpi_set_WOL(struct net_device *dev);
737 1 : static const struct ethtool_ops vortex_ethtool_ops;
738 : static void set_8021q_mode(struct net_device *dev, int enable);
739 :
740 : /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
741 : /* Option count limit only -- unlimited interfaces are supported. */
742 : #define MAX_UNITS 8
743 1 : static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
744 1 : static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
745 1 : static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
746 1 : static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
747 1 : static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
748 1 : static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
749 1 : static int global_options = -1;
750 1 : static int global_full_duplex = -1;
751 1 : static int global_enable_wol = -1;
752 1 : static int global_use_mmio = -1;
753 :
754 : /* Variables to work-around the Compaq PCI BIOS32 problem. */
755 3 : static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
756 1 : static struct net_device *compaq_net_device;
757 :
758 1 : static int vortex_cards_found;
759 :
760 : module_param(debug, int, 0);
761 : module_param(global_options, int, 0);
762 : module_param_array(options, int, NULL, 0);
763 : module_param(global_full_duplex, int, 0);
764 : module_param_array(full_duplex, int, NULL, 0);
765 : module_param_array(hw_checksums, int, NULL, 0);
766 : module_param_array(flow_ctrl, int, NULL, 0);
767 : module_param(global_enable_wol, int, 0);
768 : module_param_array(enable_wol, int, NULL, 0);
769 : module_param(rx_copybreak, int, 0);
770 : module_param(max_interrupt_work, int, 0);
771 : module_param(compaq_ioaddr, int, 0);
772 : module_param(compaq_irq, int, 0);
773 : module_param(compaq_device_id, int, 0);
774 : module_param(watchdog, int, 0);
775 : module_param(global_use_mmio, int, 0);
776 : module_param_array(use_mmio, int, NULL, 0);
777 : MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
778 : MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
779 : MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
780 : MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
781 : MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
782 : MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
783 : MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
784 : MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
785 : MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
786 : MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
787 : MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
788 : MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
789 : MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
790 : MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
791 : MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
792 : MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
793 : MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
794 :
795 : #ifdef CONFIG_NET_POLL_CONTROLLER
796 : static void poll_vortex(struct net_device *dev)
797 : {
798 : struct vortex_private *vp = netdev_priv(dev);
799 : unsigned long flags;
800 : local_irq_save(flags);
801 : (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
802 : local_irq_restore(flags);
803 : }
804 : #endif
805 :
806 : #ifdef CONFIG_PM
807 :
808 : static int vortex_suspend(struct device *dev)
809 : {
810 : struct pci_dev *pdev = to_pci_dev(dev);
811 : struct net_device *ndev = pci_get_drvdata(pdev);
812 :
813 : if (!ndev || !netif_running(ndev))
814 : return 0;
815 :
816 : netif_device_detach(ndev);
817 : vortex_down(ndev, 1);
818 :
819 : return 0;
820 : }
821 :
822 : static int vortex_resume(struct device *dev)
823 : {
824 : struct pci_dev *pdev = to_pci_dev(dev);
825 : struct net_device *ndev = pci_get_drvdata(pdev);
826 : int err;
827 :
828 : if (!ndev || !netif_running(ndev))
829 : return 0;
830 :
831 : err = vortex_up(ndev);
832 : if (err)
833 : return err;
834 :
835 : netif_device_attach(ndev);
836 :
837 : return 0;
838 : }
839 :
840 : static const struct dev_pm_ops vortex_pm_ops = {
841 : .suspend = vortex_suspend,
842 : .resume = vortex_resume,
843 : .freeze = vortex_suspend,
844 : .thaw = vortex_resume,
845 : .poweroff = vortex_suspend,
846 : .restore = vortex_resume,
847 : };
848 :
849 : #define VORTEX_PM_OPS (&vortex_pm_ops)
850 :
851 : #else /* !CONFIG_PM */
852 :
853 : #define VORTEX_PM_OPS NULL
854 :
855 : #endif /* !CONFIG_PM */
856 :
857 : #ifdef CONFIG_EISA
858 : static struct eisa_device_id vortex_eisa_ids[] = {
859 : { "TCM5920", CH_3C592 },
860 : { "TCM5970", CH_3C597 },
861 : { "" }
862 : };
863 : MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
864 :
865 : static int __init vortex_eisa_probe(struct device *device)
866 : {
867 : void __iomem *ioaddr;
868 : struct eisa_device *edev;
869 :
870 : edev = to_eisa_device(device);
871 :
872 : if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
873 : return -EBUSY;
874 :
875 : ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
876 :
877 : if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
878 : edev->id.driver_data, vortex_cards_found)) {
879 : release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
880 : return -ENODEV;
881 : }
882 :
883 : vortex_cards_found++;
884 :
885 : return 0;
886 : }
887 :
888 : static int __devexit vortex_eisa_remove(struct device *device)
889 : {
890 : struct eisa_device *edev;
891 : struct net_device *dev;
892 : struct vortex_private *vp;
893 : void __iomem *ioaddr;
894 :
895 : edev = to_eisa_device(device);
896 : dev = eisa_get_drvdata(edev);
897 :
898 : if (!dev) {
899 : pr_err("vortex_eisa_remove called for Compaq device!\n");
900 : BUG();
901 : }
902 :
903 : vp = netdev_priv(dev);
904 : ioaddr = vp->ioaddr;
905 :
906 : unregister_netdev(dev);
907 : iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
908 : release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
909 :
910 : free_netdev(dev);
911 : return 0;
912 : }
913 :
914 : static struct eisa_driver vortex_eisa_driver = {
915 : .id_table = vortex_eisa_ids,
916 : .driver = {
917 : .name = "3c59x",
918 : .probe = vortex_eisa_probe,
919 : .remove = __devexit_p(vortex_eisa_remove)
920 : }
921 : };
922 :
923 : #endif /* CONFIG_EISA */
924 :
925 : /* returns count found (>= 0), or negative on error */
926 : static int __init vortex_eisa_init(void)
927 : {
928 2 : int eisa_found = 0;
929 2 : int orig_cards_found = vortex_cards_found;
930 1 :
931 1 : #ifdef CONFIG_EISA
932 : int err;
933 :
934 : err = eisa_driver_register (&vortex_eisa_driver);
935 : if (!err) {
936 : /*
937 : * Because of the way EISA bus is probed, we cannot assume
938 : * any device have been found when we exit from
939 : * eisa_driver_register (the bus root driver may not be
940 : * initialized yet). So we blindly assume something was
941 : * found, and let the sysfs magic happend...
942 : */
943 : eisa_found = 1;
944 : }
945 : #endif
946 :
947 : /* Special code to work-around the Compaq PCI BIOS32 problem. */
948 2 : if (compaq_ioaddr) {
949 9 : vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
950 : compaq_irq, compaq_device_id, vortex_cards_found++);
951 : }
952 :
953 2 : return vortex_cards_found - orig_cards_found + eisa_found;
954 : }
955 :
956 : /* returns count (>= 0), or negative on error */
957 : static int __devinit vortex_init_one(struct pci_dev *pdev,
958 : const struct pci_device_id *ent)
959 1 : {
960 1 : int rc, unit, pci_bar;
961 1 : struct vortex_chip_info *vci;
962 1 : void __iomem *ioaddr;
963 1 :
964 : /* wake up and enable device */
965 1 : rc = pci_enable_device(pdev);
966 2 : if (rc < 0)
967 1 : goto out;
968 :
969 1 : unit = vortex_cards_found;
970 :
971 6 : if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
972 : /* Determine the default if the user didn't override us */
973 1 : vci = &vortex_info_tbl[ent->driver_data];
974 1 : pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
975 4 : } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
976 1 : pci_bar = use_mmio[unit] ? 1 : 0;
977 : else
978 1 : pci_bar = global_use_mmio ? 1 : 0;
979 :
980 1 : ioaddr = pci_iomap(pdev, pci_bar, 0);
981 2 : if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
982 1 : ioaddr = pci_iomap(pdev, 0, 0);
983 :
984 8 : rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
985 : ent->driver_data, unit);
986 2 : if (rc < 0) {
987 1 : pci_disable_device(pdev);
988 1 : goto out;
989 : }
990 :
991 1 : vortex_cards_found++;
992 1 :
993 : out:
994 2 : return rc;
995 : }
996 :
997 1 : static const struct net_device_ops boomrang_netdev_ops = {
998 : .ndo_open = vortex_open,
999 : .ndo_stop = vortex_close,
1000 : .ndo_start_xmit = boomerang_start_xmit,
1001 : .ndo_tx_timeout = vortex_tx_timeout,
1002 : .ndo_get_stats = vortex_get_stats,
1003 : #ifdef CONFIG_PCI
1004 : .ndo_do_ioctl = vortex_ioctl,
1005 : #endif
1006 : .ndo_set_multicast_list = set_rx_mode,
1007 : .ndo_change_mtu = eth_change_mtu,
1008 : .ndo_set_mac_address = eth_mac_addr,
1009 : .ndo_validate_addr = eth_validate_addr,
1010 : #ifdef CONFIG_NET_POLL_CONTROLLER
1011 : .ndo_poll_controller = poll_vortex,
1012 : #endif
1013 : };
1014 :
1015 1 : static const struct net_device_ops vortex_netdev_ops = {
1016 : .ndo_open = vortex_open,
1017 : .ndo_stop = vortex_close,
1018 : .ndo_start_xmit = vortex_start_xmit,
1019 : .ndo_tx_timeout = vortex_tx_timeout,
1020 : .ndo_get_stats = vortex_get_stats,
1021 : #ifdef CONFIG_PCI
1022 : .ndo_do_ioctl = vortex_ioctl,
1023 : #endif
1024 : .ndo_set_multicast_list = set_rx_mode,
1025 : .ndo_change_mtu = eth_change_mtu,
1026 : .ndo_set_mac_address = eth_mac_addr,
1027 : .ndo_validate_addr = eth_validate_addr,
1028 : #ifdef CONFIG_NET_POLL_CONTROLLER
1029 : .ndo_poll_controller = poll_vortex,
1030 : #endif
1031 : };
1032 :
1033 : /*
1034 : * Start up the PCI/EISA device which is described by *gendev.
1035 : * Return 0 on success.
1036 : *
1037 : * NOTE: pdev can be NULL, for the case of a Compaq device
1038 : */
1039 : static int __devinit vortex_probe1(struct device *gendev,
1040 : void __iomem *ioaddr, int irq,
1041 : int chip_idx, int card_idx)
1042 2 : {
1043 2 : struct vortex_private *vp;
1044 2 : int option;
1045 4 : unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1046 2 : int i, step;
1047 2 : struct net_device *dev;
1048 2 : static int printed_version;
1049 2 : int retval, print_info;
1050 4 : struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1051 4 : const char *print_name = "3c59x";
1052 4 : struct pci_dev *pdev = NULL;
1053 4 : struct eisa_device *edev = NULL;
1054 2 :
1055 6 : if (!printed_version) {
1056 4 : pr_info("%s", version);
1057 4 : printed_version = 1;
1058 2 : }
1059 2 :
1060 6 : if (gendev) {
1061 18 : if ((pdev = DEVICE_PCI(gendev))) {
1062 6 : print_name = pci_name(pdev);
1063 2 : }
1064 2 :
1065 14 : if ((edev = DEVICE_EISA(gendev))) {
1066 10 : print_name = dev_name(&edev->dev);
1067 2 : }
1068 2 : }
1069 2 :
1070 8 : dev = alloc_etherdev(sizeof(*vp));
1071 8 : retval = -ENOMEM;
1072 14 : if (!dev) {
1073 8 : pr_err(PFX "unable to allocate etherdev, aborting\n");
1074 8 : goto out;
1075 2 : }
1076 8 : SET_NETDEV_DEV(dev, gendev);
1077 16 : vp = netdev_priv(dev);
1078 2 :
1079 4 : option = global_options;
1080 2 :
1081 2 : /* The lower four bits are the media type. */
1082 6 : if (dev->mem_start) {
1083 2 : /*
1084 : * The 'options' param is passed in as the third arg to the
1085 : * LILO 'ether=' argument for non-modular use
1086 : */
1087 4 : option = dev->mem_start;
1088 : }
1089 4 : else if (card_idx < MAX_UNITS) {
1090 4 : if (options[card_idx] >= 0)
1091 2 : option = options[card_idx];
1092 : }
1093 :
1094 4 : if (option > 0) {
1095 4 : if (option & 0x8000)
1096 2 : vortex_debug = 7;
1097 4 : if (option & 0x4000)
1098 2 : vortex_debug = 2;
1099 4 : if (option & 0x0400)
1100 2 : vp->enable_wol = 1;
1101 : }
1102 :
1103 2 : print_info = (vortex_debug > 1);
1104 4 : if (print_info)
1105 2 : pr_info("See Documentation/networking/vortex.txt\n");
1106 :
1107 12 : pr_info("%s: 3Com %s %s at %p.\n",
1108 : print_name,
1109 : pdev ? "PCI" : "EISA",
1110 : vci->name,
1111 : ioaddr);
1112 :
1113 2 : dev->base_addr = (unsigned long)ioaddr;
1114 2 : dev->irq = irq;
1115 2 : dev->mtu = mtu;
1116 2 : vp->ioaddr = ioaddr;
1117 2 : vp->large_frames = mtu > 1500;
1118 2 : vp->drv_flags = vci->drv_flags;
1119 2 : vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1120 4 : vp->io_size = vci->io_size;
1121 2 : vp->card_idx = card_idx;
1122 :
1123 : /* module list only for Compaq device */
1124 4 : if (gendev == NULL) {
1125 2 : compaq_net_device = dev;
1126 : }
1127 :
1128 : /* PCI-only startup logic */
1129 4 : if (pdev) {
1130 : /* EISA resources already marked, so only PCI needs to do this here */
1131 : /* Ignore return value, because Cardbus drivers already allocate for us */
1132 10 : if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1133 2 : vp->must_free_region = 1;
1134 :
1135 : /* enable bus-mastering if necessary */
1136 4 : if (vci->flags & PCI_USES_MASTER)
1137 2 : pci_set_master(pdev);
1138 :
1139 4 : if (vci->drv_flags & IS_VORTEX) {
1140 : u8 pci_latency;
1141 2 : u8 new_latency = 248;
1142 :
1143 : /* Check the PCI latency value. On the 3c590 series the latency timer
1144 : must be set to the maximum value to avoid data corruption that occurs
1145 : when the timer expires during a transfer. This bug exists the Vortex
1146 : chip only. */
1147 4 : pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1148 4 : if (pci_latency < new_latency) {
1149 2 : pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1150 : print_name, pci_latency, new_latency);
1151 4 : pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1152 : }
1153 : }
1154 : }
1155 :
1156 16 : spin_lock_init(&vp->lock);
1157 2 : vp->gendev = gendev;
1158 2 : vp->mii.dev = dev;
1159 2 : vp->mii.mdio_read = mdio_read;
1160 2 : vp->mii.mdio_write = mdio_write;
1161 2 : vp->mii.phy_id_mask = 0x1f;
1162 2 : vp->mii.reg_num_mask = 0x1f;
1163 :
1164 : /* Makes sure rings are at least 16 byte aligned. */
1165 6 : vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1166 : + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1167 : &vp->rx_ring_dma);
1168 2 : retval = -ENOMEM;
1169 6 : if (!vp->rx_ring)
1170 2 : goto free_region;
1171 :
1172 2 : vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1173 2 : vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1174 :
1175 : /* if we are a PCI driver, we store info in pdev->driver_data
1176 : * instead of a module list */
1177 4 : if (pdev)
1178 4 : pci_set_drvdata(pdev, dev);
1179 8 : if (edev)
1180 8 : eisa_set_drvdata(edev, dev);
1181 :
1182 6 : vp->media_override = 7;
1183 12 : if (option >= 0) {
1184 36 : vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1185 12 : if (vp->media_override != 7)
1186 6 : vp->medialock = 1;
1187 6 : vp->full_duplex = (option & 0x200) ? 1 : 0;
1188 6 : vp->bus_master = (option & 16) ? 1 : 0;
1189 : }
1190 :
1191 12 : if (global_full_duplex > 0)
1192 6 : vp->full_duplex = 1;
1193 12 : if (global_enable_wol > 0)
1194 6 : vp->enable_wol = 1;
1195 :
1196 12 : if (card_idx < MAX_UNITS) {
1197 12 : if (full_duplex[card_idx] > 0)
1198 6 : vp->full_duplex = 1;
1199 12 : if (flow_ctrl[card_idx] > 0)
1200 6 : vp->flow_ctrl = 1;
1201 12 : if (enable_wol[card_idx] > 0)
1202 6 : vp->enable_wol = 1;
1203 : }
1204 :
1205 6 : vp->mii.force_media = vp->full_duplex;
1206 6 : vp->options = option;
1207 : /* Read the station address from the EEPROM. */
1208 6 : EL3WINDOW(0);
1209 : {
1210 : int base;
1211 :
1212 12 : if (vci->drv_flags & EEPROM_8BIT)
1213 6 : base = 0x230;
1214 12 : else if (vci->drv_flags & EEPROM_OFFSET)
1215 6 : base = EEPROM_Read + 0x30;
1216 : else
1217 6 : base = EEPROM_Read;
1218 :
1219 18 : for (i = 0; i < 0x40; i++) {
1220 2 : int timer;
1221 6 : iowrite16(base + i, ioaddr + Wn0EepromCmd);
1222 : /* Pause for at least 162 us. for the read to take place. */
1223 10 : for (timer = 10; timer >= 0; timer--) {
1224 6 : udelay(162);
1225 8 : if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1226 2 : break;
1227 : }
1228 2 : eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1229 2 : }
1230 : }
1231 10 : for (i = 0; i < 0x18; i++)
1232 6 : checksum ^= eeprom[i];
1233 4 : checksum = (checksum ^ (checksum >> 8)) & 0xff;
1234 4 : if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1235 6 : while (i < 0x21)
1236 8 : checksum ^= eeprom[i++];
1237 6 : checksum = (checksum ^ (checksum >> 8)) & 0xff;
1238 : }
1239 16 : if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1240 4 : pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1241 14 : for (i = 0; i < 3; i++)
1242 8 : ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1243 10 : memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1244 4 : if (print_info)
1245 2 : pr_cont(" %pM", dev->dev_addr);
1246 : /* Unfortunately an all zero eeprom passes the checksum and this
1247 : gets found in the wild in failure cases. Crypto is hard 8) */
1248 12 : if (!is_valid_ether_addr(dev->dev_addr)) {
1249 2 : retval = -EINVAL;
1250 2 : pr_err("*** EEPROM MAC address is invalid.\n");
1251 2 : goto free_ring; /* With every pack */
1252 : }
1253 2 : EL3WINDOW(2);
1254 10 : for (i = 0; i < 6; i++)
1255 4 : iowrite8(dev->dev_addr[i], ioaddr + i);
1256 4 :
1257 4 : if (print_info)
1258 2 : pr_cont(", IRQ %d\n", dev->irq);
1259 : /* Tell them about an invalid IRQ. */
1260 8 : if (dev->irq <= 0 || dev->irq >= nr_irqs)
1261 2 : pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1262 : dev->irq);
1263 :
1264 2 : EL3WINDOW(4);
1265 4 : step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1266 4 : if (print_info) {
1267 2 : pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1268 : eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1269 : step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1270 : }
1271 :
1272 :
1273 8 : if (pdev && vci->drv_flags & HAS_CB_FNS) {
1274 : unsigned short n;
1275 :
1276 2 : vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1277 6 : if (!vp->cb_fn_base) {
1278 2 : retval = -ENOMEM;
1279 2 : goto free_ring;
1280 : }
1281 :
1282 4 : if (print_info) {
1283 2 : pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1284 : print_name,
1285 : (unsigned long long)pci_resource_start(pdev, 2),
1286 : vp->cb_fn_base);
1287 : }
1288 2 : EL3WINDOW(2);
1289 :
1290 4 : n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1291 4 : if (vp->drv_flags & INVERT_LED_PWR)
1292 2 : n |= 0x10;
1293 4 : if (vp->drv_flags & INVERT_MII_PWR)
1294 2 : n |= 0x4000;
1295 2 : iowrite16(n, ioaddr + Wn2_ResetOptions);
1296 4 : if (vp->drv_flags & WNO_XCVR_PWR) {
1297 2 : EL3WINDOW(0);
1298 2 : iowrite16(0x0800, ioaddr);
1299 : }
1300 : }
1301 :
1302 : /* Extract our information from the EEPROM data. */
1303 2 : vp->info1 = eeprom[13];
1304 2 : vp->info2 = eeprom[15];
1305 2 : vp->capabilities = eeprom[16];
1306 :
1307 6 : if (vp->info1 & 0x8000) {
1308 2 : vp->full_duplex = 1;
1309 4 : if (print_info)
1310 2 : pr_info("Full duplex capable\n");
1311 : }
1312 :
1313 : {
1314 8 : static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1315 : unsigned int config;
1316 2 : EL3WINDOW(3);
1317 4 : vp->available_media = ioread16(ioaddr + Wn3_Options);
1318 6 : if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1319 2 : vp->available_media = 0x40;
1320 2 : config = ioread32(ioaddr + Wn3_Config);
1321 4 : if (print_info) {
1322 : pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1323 : config, ioread16(ioaddr + Wn3_Options));
1324 8 : pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1325 8 : 8 << RAM_SIZE(config),
1326 16 : RAM_WIDTH(config) ? "word" : "byte",
1327 : ram_split[RAM_SPLIT(config)],
1328 : AUTOSELECT(config) ? "autoselect/" : "",
1329 : XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1330 : media_tbl[XCVR(config)].name);
1331 : }
1332 2 : vp->default_media = XCVR(config);
1333 4 : if (vp->default_media == XCVR_NWAY)
1334 2 : vp->has_nway = 1;
1335 2 : vp->autoselect = AUTOSELECT(config);
1336 : }
1337 :
1338 4 : if (vp->media_override != 7) {
1339 6 : pr_info("%s: Media override to transceiver type %d (%s).\n",
1340 : print_name, vp->media_override,
1341 : media_tbl[vp->media_override].name);
1342 4 : dev->if_port = vp->media_override;
1343 : } else
1344 4 : dev->if_port = vp->default_media;
1345 :
1346 22 : if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1347 : dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1348 2 : int phy, phy_idx = 0;
1349 2 : EL3WINDOW(4);
1350 2 : mii_preamble_required++;
1351 4 : if (vp->drv_flags & EXTRA_PREAMBLE)
1352 2 : mii_preamble_required++;
1353 4 : mdio_sync(ioaddr, 32);
1354 4 : mdio_read(dev, 24, MII_BMSR);
1355 14 : for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1356 4 : int mii_status, phyx;
1357 2 :
1358 : /*
1359 : * For the 3c905CX we look at index 24 first, because it bogusly
1360 : * reports an external PHY at all indices
1361 : */
1362 4 : if (phy == 0)
1363 2 : phyx = 24;
1364 4 : else if (phy <= 24)
1365 2 : phyx = phy - 1;
1366 : else
1367 2 : phyx = phy;
1368 4 : mii_status = mdio_read(dev, phyx, MII_BMSR);
1369 8 : if (mii_status && mii_status != 0xffff) {
1370 6 : vp->phys[phy_idx++] = phyx;
1371 4 : if (print_info) {
1372 2 : pr_info(" MII transceiver found at address %d, status %4x.\n",
1373 : phyx, mii_status);
1374 : }
1375 4 : if ((mii_status & 0x0040) == 0)
1376 2 : mii_preamble_required++;
1377 : }
1378 : }
1379 2 : mii_preamble_required--;
1380 4 : if (phy_idx == 0) {
1381 2 : pr_warning(" ***WARNING*** No MII transceivers found!\n");
1382 2 : vp->phys[0] = 24;
1383 : } else {
1384 6 : vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1385 4 : if (vp->full_duplex) {
1386 : /* Only advertise the FD media types. */
1387 4 : vp->advertising &= ~0x02A0;
1388 6 : mdio_write(dev, vp->phys[0], 4, vp->advertising);
1389 : }
1390 : }
1391 6 : vp->mii.phy_id = vp->phys[0];
1392 : }
1393 :
1394 24 : if (vp->capabilities & CapBusMaster) {
1395 8 : vp->full_bus_master_tx = 1;
1396 16 : if (print_info) {
1397 56 : pr_info(" Enabling bus-master transmits and %s receives.\n",
1398 : (vp->info2 & 1) ? "early" : "whole-frame" );
1399 : }
1400 56 : vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1401 8 : vp->bus_master = 0; /* AKPM: vortex only */
1402 : }
1403 :
1404 : /* The 3c59x-specific entries in the device structure. */
1405 16 : if (vp->full_bus_master_tx) {
1406 8 : dev->netdev_ops = &boomrang_netdev_ops;
1407 : /* Actually, it still should work with iommu. */
1408 64 : if (card_idx < MAX_UNITS &&
1409 : ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1410 : hw_checksums[card_idx] == 1)) {
1411 8 : dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1412 : }
1413 : } else
1414 8 : dev->netdev_ops = &vortex_netdev_ops;
1415 :
1416 16 : if (print_info) {
1417 64 : pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1418 32 : print_name,
1419 : (dev->features & NETIF_F_SG) ? "en":"dis",
1420 : (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1421 : }
1422 :
1423 8 : dev->ethtool_ops = &vortex_ethtool_ops;
1424 8 : dev->watchdog_timeo = (watchdog * HZ) / 1000;
1425 :
1426 16 : if (pdev) {
1427 8 : vp->pm_state_valid = 1;
1428 104 : pci_save_state(VORTEX_PCI(vp));
1429 24 : acpi_set_WOL(dev);
1430 : }
1431 20 : retval = register_netdev(dev);
1432 4 : if (retval == 0)
1433 2 : return 0;
1434 :
1435 : free_ring:
1436 18 : pci_free_consistent(pdev,
1437 2 : sizeof(struct boom_rx_desc) * RX_RING_SIZE
1438 2 : + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1439 : vp->rx_ring,
1440 : vp->rx_ring_dma);
1441 : free_region:
1442 8 : if (vp->must_free_region)
1443 12 : release_region(dev->base_addr, vci->io_size);
1444 8 : free_netdev(dev);
1445 2 : pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1446 : out:
1447 10 : return retval;
1448 : }
1449 :
1450 : static void
1451 : issue_and_wait(struct net_device *dev, int cmd)
1452 : {
1453 7320 : struct vortex_private *vp = netdev_priv(dev);
1454 3660 : void __iomem *ioaddr = vp->ioaddr;
1455 1830 : int i;
1456 1830 :
1457 3660 : iowrite16(cmd, ioaddr + EL3_CMD);
1458 10980 : for (i = 0; i < 2000; i++) {
1459 10980 : if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1460 3660 : return;
1461 : }
1462 :
1463 : /* OK, that didn't work. Do it the slow way. One second */
1464 9150 : for (i = 0; i < 100000; i++) {
1465 7320 : if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1466 7320 : if (vortex_debug > 1)
1467 1830 : pr_info("%s: command 0x%04x took %d usecs\n",
1468 : dev->name, cmd, i * 10);
1469 1830 : return;
1470 : }
1471 1830 : udelay(10);
1472 : }
1473 3660 : pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1474 1830 : dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1475 : }
1476 :
1477 : static void
1478 : vortex_set_duplex(struct net_device *dev)
1479 : {
1480 2080 : struct vortex_private *vp = netdev_priv(dev);
1481 1040 : void __iomem *ioaddr = vp->ioaddr;
1482 520 :
1483 3120 : pr_info("%s: setting %s-duplex.\n",
1484 : dev->name, (vp->full_duplex) ? "full" : "half");
1485 :
1486 520 : EL3WINDOW(3);
1487 : /* Set the full-duplex bit. */
1488 7280 : iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1489 : (vp->large_frames ? 0x40 : 0) |
1490 : ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1491 : 0x100 : 0),
1492 : ioaddr + Wn3_MAC_Ctrl);
1493 520 : }
1494 :
1495 : static void vortex_check_media(struct net_device *dev, unsigned int init)
1496 : {
1497 520 : struct vortex_private *vp = netdev_priv(dev);
1498 260 : unsigned int ok_to_print = 0;
1499 130 :
1500 390 : if (vortex_debug > 3)
1501 130 : ok_to_print = 1;
1502 :
1503 390 : if (mii_check_media(&vp->mii, ok_to_print, init)) {
1504 130 : vp->full_duplex = vp->mii.full_duplex;
1505 260 : vortex_set_duplex(dev);
1506 260 : } else if (init) {
1507 260 : vortex_set_duplex(dev);
1508 390 : }
1509 : }
1510 :
1511 : static int
1512 : vortex_up(struct net_device *dev)
1513 : {
1514 520 : struct vortex_private *vp = netdev_priv(dev);
1515 260 : void __iomem *ioaddr = vp->ioaddr;
1516 130 : unsigned int config;
1517 260 : int i, mii_reg1, mii_reg5, err = 0;
1518 130 :
1519 1430 : if (VORTEX_PCI(vp)) {
1520 1820 : pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1521 390 : if (vp->pm_state_valid)
1522 1820 : pci_restore_state(VORTEX_PCI(vp));
1523 1820 : err = pci_enable_device(VORTEX_PCI(vp));
1524 390 : if (err) {
1525 260 : pr_warning("%s: Could not enable device\n",
1526 130 : dev->name);
1527 260 : goto err_out;
1528 130 : }
1529 130 : }
1530 130 :
1531 130 : /* Before initializing select the active media port. */
1532 260 : EL3WINDOW(3);
1533 260 : config = ioread32(ioaddr + Wn3_Config);
1534 130 :
1535 390 : if (vp->media_override != 7) {
1536 520 : pr_info("%s: Media override to transceiver %d (%s).\n",
1537 : dev->name, vp->media_override,
1538 : media_tbl[vp->media_override].name);
1539 260 : dev->if_port = vp->media_override;
1540 260 : } else if (vp->autoselect) {
1541 260 : if (vp->has_nway) {
1542 260 : if (vortex_debug > 1)
1543 260 : pr_info("%s: using NWAY device table, not %d\n",
1544 : dev->name, dev->if_port);
1545 130 : dev->if_port = XCVR_NWAY;
1546 : } else {
1547 : /* Find first available media type, starting with 100baseTx. */
1548 130 : dev->if_port = XCVR_100baseTx;
1549 650 : while (! (vp->available_media & media_tbl[dev->if_port].mask))
1550 390 : dev->if_port = media_tbl[dev->if_port].next;
1551 520 : if (vortex_debug > 1)
1552 260 : pr_info("%s: first available media type: %s\n",
1553 : dev->name, media_tbl[dev->if_port].name);
1554 : }
1555 : } else {
1556 260 : dev->if_port = vp->default_media;
1557 260 : if (vortex_debug > 1)
1558 260 : pr_info("%s: using default media %s\n",
1559 : dev->name, media_tbl[dev->if_port].name);
1560 : }
1561 :
1562 260 : init_timer(&vp->timer);
1563 520 : vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1564 260 : vp->timer.data = (unsigned long)dev;
1565 260 : vp->timer.function = vortex_timer; /* timer handler */
1566 260 : add_timer(&vp->timer);
1567 :
1568 260 : init_timer(&vp->rx_oom_timer);
1569 260 : vp->rx_oom_timer.data = (unsigned long)dev;
1570 260 : vp->rx_oom_timer.function = rx_oom_timer;
1571 :
1572 : if (vortex_debug > 1)
1573 : pr_debug("%s: Initial media type %s.\n",
1574 : dev->name, media_tbl[dev->if_port].name);
1575 :
1576 260 : vp->full_duplex = vp->mii.force_media;
1577 520 : config = BFINS(config, dev->if_port, 20, 4);
1578 : if (vortex_debug > 6)
1579 : pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1580 260 : iowrite32(config, ioaddr + Wn3_Config);
1581 :
1582 1560 : if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1583 260 : EL3WINDOW(4);
1584 520 : mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1585 260 : mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1586 130 : vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1587 130 : vp->mii.full_duplex = vp->full_duplex;
1588 :
1589 520 : vortex_check_media(dev, 1);
1590 : }
1591 : else
1592 520 : vortex_set_duplex(dev);
1593 :
1594 780 : issue_and_wait(dev, TxReset);
1595 : /*
1596 : * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1597 : */
1598 390 : issue_and_wait(dev, RxReset|0x04);
1599 :
1600 :
1601 130 : iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1602 :
1603 260 : if (vortex_debug > 1) {
1604 130 : EL3WINDOW(4);
1605 : pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1606 : dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1607 : }
1608 :
1609 : /* Set the station address and mask in window 2 each time opened. */
1610 130 : EL3WINDOW(2);
1611 650 : for (i = 0; i < 6; i++)
1612 260 : iowrite8(dev->dev_addr[i], ioaddr + i);
1613 780 : for (; i < 12; i+=2)
1614 260 : iowrite16(0, ioaddr + i);
1615 260 :
1616 390 : if (vp->cb_fn_base) {
1617 260 : unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1618 260 : if (vp->drv_flags & INVERT_LED_PWR)
1619 130 : n |= 0x10;
1620 260 : if (vp->drv_flags & INVERT_MII_PWR)
1621 130 : n |= 0x4000;
1622 130 : iowrite16(n, ioaddr + Wn2_ResetOptions);
1623 : }
1624 :
1625 390 : if (dev->if_port == XCVR_10base2)
1626 : /* Start the thinnet transceiver. We should really wait 50ms...*/
1627 130 : iowrite16(StartCoax, ioaddr + EL3_CMD);
1628 390 : if (dev->if_port != XCVR_NWAY) {
1629 130 : EL3WINDOW(4);
1630 390 : iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1631 : media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1632 : }
1633 :
1634 : /* Switch to the stats window, and clear all stats by reading. */
1635 130 : iowrite16(StatsDisable, ioaddr + EL3_CMD);
1636 130 : EL3WINDOW(6);
1637 650 : for (i = 0; i < 10; i++)
1638 260 : ioread8(ioaddr + i);
1639 390 : ioread16(ioaddr + 10);
1640 130 : ioread16(ioaddr + 12);
1641 : /* New: On the Vortex we must also clear the BadSSD counter. */
1642 130 : EL3WINDOW(4);
1643 130 : ioread8(ioaddr + 12);
1644 : /* ..and on the Boomerang we enable the extra statistics bits. */
1645 130 : iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1646 :
1647 : /* Switch to register set 7 for normal use. */
1648 130 : EL3WINDOW(7);
1649 :
1650 260 : if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1651 390 : vp->cur_rx = vp->dirty_rx = 0;
1652 : /* Initialize the RxEarly register as recommended. */
1653 130 : iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1654 130 : iowrite32(0x0020, ioaddr + PktStatus);
1655 260 : iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1656 : }
1657 260 : if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1658 390 : vp->cur_tx = vp->dirty_tx = 0;
1659 260 : if (vp->drv_flags & IS_BOOMERANG)
1660 130 : iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1661 : /* Clear the Rx, Tx rings. */
1662 650 : for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1663 390 : vp->rx_ring[i].status = 0;
1664 780 : for (i = 0; i < TX_RING_SIZE; i++)
1665 390 : vp->tx_skbuff[i] = NULL;
1666 260 : iowrite32(0, ioaddr + DownListPtr);
1667 : }
1668 : /* Set receiver mode: presumably accept b-case and phys addr only. */
1669 520 : set_rx_mode(dev);
1670 : /* enable 802.1q tagged frames */
1671 260 : set_8021q_mode(dev, 1);
1672 130 : iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1673 :
1674 130 : iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1675 130 : iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1676 : /* Allow status bits to be seen. */
1677 2080 : vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1678 : (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1679 : (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1680 : (vp->bus_master ? DMADone : 0);
1681 1430 : vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1682 : (vp->full_bus_master_rx ? 0 : RxComplete) |
1683 : StatsFull | HostError | TxComplete | IntReq
1684 : | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1685 260 : iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1686 : /* Ack all pending events, and set active indicator mask. */
1687 130 : iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1688 : ioaddr + EL3_CMD);
1689 260 : iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1690 390 : if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1691 130 : iowrite32(0x8000, vp->cb_fn_base + 4);
1692 260 : netif_start_queue (dev);
1693 : err_out:
1694 390 : return err;
1695 : }
1696 :
1697 : static int
1698 : vortex_open(struct net_device *dev)
1699 : {
1700 40 : struct vortex_private *vp = netdev_priv(dev);
1701 10 : int i;
1702 10 : int retval;
1703 10 :
1704 10 : /* Use the now-standard shared IRQ implementation. */
1705 140 : if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1706 10 : &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1707 30 : pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1708 30 : goto err;
1709 10 : }
1710 :
1711 40 : if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1712 : if (vortex_debug > 2)
1713 : pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1714 100 : for (i = 0; i < RX_RING_SIZE; i++) {
1715 20 : struct sk_buff *skb;
1716 80 : vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1717 20 : vp->rx_ring[i].status = 0; /* Clear complete bit. */
1718 20 : vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1719 :
1720 40 : skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1721 : GFP_KERNEL);
1722 20 : vp->rx_skbuff[i] = skb;
1723 40 : if (skb == NULL)
1724 20 : break; /* Bad news! */
1725 :
1726 40 : skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
1727 320 : vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1728 : }
1729 40 : if (i != RX_RING_SIZE) {
1730 : int j;
1731 20 : pr_emerg("%s: no memory for rx ring\n", dev->name);
1732 100 : for (j = 0; j < i; j++) {
1733 80 : if (vp->rx_skbuff[j]) {
1734 40 : dev_kfree_skb(vp->rx_skbuff[j]);
1735 20 : vp->rx_skbuff[j] = NULL;
1736 : }
1737 : }
1738 20 : retval = -ENOMEM;
1739 20 : goto err_free_irq;
1740 : }
1741 : /* Wrap the ring. */
1742 40 : vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1743 : }
1744 :
1745 120 : retval = vortex_up(dev);
1746 40 : if (!retval)
1747 20 : goto out;
1748 :
1749 : err_free_irq:
1750 80 : free_irq(dev->irq, dev);
1751 20 : err:
1752 100 : if (vortex_debug > 1)
1753 40 : pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1754 : out:
1755 60 : return retval;
1756 : }
1757 :
1758 40 : static void
1759 : vortex_timer(unsigned long data)
1760 : {
1761 0 : struct net_device *dev = (struct net_device *)data;
1762 0 : struct vortex_private *vp = netdev_priv(dev);
1763 0 : void __iomem *ioaddr = vp->ioaddr;
1764 0 : int next_tick = 60*HZ;
1765 0 : int ok = 0;
1766 0 : int media_status, old_window;
1767 0 :
1768 0 : if (vortex_debug > 2) {
1769 0 : pr_debug("%s: Media selection timer tick happened, %s.\n",
1770 0 : dev->name, media_tbl[dev->if_port].name);
1771 0 : pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1772 0 : }
1773 :
1774 0 : disable_irq_lockdep(dev->irq);
1775 0 : old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1776 0 : EL3WINDOW(4);
1777 0 : media_status = ioread16(ioaddr + Wn4_Media);
1778 : switch (dev->if_port) {
1779 0 : case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1780 0 : if (media_status & Media_LnkBeat) {
1781 0 : netif_carrier_on(dev);
1782 0 : ok = 1;
1783 : if (vortex_debug > 1)
1784 : pr_debug("%s: Media %s has link beat, %x.\n",
1785 : dev->name, media_tbl[dev->if_port].name, media_status);
1786 : } else {
1787 0 : netif_carrier_off(dev);
1788 : if (vortex_debug > 1) {
1789 : pr_debug("%s: Media %s has no link beat, %x.\n",
1790 : dev->name, media_tbl[dev->if_port].name, media_status);
1791 : }
1792 : }
1793 0 : break;
1794 0 : case XCVR_MII: case XCVR_NWAY:
1795 0 : {
1796 0 : ok = 1;
1797 : /* Interrupts are already disabled */
1798 0 : spin_lock(&vp->lock);
1799 0 : vortex_check_media(dev, 0);
1800 0 : spin_unlock(&vp->lock);
1801 : }
1802 0 : break;
1803 0 : default: /* Other media types handled by Tx timeouts. */
1804 0 : if (vortex_debug > 1)
1805 0 : pr_debug("%s: Media %s has no indication, %x.\n",
1806 0 : dev->name, media_tbl[dev->if_port].name, media_status);
1807 0 : ok = 1;
1808 0 : }
1809 :
1810 0 : if (!netif_carrier_ok(dev))
1811 0 : next_tick = 5*HZ;
1812 :
1813 0 : if (vp->medialock)
1814 0 : goto leave_media_alone;
1815 :
1816 0 : if (!ok) {
1817 0 : unsigned int config;
1818 :
1819 : do {
1820 0 : dev->if_port = media_tbl[dev->if_port].next;
1821 0 : } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1822 0 : if (dev->if_port == XCVR_Default) { /* Go back to default. */
1823 0 : dev->if_port = vp->default_media;
1824 : if (vortex_debug > 1)
1825 : pr_debug("%s: Media selection failing, using default %s port.\n",
1826 : dev->name, media_tbl[dev->if_port].name);
1827 : } else {
1828 : if (vortex_debug > 1)
1829 : pr_debug("%s: Media selection failed, now trying %s port.\n",
1830 : dev->name, media_tbl[dev->if_port].name);
1831 0 : next_tick = media_tbl[dev->if_port].wait;
1832 : }
1833 0 : iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1834 : media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1835 :
1836 0 : EL3WINDOW(3);
1837 0 : config = ioread32(ioaddr + Wn3_Config);
1838 0 : config = BFINS(config, dev->if_port, 20, 4);
1839 0 : iowrite32(config, ioaddr + Wn3_Config);
1840 :
1841 0 : iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1842 : ioaddr + EL3_CMD);
1843 : if (vortex_debug > 1)
1844 : pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1845 : /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1846 0 : }
1847 :
1848 : leave_media_alone:
1849 : if (vortex_debug > 2)
1850 : pr_debug("%s: Media selection timer finished, %s.\n",
1851 : dev->name, media_tbl[dev->if_port].name);
1852 :
1853 0 : EL3WINDOW(old_window);
1854 0 : enable_irq_lockdep(dev->irq);
1855 0 : mod_timer(&vp->timer, RUN_AT(next_tick));
1856 0 : if (vp->deferred)
1857 0 : iowrite16(FakeIntr, ioaddr + EL3_CMD);
1858 0 : return;
1859 : }
1860 :
1861 : static void vortex_tx_timeout(struct net_device *dev)
1862 : {
1863 40 : struct vortex_private *vp = netdev_priv(dev);
1864 20 : void __iomem *ioaddr = vp->ioaddr;
1865 10 :
1866 40 : pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1867 10 : dev->name, ioread8(ioaddr + TxStatus),
1868 10 : ioread16(ioaddr + EL3_STATUS));
1869 20 : EL3WINDOW(4);
1870 60 : pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1871 10 : ioread16(ioaddr + Wn4_NetDiag),
1872 10 : ioread16(ioaddr + Wn4_Media),
1873 10 : ioread32(ioaddr + PktStatus),
1874 10 : ioread16(ioaddr + Wn4_FIFODiag));
1875 10 : /* Slight code bloat to be user friendly. */
1876 40 : if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1877 10 : pr_err("%s: Transmitter encountered 16 collisions --"
1878 : " network cable problem?\n", dev->name);
1879 30 : if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1880 10 : pr_err("%s: Interrupt posted but not delivered --"
1881 : " IRQ blocked by another device?\n", dev->name);
1882 : /* Bad idea here.. but we might as well handle a few events. */
1883 : {
1884 : /*
1885 : * Block interrupts because vortex_interrupt does a bare spin_lock()
1886 : */
1887 : unsigned long flags;
1888 20 : local_irq_save(flags);
1889 20 : if (vp->full_bus_master_tx)
1890 30 : boomerang_interrupt(dev->irq, dev);
1891 : else
1892 30 : vortex_interrupt(dev->irq, dev);
1893 100 : local_irq_restore(flags);
1894 : }
1895 : }
1896 :
1897 60 : if (vortex_debug > 0)
1898 120 : dump_tx_ring(dev);
1899 :
1900 120 : issue_and_wait(dev, TxReset);
1901 :
1902 10 : dev->stats.tx_errors++;
1903 20 : if (vp->full_bus_master_tx) {
1904 : pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1905 50 : if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1906 20 : iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1907 : ioaddr + DownListPtr);
1908 20 : if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1909 20 : netif_wake_queue (dev);
1910 40 : if (vp->drv_flags & IS_BOOMERANG)
1911 20 : iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1912 20 : iowrite16(DownUnstall, ioaddr + EL3_CMD);
1913 : } else {
1914 10 : dev->stats.tx_dropped++;
1915 20 : netif_wake_queue(dev);
1916 : }
1917 :
1918 : /* Issue Tx Enable */
1919 30 : iowrite16(TxEnable, ioaddr + EL3_CMD);
1920 30 : dev->trans_start = jiffies;
1921 :
1922 : /* Switch to register set 7 for normal use. */
1923 30 : EL3WINDOW(7);
1924 30 : }
1925 :
1926 : /*
1927 : * Handle uncommon interrupt sources. This is a separate routine to minimize
1928 : * the cache impact.
1929 : */
1930 : static void
1931 : vortex_error(struct net_device *dev, int status)
1932 : {
1933 360 : struct vortex_private *vp = netdev_priv(dev);
1934 180 : void __iomem *ioaddr = vp->ioaddr;
1935 270 : int do_tx_reset = 0, reset_mask = 0;
1936 180 : unsigned char tx_status = 0;
1937 90 :
1938 270 : if (vortex_debug > 2) {
1939 180 : pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1940 90 : }
1941 90 :
1942 270 : if (status & TxComplete) { /* Really "TxError" for us. */
1943 270 : tx_status = ioread8(ioaddr + TxStatus);
1944 90 : /* Presumably a tx-timeout. We must merely re-enable. */
1945 630 : if (vortex_debug > 2 ||
1946 90 : (tx_status != 0x88 && vortex_debug > 0)) {
1947 90 : pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1948 : dev->name, tx_status);
1949 180 : if (tx_status == 0x82) {
1950 90 : pr_err("Probably a duplex mismatch. See "
1951 : "Documentation/networking/vortex.txt\n");
1952 : }
1953 360 : dump_tx_ring(dev);
1954 : }
1955 540 : if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1956 540 : if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1957 540 : if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1958 180 : iowrite8(0, ioaddr + TxStatus);
1959 360 : if (tx_status & 0x30) { /* txJabber or txUnderrun */
1960 180 : do_tx_reset = 1;
1961 720 : } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1962 180 : do_tx_reset = 1;
1963 180 : reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1964 : } else { /* Merely re-enable the transmitter. */
1965 180 : iowrite16(TxEnable, ioaddr + EL3_CMD);
1966 : }
1967 : }
1968 :
1969 360 : if (status & RxEarly) { /* Rx early is unused. */
1970 360 : vortex_rx(dev);
1971 90 : iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1972 : }
1973 540 : if (status & StatsFull) { /* Empty statistics. */
1974 : static int DoneDidThat;
1975 : if (vortex_debug > 4)
1976 : pr_debug("%s: Updating stats.\n", dev->name);
1977 540 : update_stats(ioaddr, dev);
1978 : /* HACK: Disable statistics as an interrupt source. */
1979 : /* This occurs when we have the wrong media type! */
1980 450 : if (DoneDidThat == 0 &&
1981 : ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1982 90 : pr_warning("%s: Updating statistics failed, disabling "
1983 : "stats as an interrupt source.\n", dev->name);
1984 90 : EL3WINDOW(5);
1985 180 : iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1986 180 : vp->intr_enable &= ~StatsFull;
1987 90 : EL3WINDOW(7);
1988 90 : DoneDidThat++;
1989 : }
1990 : }
1991 720 : if (status & IntReq) { /* Restore all interrupt sources. */
1992 720 : iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1993 720 : iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1994 : }
1995 720 : if (status & HostError) {
1996 : u16 fifo_diag;
1997 360 : EL3WINDOW(4);
1998 720 : fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1999 360 : pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2000 : dev->name, fifo_diag);
2001 : /* Adapter failure requires Tx/Rx reset and reinit. */
2002 720 : if (vp->full_bus_master_tx) {
2003 720 : int bus_status = ioread32(ioaddr + PktStatus);
2004 : /* 0x80000000 PCI master abort. */
2005 : /* 0x40000000 PCI target abort. */
2006 720 : if (vortex_debug)
2007 360 : pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2008 :
2009 : /* In this case, blow the card away */
2010 : /* Must not enter D3 or we can't legally issue the reset! */
2011 1080 : vortex_down(dev, 0);
2012 270 : issue_and_wait(dev, TotalReset | 0xff);
2013 270 : vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2014 720 : } else if (fifo_diag & 0x0400)
2015 360 : do_tx_reset = 1;
2016 900 : if (fifo_diag & 0x3000) {
2017 : /* Reset Rx fifo and upload logic */
2018 1350 : issue_and_wait(dev, RxReset|0x07);
2019 : /* Set the Rx filter to the current state. */
2020 180 : set_rx_mode(dev);
2021 : /* enable 802.1q VLAN tagged frames */
2022 180 : set_8021q_mode(dev, 1);
2023 90 : iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2024 90 : iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2025 : }
2026 : }
2027 :
2028 1080 : if (do_tx_reset) {
2029 1620 : issue_and_wait(dev, TxReset|reset_mask);
2030 90 : iowrite16(TxEnable, ioaddr + EL3_CMD);
2031 180 : if (!vp->full_bus_master_tx)
2032 180 : netif_wake_queue(dev);
2033 : }
2034 720 : }
2035 :
2036 : static netdev_tx_t
2037 : vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2038 : {
2039 40 : struct vortex_private *vp = netdev_priv(dev);
2040 20 : void __iomem *ioaddr = vp->ioaddr;
2041 10 :
2042 10 : /* Put out the doubleword header... */
2043 20 : iowrite32(skb->len, ioaddr + TX_FIFO);
2044 30 : if (vp->bus_master) {
2045 10 : /* Set the bus-master controller to transfer the packet. */
2046 20 : int len = (skb->len + 3) & ~3;
2047 180 : iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
2048 10 : ioaddr + Wn7_MasterAddr);
2049 20 : iowrite16(len, ioaddr + Wn7_MasterLen);
2050 20 : vp->tx_skb = skb;
2051 10 : iowrite16(StartDMADown, ioaddr + EL3_CMD);
2052 : /* netif_wake_queue() will be called at the DMADone interrupt. */
2053 : } else {
2054 : /* ... and the packet rounded to a doubleword. */
2055 20 : iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2056 10 : dev_kfree_skb (skb);
2057 30 : if (ioread16(ioaddr + TxFree) > 1536) {
2058 20 : netif_start_queue (dev); /* AKPM: redundant? */
2059 : } else {
2060 : /* Interrupt us when the FIFO has room for max-sized packet. */
2061 20 : netif_stop_queue(dev);
2062 10 : iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2063 : }
2064 : }
2065 :
2066 30 : dev->trans_start = jiffies;
2067 :
2068 : /* Clear the Tx status stack. */
2069 : {
2070 : int tx_status;
2071 30 : int i = 32;
2072 :
2073 100 : while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2074 30 : if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2075 10 : if (vortex_debug > 2)
2076 : pr_debug("%s: Tx error, status %2.2x.\n",
2077 : dev->name, tx_status);
2078 40 : if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2079 30 : if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2080 20 : if (tx_status & 0x30) {
2081 30 : issue_and_wait(dev, TxReset);
2082 : }
2083 30 : iowrite16(TxEnable, ioaddr + EL3_CMD);
2084 : }
2085 20 : iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2086 : }
2087 20 : }
2088 10 : return NETDEV_TX_OK;
2089 : }
2090 :
2091 : static netdev_tx_t
2092 : boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2093 : {
2094 0 : struct vortex_private *vp = netdev_priv(dev);
2095 0 : void __iomem *ioaddr = vp->ioaddr;
2096 0 : /* Calculate the next Tx descriptor entry. */
2097 0 : int entry = vp->cur_tx % TX_RING_SIZE;
2098 0 : struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2099 0 : unsigned long flags;
2100 0 :
2101 0 : if (vortex_debug > 6) {
2102 0 : pr_debug("boomerang_start_xmit()\n");
2103 0 : pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2104 0 : dev->name, vp->cur_tx);
2105 0 : }
2106 0 :
2107 0 : if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2108 0 : if (vortex_debug > 0)
2109 0 : pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
2110 0 : dev->name);
2111 0 : netif_stop_queue(dev);
2112 0 : return NETDEV_TX_BUSY;
2113 0 : }
2114 0 :
2115 0 : vp->tx_skbuff[entry] = skb;
2116 0 :
2117 0 : vp->tx_ring[entry].next = 0;
2118 0 : #if DO_ZEROCOPY
2119 0 : if (skb->ip_summed != CHECKSUM_PARTIAL)
2120 0 : vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2121 : else
2122 0 : vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2123 :
2124 0 : if (!skb_shinfo(skb)->nr_frags) {
2125 0 : vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2126 : skb->len, PCI_DMA_TODEVICE));
2127 0 : vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2128 : } else {
2129 : int i;
2130 :
2131 0 : vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2132 : skb->len-skb->data_len, PCI_DMA_TODEVICE));
2133 0 : vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2134 :
2135 0 : for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2136 0 : skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2137 0 :
2138 0 : vp->tx_ring[entry].frag[i+1].addr =
2139 0 : cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2140 : (void*)page_address(frag->page) + frag->page_offset,
2141 : frag->size, PCI_DMA_TODEVICE));
2142 :
2143 0 : if (i == skb_shinfo(skb)->nr_frags-1)
2144 0 : vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2145 : else
2146 0 : vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2147 : }
2148 : }
2149 : #else
2150 : vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2151 : vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2152 : vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2153 : #endif
2154 :
2155 0 : spin_lock_irqsave(&vp->lock, flags);
2156 : /* Wait for the stall to complete. */
2157 0 : issue_and_wait(dev, DownStall);
2158 0 : prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2159 0 : if (ioread32(ioaddr + DownListPtr) == 0) {
2160 0 : iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2161 0 : vp->queued_packet++;
2162 : }
2163 :
2164 0 : vp->cur_tx++;
2165 0 : if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2166 0 : netif_stop_queue (dev);
2167 : } else { /* Clear previous interrupt enable. */
2168 : #if defined(tx_interrupt_mitigation)
2169 : /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2170 : * were selected, this would corrupt DN_COMPLETE. No?
2171 : */
2172 0 : prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2173 : #endif
2174 : }
2175 0 : iowrite16(DownUnstall, ioaddr + EL3_CMD);
2176 0 : spin_unlock_irqrestore(&vp->lock, flags);
2177 0 : dev->trans_start = jiffies;
2178 0 : return NETDEV_TX_OK;
2179 : }
2180 :
2181 : /* The interrupt handler does all of the Rx thread work and cleans up
2182 : after the Tx thread. */
2183 :
2184 : /*
2185 : * This is the ISR for the vortex series chips.
2186 : * full_bus_master_tx == 0 && full_bus_master_rx == 0
2187 : */
2188 :
2189 : static irqreturn_t
2190 : vortex_interrupt(int irq, void *dev_id)
2191 : {
2192 20 : struct net_device *dev = dev_id;
2193 40 : struct vortex_private *vp = netdev_priv(dev);
2194 10 : void __iomem *ioaddr;
2195 10 : int status;
2196 20 : int work_done = max_interrupt_work;
2197 20 : int handled = 0;
2198 10 :
2199 20 : ioaddr = vp->ioaddr;
2200 30 : spin_lock(&vp->lock);
2201 10 :
2202 30 : status = ioread16(ioaddr + EL3_STATUS);
2203 10 :
2204 10 : if (vortex_debug > 6)
2205 10 : pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2206 10 :
2207 20 : if ((status & IntLatch) == 0)
2208 10 : goto handler_exit; /* No interrupt: shared IRQs cause this */
2209 10 : handled = 1;
2210 :
2211 20 : if (status & IntReq) {
2212 20 : status |= vp->deferred;
2213 10 : vp->deferred = 0;
2214 : }
2215 :
2216 20 : if (status == 0xffff) /* h/w no longer present (hotplug)? */
2217 10 : goto handler_exit;
2218 :
2219 : if (vortex_debug > 4)
2220 : pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2221 10 : dev->name, status, ioread8(ioaddr + Timer));
2222 :
2223 : do {
2224 : if (vortex_debug > 5)
2225 : pr_debug("%s: In interrupt loop, status %4.4x.\n",
2226 : dev->name, status);
2227 20 : if (status & RxComplete)
2228 20 : vortex_rx(dev);
2229 :
2230 40 : if (status & TxAvailable) {
2231 : if (vortex_debug > 5)
2232 : pr_debug(" TX room bit was handled.\n");
2233 : /* There's room in the FIFO for a full-sized packet. */
2234 20 : iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2235 40 : netif_wake_queue (dev);
2236 : }
2237 :
2238 60 : if (status & DMADone) {
2239 90 : if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2240 30 : iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2241 420 : pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2242 10 : dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2243 30 : if (ioread16(ioaddr + TxFree) > 1536) {
2244 : /*
2245 : * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2246 : * insufficient FIFO room, the TxAvailable test will succeed and call
2247 : * netif_wake_queue()
2248 : */
2249 20 : netif_wake_queue(dev);
2250 : } else { /* Interrupt when FIFO has room for max-sized packet. */
2251 10 : iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2252 20 : netif_stop_queue(dev);
2253 : }
2254 : }
2255 : }
2256 : /* Check for all uncommon interrupts at once. */
2257 100 : if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2258 100 : if (status == 0xffff)
2259 50 : break;
2260 450 : vortex_error(dev, status);
2261 : }
2262 :
2263 180 : if (--work_done < 0) {
2264 60 : pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2265 : dev->name, status);
2266 : /* Disable all pending interrupts. */
2267 60 : do {
2268 20 : vp->deferred |= status;
2269 30 : iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2270 : ioaddr + EL3_CMD);
2271 20 : iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2272 40 : } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2273 : /* The timer will reenable interrupts. */
2274 30 : mod_timer(&vp->timer, jiffies + 1*HZ);
2275 10 : break;
2276 : }
2277 : /* Acknowledge the IRQ. */
2278 60 : iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2279 240 : } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2280 :
2281 60 : if (vortex_debug > 4)
2282 : pr_debug("%s: exiting interrupt, status %4.4x.\n",
2283 : dev->name, status);
2284 : handler_exit:
2285 220 : spin_unlock(&vp->lock);
2286 80 : return IRQ_RETVAL(handled);
2287 : }
2288 :
2289 : /*
2290 : * This is the ISR for the boomerang series chips.
2291 : * full_bus_master_tx == 1 && full_bus_master_rx == 1
2292 : */
2293 :
2294 : static irqreturn_t
2295 : boomerang_interrupt(int irq, void *dev_id)
2296 : {
2297 20 : struct net_device *dev = dev_id;
2298 40 : struct vortex_private *vp = netdev_priv(dev);
2299 10 : void __iomem *ioaddr;
2300 10 : int status;
2301 20 : int work_done = max_interrupt_work;
2302 10 :
2303 20 : ioaddr = vp->ioaddr;
2304 10 :
2305 10 : /*
2306 10 : * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2307 10 : * and boomerang_start_xmit
2308 10 : */
2309 30 : spin_lock(&vp->lock);
2310 10 :
2311 30 : status = ioread16(ioaddr + EL3_STATUS);
2312 10 :
2313 10 : if (vortex_debug > 6)
2314 10 : pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2315 :
2316 20 : if ((status & IntLatch) == 0)
2317 10 : goto handler_exit; /* No interrupt: shared IRQs can cause this */
2318 :
2319 20 : if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2320 : if (vortex_debug > 1)
2321 : pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2322 10 : goto handler_exit;
2323 : }
2324 :
2325 20 : if (status & IntReq) {
2326 20 : status |= vp->deferred;
2327 10 : vp->deferred = 0;
2328 : }
2329 :
2330 : if (vortex_debug > 4)
2331 10 : pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2332 : dev->name, status, ioread8(ioaddr + Timer));
2333 : do {
2334 : if (vortex_debug > 5)
2335 : pr_debug("%s: In interrupt loop, status %4.4x.\n",
2336 : dev->name, status);
2337 20 : if (status & UpComplete) {
2338 10 : iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2339 : if (vortex_debug > 5)
2340 : pr_debug("boomerang_interrupt->boomerang_rx\n");
2341 40 : boomerang_rx(dev);
2342 : }
2343 :
2344 40 : if (status & DownComplete) {
2345 20 : unsigned int dirty_tx = vp->dirty_tx;
2346 :
2347 20 : iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2348 40 : while (vp->cur_tx - dirty_tx > 0) {
2349 20 : int entry = dirty_tx % TX_RING_SIZE;
2350 10 : #if 1 /* AKPM: the latter is faster, but cyclone-only */
2351 30 : if (ioread32(ioaddr + DownListPtr) ==
2352 : vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2353 10 : break; /* It still hasn't been processed. */
2354 10 : #else
2355 : if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2356 : break; /* It still hasn't been processed. */
2357 : #endif
2358 :
2359 20 : if (vp->tx_skbuff[entry]) {
2360 10 : struct sk_buff *skb = vp->tx_skbuff[entry];
2361 : #if DO_ZEROCOPY
2362 : int i;
2363 80 : for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2364 150 : pci_unmap_single(VORTEX_PCI(vp),
2365 20 : le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2366 : le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2367 : PCI_DMA_TODEVICE);
2368 : #else
2369 : pci_unmap_single(VORTEX_PCI(vp),
2370 : le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2371 : #endif
2372 10 : dev_kfree_skb_irq(skb);
2373 10 : vp->tx_skbuff[entry] = NULL;
2374 : } else {
2375 : pr_debug("boomerang_interrupt: no skb!\n");
2376 : }
2377 : /* dev->stats.tx_packets++; Counted below. */
2378 20 : dirty_tx++;
2379 20 : }
2380 10 : vp->dirty_tx = dirty_tx;
2381 20 : if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2382 : if (vortex_debug > 6)
2383 : pr_debug("boomerang_interrupt: wake queue\n");
2384 20 : netif_wake_queue (dev);
2385 : }
2386 : }
2387 :
2388 : /* Check for all uncommon interrupts at once. */
2389 80 : if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2390 360 : vortex_error(dev, status);
2391 :
2392 150 : if (--work_done < 0) {
2393 50 : pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2394 : dev->name, status);
2395 : /* Disable all pending interrupts. */
2396 50 : do {
2397 20 : vp->deferred |= status;
2398 30 : iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2399 : ioaddr + EL3_CMD);
2400 20 : iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2401 40 : } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2402 : /* The timer will reenable interrupts. */
2403 30 : mod_timer(&vp->timer, jiffies + 1*HZ);
2404 10 : break;
2405 : }
2406 : /* Acknowledge the IRQ. */
2407 50 : iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2408 150 : if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2409 50 : iowrite32(0x8000, vp->cb_fn_base + 4);
2410 :
2411 200 : } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2412 :
2413 50 : if (vortex_debug > 4)
2414 : pr_debug("%s: exiting interrupt, status %4.4x.\n",
2415 : dev->name, status);
2416 : handler_exit:
2417 190 : spin_unlock(&vp->lock);
2418 70 : return IRQ_HANDLED;
2419 : }
2420 :
2421 : static int vortex_rx(struct net_device *dev)
2422 : {
2423 760 : struct vortex_private *vp = netdev_priv(dev);
2424 380 : void __iomem *ioaddr = vp->ioaddr;
2425 190 : int i;
2426 190 : short rx_status;
2427 190 :
2428 190 : if (vortex_debug > 5)
2429 190 : pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2430 190 : ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2431 1140 : while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2432 760 : if (rx_status & 0x4000) { /* Error, update stats. */
2433 760 : unsigned char rx_error = ioread8(ioaddr + RxErrors);
2434 190 : if (vortex_debug > 2)
2435 190 : pr_debug(" Rx error: status %2.2x.\n", rx_error);
2436 380 : dev->stats.rx_errors++;
2437 760 : if (rx_error & 0x01) dev->stats.rx_over_errors++;
2438 760 : if (rx_error & 0x02) dev->stats.rx_length_errors++;
2439 760 : if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2440 760 : if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2441 760 : if (rx_error & 0x10) dev->stats.rx_length_errors++;
2442 190 : } else {
2443 190 : /* The packet length: up to 4.5K!. */
2444 380 : int pkt_len = rx_status & 0x1fff;
2445 190 : struct sk_buff *skb;
2446 :
2447 190 : skb = dev_alloc_skb(pkt_len + 5);
2448 : if (vortex_debug > 4)
2449 : pr_debug("Receiving packet size %d status %4.4x.\n",
2450 : pkt_len, rx_status);
2451 380 : if (skb != NULL) {
2452 380 : skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2453 : /* 'skb_put()' points to the start of sk_buff data area. */
2454 950 : if (vp->bus_master &&
2455 : ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2456 3040 : dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2457 : pkt_len, PCI_DMA_FROMDEVICE);
2458 190 : iowrite32(dma, ioaddr + Wn7_MasterAddr);
2459 380 : iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2460 190 : iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2461 760 : while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2462 190 : ;
2463 3040 : pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2464 : } else {
2465 760 : ioread32_rep(ioaddr + RX_FIFO,
2466 : skb_put(skb, pkt_len),
2467 : (pkt_len + 3) >> 2);
2468 : }
2469 380 : iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2470 380 : skb->protocol = eth_type_trans(skb, dev);
2471 380 : netif_rx(skb);
2472 380 : dev->stats.rx_packets++;
2473 : /* Wait a limited time to go to next packet. */
2474 1330 : for (i = 200; i >= 0; i--)
2475 950 : if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2476 380 : break;
2477 190 : continue;
2478 380 : } else if (vortex_debug > 0)
2479 190 : pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2480 190 : dev->name, pkt_len);
2481 190 : dev->stats.rx_dropped++;
2482 : }
2483 570 : issue_and_wait(dev, RxDiscard);
2484 : }
2485 190 :
2486 190 : return 0;
2487 : }
2488 :
2489 : static int
2490 : boomerang_rx(struct net_device *dev)
2491 : {
2492 40 : struct vortex_private *vp = netdev_priv(dev);
2493 30 : int entry = vp->cur_rx % RX_RING_SIZE;
2494 20 : void __iomem *ioaddr = vp->ioaddr;
2495 10 : int rx_status;
2496 20 : int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2497 10 :
2498 10 : if (vortex_debug > 5)
2499 10 : pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2500 10 :
2501 60 : while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2502 50 : if (--rx_work_limit < 0)
2503 30 : break;
2504 30 : if (rx_status & RxDError) { /* Error, update stats. */
2505 20 : unsigned char rx_error = rx_status >> 16;
2506 10 : if (vortex_debug > 2)
2507 20 : pr_debug(" Rx error: status %2.2x.\n", rx_error);
2508 20 : dev->stats.rx_errors++;
2509 40 : if (rx_error & 0x01) dev->stats.rx_over_errors++;
2510 40 : if (rx_error & 0x02) dev->stats.rx_length_errors++;
2511 40 : if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2512 40 : if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2513 40 : if (rx_error & 0x10) dev->stats.rx_length_errors++;
2514 10 : } else {
2515 10 : /* The packet length: up to 4.5K!. */
2516 20 : int pkt_len = rx_status & 0x1fff;
2517 10 : struct sk_buff *skb;
2518 30 : dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2519 :
2520 : if (vortex_debug > 4)
2521 : pr_debug("Receiving packet size %d status %4.4x.\n",
2522 : pkt_len, rx_status);
2523 :
2524 : /* Check if the packet is long enough to just accept without
2525 : copying to a properly sized skbuff. */
2526 60 : if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
2527 20 : skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2528 140 : pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2529 10 : /* 'skb_put()' points to the start of sk_buff data area. */
2530 30 : memcpy(skb_put(skb, pkt_len),
2531 : vp->rx_skbuff[entry]->data,
2532 : pkt_len);
2533 140 : pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2534 10 : vp->rx_copy++;
2535 : } else {
2536 : /* Pass up the skbuff already on the Rx ring. */
2537 10 : skb = vp->rx_skbuff[entry];
2538 10 : vp->rx_skbuff[entry] = NULL;
2539 10 : skb_put(skb, pkt_len);
2540 140 : pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2541 10 : vp->rx_nocopy++;
2542 : }
2543 20 : skb->protocol = eth_type_trans(skb, dev);
2544 : { /* Use hardware checksum info. */
2545 20 : int csum_bits = rx_status & 0xee000000;
2546 120 : if (csum_bits &&
2547 : (csum_bits == (IPChksumValid | TCPChksumValid) ||
2548 : csum_bits == (IPChksumValid | UDPChksumValid))) {
2549 20 : skb->ip_summed = CHECKSUM_UNNECESSARY;
2550 20 : vp->rx_csumhits++;
2551 : }
2552 : }
2553 20 : netif_rx(skb);
2554 20 : dev->stats.rx_packets++;
2555 : }
2556 90 : entry = (++vp->cur_rx) % RX_RING_SIZE;
2557 30 : }
2558 : /* Refill the Rx ring buffers. */
2559 50 : for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2560 10 : struct sk_buff *skb;
2561 50 : entry = vp->dirty_rx % RX_RING_SIZE;
2562 20 : if (vp->rx_skbuff[entry] == NULL) {
2563 30 : skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
2564 20 : if (skb == NULL) {
2565 10 : static unsigned long last_jif;
2566 20 : if (time_after(jiffies, last_jif + 10 * HZ)) {
2567 10 : pr_warning("%s: memory shortage\n", dev->name);
2568 10 : last_jif = jiffies;
2569 : }
2570 20 : if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2571 20 : mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2572 20 : break; /* Bad news! */
2573 : }
2574 :
2575 160 : vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2576 10 : vp->rx_skbuff[entry] = skb;
2577 : }
2578 20 : vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2579 20 : iowrite16(UpUnstall, ioaddr + EL3_CMD);
2580 : }
2581 30 : return 0;
2582 : }
2583 :
2584 : /*
2585 : * If we've hit a total OOM refilling the Rx ring we poll once a second
2586 : * for some memory. Otherwise there is no way to restart the rx process.
2587 : */
2588 : static void
2589 : rx_oom_timer(unsigned long arg)
2590 : {
2591 0 : struct net_device *dev = (struct net_device *)arg;
2592 0 : struct vortex_private *vp = netdev_priv(dev);
2593 0 :
2594 0 : spin_lock_irq(&vp->lock);
2595 0 : if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2596 0 : boomerang_rx(dev);
2597 : if (vortex_debug > 1) {
2598 : pr_debug("%s: rx_oom_timer %s\n", dev->name,
2599 : ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2600 : }
2601 0 : spin_unlock_irq(&vp->lock);
2602 0 : }
2603 :
2604 : static void
2605 : vortex_down(struct net_device *dev, int final_down)
2606 : {
2607 1456 : struct vortex_private *vp = netdev_priv(dev);
2608 728 : void __iomem *ioaddr = vp->ioaddr;
2609 364 :
2610 1092 : netif_stop_queue (dev);
2611 364 :
2612 1092 : del_timer_sync(&vp->rx_oom_timer);
2613 1092 : del_timer_sync(&vp->timer);
2614 :
2615 : /* Turn off statistics ASAP. We update dev->stats below. */
2616 364 : iowrite16(StatsDisable, ioaddr + EL3_CMD);
2617 :
2618 : /* Disable the receiver and transmitter. */
2619 364 : iowrite16(RxDisable, ioaddr + EL3_CMD);
2620 364 : iowrite16(TxDisable, ioaddr + EL3_CMD);
2621 :
2622 : /* Disable receiving 802.1q tagged frames */
2623 728 : set_8021q_mode(dev, 0);
2624 :
2625 1092 : if (dev->if_port == XCVR_10base2)
2626 : /* Turn off thinnet power. Green! */
2627 364 : iowrite16(StopCoax, ioaddr + EL3_CMD);
2628 :
2629 364 : iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2630 :
2631 728 : update_stats(ioaddr, dev);
2632 728 : if (vp->full_bus_master_rx)
2633 364 : iowrite32(0, ioaddr + UpListPtr);
2634 728 : if (vp->full_bus_master_tx)
2635 364 : iowrite32(0, ioaddr + DownListPtr);
2636 :
2637 4368 : if (final_down && VORTEX_PCI(vp)) {
2638 364 : vp->pm_state_valid = 1;
2639 4732 : pci_save_state(VORTEX_PCI(vp));
2640 1092 : acpi_set_WOL(dev);
2641 : }
2642 728 : }
2643 :
2644 : static int
2645 : vortex_close(struct net_device *dev)
2646 : {
2647 16 : struct vortex_private *vp = netdev_priv(dev);
2648 8 : void __iomem *ioaddr = vp->ioaddr;
2649 4 : int i;
2650 4 :
2651 20 : if (netif_device_present(dev))
2652 16 : vortex_down(dev, 1);
2653 4 :
2654 4 : if (vortex_debug > 1) {
2655 4 : pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2656 4 : dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2657 4 : pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2658 4 : " tx_queued %d Rx pre-checksummed %d.\n",
2659 4 : dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2660 4 : }
2661 :
2662 : #if DO_ZEROCOPY
2663 64 : if (vp->rx_csumhits &&
2664 : (vp->drv_flags & HAS_HWCKSM) == 0 &&
2665 : (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2666 8 : pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
2667 : }
2668 : #endif
2669 :
2670 16 : free_irq(dev->irq, dev);
2671 :
2672 8 : if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2673 24 : for (i = 0; i < RX_RING_SIZE; i++)
2674 20 : if (vp->rx_skbuff[i]) {
2675 64 : pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2676 : PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2677 4 : dev_kfree_skb(vp->rx_skbuff[i]);
2678 4 : vp->rx_skbuff[i] = NULL;
2679 : }
2680 : }
2681 16 : if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2682 32 : for (i = 0; i < TX_RING_SIZE; i++) {
2683 20 : if (vp->tx_skbuff[i]) {
2684 8 : struct sk_buff *skb = vp->tx_skbuff[i];
2685 : #if DO_ZEROCOPY
2686 : int k;
2687 :
2688 32 : for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2689 60 : pci_unmap_single(VORTEX_PCI(vp),
2690 8 : le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2691 : le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2692 : PCI_DMA_TODEVICE);
2693 : #else
2694 : pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2695 : #endif
2696 4 : dev_kfree_skb(skb);
2697 4 : vp->tx_skbuff[i] = NULL;
2698 : }
2699 : }
2700 : }
2701 :
2702 12 : return 0;
2703 : }
2704 :
2705 : static void
2706 : dump_tx_ring(struct net_device *dev)
2707 : {
2708 360 : if (vortex_debug > 0) {
2709 480 : struct vortex_private *vp = netdev_priv(dev);
2710 240 : void __iomem *ioaddr = vp->ioaddr;
2711 120 :
2712 360 : if (vp->full_bus_master_tx) {
2713 120 : int i;
2714 360 : int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2715 120 :
2716 240 : pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2717 : vp->full_bus_master_tx,
2718 : vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2719 : vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2720 360 : pr_err(" Transmit list %8.8x vs. %p.\n",
2721 : ioread32(ioaddr + DownListPtr),
2722 : &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2723 360 : issue_and_wait(dev, DownStall);
2724 600 : for (i = 0; i < TX_RING_SIZE; i++) {
2725 120 : unsigned int length;
2726 240 :
2727 : #if DO_ZEROCOPY
2728 120 : length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2729 : #else
2730 : length = le32_to_cpu(vp->tx_ring[i].length);
2731 : #endif
2732 120 : pr_err(" %d: @%p length %8.8x status %8.8x\n",
2733 : i, &vp->tx_ring[i], length,
2734 : le32_to_cpu(vp->tx_ring[i].status));
2735 : }
2736 240 : if (!stalled)
2737 120 : iowrite16(DownUnstall, ioaddr + EL3_CMD);
2738 : }
2739 : }
2740 360 : }
2741 :
2742 : static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2743 : {
2744 40 : struct vortex_private *vp = netdev_priv(dev);
2745 20 : void __iomem *ioaddr = vp->ioaddr;
2746 10 : unsigned long flags;
2747 10 :
2748 50 : if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2749 40 : spin_lock_irqsave (&vp->lock, flags);
2750 20 : update_stats(ioaddr, dev);
2751 20 : spin_unlock_irqrestore (&vp->lock, flags);
2752 : }
2753 20 : return &dev->stats;
2754 : }
2755 :
2756 : /* Update statistics.
2757 : Unlike with the EL3 we need not worry about interrupts changing
2758 : the window setting from underneath us, but we must still guard
2759 : against a race condition with a StatsUpdate interrupt updating the
2760 : table. This is done by checking that the ASM (!) code generated uses
2761 : atomic updates with '+='.
2762 : */
2763 : static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2764 : {
2765 2616 : struct vortex_private *vp = netdev_priv(dev);
2766 1962 : int old_window = ioread16(ioaddr + EL3_CMD);
2767 654 :
2768 1962 : if (old_window == 0xffff) /* Chip suspended or ejected. */
2769 1308 : return;
2770 654 : /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2771 654 : /* Switch to the stats window, and read everything. */
2772 1308 : EL3WINDOW(6);
2773 1962 : dev->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2774 1962 : dev->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
2775 1962 : dev->stats.tx_window_errors += ioread8(ioaddr + 4);
2776 1962 : dev->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2777 1962 : dev->stats.tx_packets += ioread8(ioaddr + 6);
2778 1962 : dev->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2779 1308 : /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
2780 654 : /* Don't bother with register 9, an extension of registers 6&7.
2781 654 : If we do use the 6&7 values the atomic update assumption above
2782 654 : is invalid. */
2783 1308 : dev->stats.rx_bytes += ioread16(ioaddr + 10);
2784 1308 : dev->stats.tx_bytes += ioread16(ioaddr + 12);
2785 : /* Extra stats for get_ethtool_stats() */
2786 1308 : vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
2787 1308 : vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
2788 1308 : vp->xstats.tx_deferred += ioread8(ioaddr + 8);
2789 654 : EL3WINDOW(4);
2790 1308 : vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
2791 :
2792 654 : dev->stats.collisions = vp->xstats.tx_multiple_collisions
2793 : + vp->xstats.tx_single_collisions
2794 : + vp->xstats.tx_max_collisions;
2795 :
2796 : {
2797 1308 : u8 up = ioread8(ioaddr + 13);
2798 654 : dev->stats.rx_bytes += (up & 0x0f) << 16;
2799 654 : dev->stats.tx_bytes += (up & 0xf0) << 12;
2800 : }
2801 :
2802 654 : EL3WINDOW(old_window >> 13);
2803 654 : return;
2804 : }
2805 :
2806 : static int vortex_nway_reset(struct net_device *dev)
2807 : {
2808 40 : struct vortex_private *vp = netdev_priv(dev);
2809 20 : void __iomem *ioaddr = vp->ioaddr;
2810 10 : unsigned long flags;
2811 10 : int rc;
2812 10 :
2813 40 : spin_lock_irqsave(&vp->lock, flags);
2814 10 : EL3WINDOW(4);
2815 10 : rc = mii_nway_restart(&vp->mii);
2816 20 : spin_unlock_irqrestore(&vp->lock, flags);
2817 10 : return rc;
2818 : }
2819 :
2820 : static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2821 : {
2822 40 : struct vortex_private *vp = netdev_priv(dev);
2823 20 : void __iomem *ioaddr = vp->ioaddr;
2824 10 : unsigned long flags;
2825 10 : int rc;
2826 10 :
2827 40 : spin_lock_irqsave(&vp->lock, flags);
2828 10 : EL3WINDOW(4);
2829 10 : rc = mii_ethtool_gset(&vp->mii, cmd);
2830 20 : spin_unlock_irqrestore(&vp->lock, flags);
2831 10 : return rc;
2832 : }
2833 :
2834 : static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2835 : {
2836 40 : struct vortex_private *vp = netdev_priv(dev);
2837 20 : void __iomem *ioaddr = vp->ioaddr;
2838 10 : unsigned long flags;
2839 10 : int rc;
2840 10 :
2841 40 : spin_lock_irqsave(&vp->lock, flags);
2842 10 : EL3WINDOW(4);
2843 10 : rc = mii_ethtool_sset(&vp->mii, cmd);
2844 20 : spin_unlock_irqrestore(&vp->lock, flags);
2845 10 : return rc;
2846 : }
2847 :
2848 : static u32 vortex_get_msglevel(struct net_device *dev)
2849 : {
2850 10 : return vortex_debug;
2851 : }
2852 :
2853 : static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2854 : {
2855 10 : vortex_debug = dbg;
2856 10 : }
2857 :
2858 : static int vortex_get_sset_count(struct net_device *dev, int sset)
2859 : {
2860 : switch (sset) {
2861 30 : case ETH_SS_STATS:
2862 10 : return VORTEX_NUM_STATS;
2863 20 : default:
2864 20 : return -EOPNOTSUPP;
2865 : }
2866 : }
2867 :
2868 : static void vortex_get_ethtool_stats(struct net_device *dev,
2869 : struct ethtool_stats *stats, u64 *data)
2870 : {
2871 40 : struct vortex_private *vp = netdev_priv(dev);
2872 20 : void __iomem *ioaddr = vp->ioaddr;
2873 10 : unsigned long flags;
2874 10 :
2875 40 : spin_lock_irqsave(&vp->lock, flags);
2876 20 : update_stats(ioaddr, dev);
2877 20 : spin_unlock_irqrestore(&vp->lock, flags);
2878 :
2879 10 : data[0] = vp->xstats.tx_deferred;
2880 10 : data[1] = vp->xstats.tx_max_collisions;
2881 10 : data[2] = vp->xstats.tx_multiple_collisions;
2882 10 : data[3] = vp->xstats.tx_single_collisions;
2883 10 : data[4] = vp->xstats.rx_bad_ssd;
2884 10 : }
2885 :
2886 :
2887 : static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2888 : {
2889 10 : switch (stringset) {
2890 40 : case ETH_SS_STATS:
2891 10 : memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
2892 10 : break;
2893 20 : default:
2894 90 : WARN_ON(1);
2895 10 : break;
2896 : }
2897 : }
2898 20 :
2899 : static void vortex_get_drvinfo(struct net_device *dev,
2900 : struct ethtool_drvinfo *info)
2901 10 : {
2902 40 : struct vortex_private *vp = netdev_priv(dev);
2903 10 :
2904 20 : strcpy(info->driver, DRV_NAME);
2905 110 : if (VORTEX_PCI(vp)) {
2906 160 : strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2907 10 : } else {
2908 : if (VORTEX_EISA(vp))
2909 : strcpy(info->bus_info, dev_name(vp->gendev));
2910 : else
2911 30 : sprintf(info->bus_info, "EISA 0x%lx %d",
2912 : dev->base_addr, dev->irq);
2913 20 : }
2914 : }
2915 :
2916 1 : static const struct ethtool_ops vortex_ethtool_ops = {
2917 : .get_drvinfo = vortex_get_drvinfo,
2918 : .get_strings = vortex_get_strings,
2919 : .get_msglevel = vortex_get_msglevel,
2920 : .set_msglevel = vortex_set_msglevel,
2921 : .get_ethtool_stats = vortex_get_ethtool_stats,
2922 : .get_sset_count = vortex_get_sset_count,
2923 : .get_settings = vortex_get_settings,
2924 : .set_settings = vortex_set_settings,
2925 : .get_link = ethtool_op_get_link,
2926 : .nway_reset = vortex_nway_reset,
2927 : };
2928 :
2929 : #ifdef CONFIG_PCI
2930 : /*
2931 : * Must power the device up to do MDIO operations
2932 : */
2933 : static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2934 : {
2935 10 : int err;
2936 40 : struct vortex_private *vp = netdev_priv(dev);
2937 20 : void __iomem *ioaddr = vp->ioaddr;
2938 10 : unsigned long flags;
2939 20 : pci_power_t state = 0;
2940 10 :
2941 110 : if(VORTEX_PCI(vp))
2942 140 : state = VORTEX_PCI(vp)->current_state;
2943 10 :
2944 10 : /* The kernel core really should have pci_get_power_state() */
2945 10 :
2946 30 : if(state != 0)
2947 140 : pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2948 40 : spin_lock_irqsave(&vp->lock, flags);
2949 20 : EL3WINDOW(4);
2950 40 : err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2951 30 : spin_unlock_irqrestore(&vp->lock, flags);
2952 30 : if(state != 0)
2953 130 : pci_set_power_state(VORTEX_PCI(vp), state);
2954 :
2955 10 : return err;
2956 : }
2957 : #endif
2958 :
2959 :
2960 : /* Pre-Cyclone chips have no documented multicast filter, so the only
2961 : multicast setting is to receive all multicast frames. At least
2962 : the chip has a very clean way to set the mode, unlike many others. */
2963 : static void set_rx_mode(struct net_device *dev)
2964 : {
2965 1440 : struct vortex_private *vp = netdev_priv(dev);
2966 720 : void __iomem *ioaddr = vp->ioaddr;
2967 360 : int new_mode;
2968 360 :
2969 720 : if (dev->flags & IFF_PROMISC) {
2970 720 : if (vortex_debug > 3)
2971 360 : pr_notice("%s: Setting promiscuous mode.\n", dev->name);
2972 360 : new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2973 1800 : } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2974 360 : new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2975 : } else
2976 360 : new_mode = SetRxFilter | RxStation | RxBroadcast;
2977 :
2978 360 : iowrite16(new_mode, ioaddr + EL3_CMD);
2979 360 : }
2980 :
2981 : #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2982 : /* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2983 : Note that this must be done after each RxReset due to some backwards
2984 : compatibility logic in the Cyclone and Tornado ASICs */
2985 :
2986 : /* The Ethernet Type used for 802.1q tagged frames */
2987 : #define VLAN_ETHER_TYPE 0x8100
2988 :
2989 : static void set_8021q_mode(struct net_device *dev, int enable)
2990 : {
2991 : struct vortex_private *vp = netdev_priv(dev);
2992 : void __iomem *ioaddr = vp->ioaddr;
2993 : int old_window = ioread16(ioaddr + EL3_CMD);
2994 : int mac_ctrl;
2995 :
2996 : if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2997 : /* cyclone and tornado chipsets can recognize 802.1q
2998 : * tagged frames and treat them correctly */
2999 :
3000 : int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3001 : if (enable)
3002 : max_pkt_size += 4; /* 802.1Q VLAN tag */
3003 :
3004 : EL3WINDOW(3);
3005 : iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
3006 :
3007 : /* set VlanEtherType to let the hardware checksumming
3008 : treat tagged frames correctly */
3009 : EL3WINDOW(7);
3010 : iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
3011 : } else {
3012 : /* on older cards we have to enable large frames */
3013 :
3014 : vp->large_frames = dev->mtu > 1500 || enable;
3015 :
3016 : EL3WINDOW(3);
3017 : mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
3018 : if (vp->large_frames)
3019 : mac_ctrl |= 0x40;
3020 : else
3021 : mac_ctrl &= ~0x40;
3022 : iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
3023 : }
3024 :
3025 : EL3WINDOW(old_window);
3026 : }
3027 : #else
3028 :
3029 : static void set_8021q_mode(struct net_device *dev, int enable)
3030 : {
3031 584 : }
3032 :
3033 :
3034 : #endif
3035 :
3036 : /* MII transceiver control section.
3037 : Read and write the MII registers using software-generated serial
3038 : MDIO protocol. See the MII specifications or DP83840A data sheet
3039 : for details. */
3040 :
3041 : /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3042 : met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3043 : "overclocking" issues. */
3044 : #define mdio_delay() ioread32(mdio_addr)
3045 :
3046 : #define MDIO_SHIFT_CLK 0x01
3047 : #define MDIO_DIR_WRITE 0x04
3048 : #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3049 : #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3050 : #define MDIO_DATA_READ 0x02
3051 : #define MDIO_ENB_IN 0x00
3052 :
3053 : /* Generate the preamble required for initial synchronization and
3054 : a few older transceivers. */
3055 : static void mdio_sync(void __iomem *ioaddr, int bits)
3056 : {
3057 800 : void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3058 :
3059 : /* Establish sync by sending at least 32 logic ones. */
3060 1600 : while (-- bits >= 0) {
3061 800 : iowrite16(MDIO_DATA_WRITE1, mdio_addr);
3062 800 : mdio_delay();
3063 400 : iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
3064 400 : mdio_delay();
3065 : }
3066 400 : }
3067 400 :
3068 : static int mdio_read(struct net_device *dev, int phy_id, int location)
3069 : {
3070 396 : int i;
3071 1584 : struct vortex_private *vp = netdev_priv(dev);
3072 792 : void __iomem *ioaddr = vp->ioaddr;
3073 792 : int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3074 792 : unsigned int retval = 0;
3075 792 : void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3076 396 :
3077 1188 : if (mii_preamble_required)
3078 1188 : mdio_sync(ioaddr, 32);
3079 :
3080 : /* Shift the read command bits out. */
3081 2772 : for (i = 14; i >= 0; i--) {
3082 2772 : int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3083 1188 : iowrite16(dataval, mdio_addr);
3084 396 : mdio_delay();
3085 396 : iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3086 396 : mdio_delay();
3087 : }
3088 : /* Read the two transition, 16 data, and wire-idle bits. */
3089 1980 : for (i = 19; i > 0; i--) {
3090 792 : iowrite16(MDIO_ENB_IN, mdio_addr);
3091 1188 : mdio_delay();
3092 2772 : retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3093 396 : iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3094 396 : mdio_delay();
3095 : }
3096 2376 : return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3097 : }
3098 :
3099 : static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3100 : {
3101 8 : struct vortex_private *vp = netdev_priv(dev);
3102 4 : void __iomem *ioaddr = vp->ioaddr;
3103 4 : int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3104 4 : void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3105 2 : int i;
3106 2 :
3107 6 : if (mii_preamble_required)
3108 4 : mdio_sync(ioaddr, 32);
3109 :
3110 : /* Shift the command bits out. */
3111 14 : for (i = 31; i >= 0; i--) {
3112 14 : int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3113 6 : iowrite16(dataval, mdio_addr);
3114 2 : mdio_delay();
3115 2 : iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3116 2 : mdio_delay();
3117 : }
3118 : /* Leave the interface idle. */
3119 10 : for (i = 1; i >= 0; i--) {
3120 4 : iowrite16(MDIO_ENB_IN, mdio_addr);
3121 6 : mdio_delay();
3122 2 : iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3123 2 : mdio_delay();
3124 : }
3125 2 : return;
3126 : }
3127 :
3128 : /* ACPI: Advanced Configuration and Power Interface. */
3129 : /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3130 : static void acpi_set_WOL(struct net_device *dev)
3131 : {
3132 1488 : struct vortex_private *vp = netdev_priv(dev);
3133 744 : void __iomem *ioaddr = vp->ioaddr;
3134 372 :
3135 372 : device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3136 372 :
3137 1116 : if (vp->enable_wol) {
3138 372 : /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3139 744 : EL3WINDOW(7);
3140 744 : iowrite16(2, ioaddr + 0x0c);
3141 372 : /* The RxFilter must accept the WOL frames. */
3142 744 : iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3143 744 : iowrite16(RxEnable, ioaddr + EL3_CMD);
3144 372 :
3145 5952 : if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3146 5580 : pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3147 :
3148 372 : vp->enable_wol = 0;
3149 372 : return;
3150 : }
3151 :
3152 : /* Change the power state to D3; RxEnable doesn't take effect. */
3153 4836 : pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3154 : }
3155 372 : }
3156 :
3157 :
3158 : static void __devexit vortex_remove_one(struct pci_dev *pdev)
3159 : {
3160 : struct net_device *dev = pci_get_drvdata(pdev);
3161 : struct vortex_private *vp;
3162 :
3163 : if (!dev) {
3164 : pr_err("vortex_remove_one called for Compaq device!\n");
3165 : BUG();
3166 : }
3167 :
3168 : vp = netdev_priv(dev);
3169 :
3170 : if (vp->cb_fn_base)
3171 : pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3172 :
3173 : unregister_netdev(dev);
3174 :
3175 : if (VORTEX_PCI(vp)) {
3176 : pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3177 : if (vp->pm_state_valid)
3178 : pci_restore_state(VORTEX_PCI(vp));
3179 : pci_disable_device(VORTEX_PCI(vp));
3180 : }
3181 : /* Should really use issue_and_wait() here */
3182 : iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3183 : vp->ioaddr + EL3_CMD);
3184 :
3185 : pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
3186 :
3187 : pci_free_consistent(pdev,
3188 : sizeof(struct boom_rx_desc) * RX_RING_SIZE
3189 : + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3190 : vp->rx_ring,
3191 : vp->rx_ring_dma);
3192 : if (vp->must_free_region)
3193 : release_region(dev->base_addr, vp->io_size);
3194 : free_netdev(dev);
3195 : }
3196 :
3197 :
3198 1 : static struct pci_driver vortex_driver = {
3199 : .name = "3c59x",
3200 : .probe = vortex_init_one,
3201 : .remove = __devexit_p(vortex_remove_one),
3202 : .id_table = vortex_pci_tbl,
3203 : .driver.pm = VORTEX_PM_OPS,
3204 : };
3205 :
3206 :
3207 1 : static int vortex_have_pci;
3208 1 : static int vortex_have_eisa;
3209 :
3210 :
3211 : static int __init vortex_init(void)
3212 : {
3213 1 : int pci_rc, eisa_rc;
3214 1 :
3215 2 : pci_rc = pci_register_driver(&vortex_driver);
3216 3 : eisa_rc = vortex_eisa_init();
3217 :
3218 2 : if (pci_rc == 0)
3219 1 : vortex_have_pci = 1;
3220 2 : if (eisa_rc > 0)
3221 1 : vortex_have_eisa = 1;
3222 :
3223 6 : return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3224 : }
3225 :
3226 :
3227 : static void __exit vortex_eisa_cleanup(void)
3228 : {
3229 4 : struct vortex_private *vp;
3230 4 : void __iomem *ioaddr;
3231 4 :
3232 : #ifdef CONFIG_EISA
3233 : /* Take care of the EISA devices */
3234 : eisa_driver_unregister(&vortex_eisa_driver);
3235 : #endif
3236 :
3237 8 : if (compaq_net_device) {
3238 12 : vp = netdev_priv(compaq_net_device);
3239 4 : ioaddr = ioport_map(compaq_net_device->base_addr,
3240 : VORTEX_TOTAL_SIZE);
3241 :
3242 8 : unregister_netdev(compaq_net_device);
3243 4 : iowrite16(TotalReset, ioaddr + EL3_CMD);
3244 8 : release_region(compaq_net_device->base_addr,
3245 : VORTEX_TOTAL_SIZE);
3246 :
3247 8 : free_netdev(compaq_net_device);
3248 : }
3249 8 : }
3250 :
3251 :
3252 : static void __exit vortex_cleanup(void)
3253 : {
3254 4 : if (vortex_have_pci)
3255 4 : pci_unregister_driver(&vortex_driver);
3256 8 : if (vortex_have_eisa)
3257 12 : vortex_eisa_cleanup();
3258 6 : }
3259 :
3260 :
3261 : module_init(vortex_init);
3262 : module_exit(vortex_cleanup);
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