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#
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# Copyright 2015 ISP RAS (http://www.ispras.ru)
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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require_relative 'minimips_base'
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#
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# Description:
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#
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# This test template demonstrates how MicroTESK can simulate the execution
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# of a test program to predict the resulting state of a microprocessor
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# design under test. The described test program is a simple implemention of
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# the bubble sort algorithm. The algorithm in pseudocode (from Wikipedia):
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#
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# procedure bubbleSort( A : list of sortable items )
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# n = length(A)
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# repeat
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# swapped = false
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# for i = 1 to n-1 inclusive do
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# /* if this pair is out of order */
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# if A[i-1] > A[i] then
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# /* swap them and remember something changed */
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# swap( A[i-1], A[i] )
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# swapped = true
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# end if
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# end for
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# until not swapped
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# end procedure
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#
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class BubbleSortTemplate < MiniMipsBaseTemplate
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def pre
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super
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data {
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label :data
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word rand(1, 9), rand(1, 9), rand(1, 9), rand(1, 9)
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word rand(1, 9), rand(1, 9), rand(1, 9), rand(1, 9)
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word rand(1, 9), rand(1, 9), rand(1, 9), rand(1, 9)
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label :end
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space 1
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}
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end
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def run
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sequence {
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trace_data :data, :end
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la s0, :data
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la s1, :end
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add t0, zero, zero
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########################### Outer loop starts ##############################
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label :repeat
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addi t1, s0, 4
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########################### Inner loop starts ##############################
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label :for
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beq t1, s1, :exit_for
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addi t3, zero, 4
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sub t2, t1, t3
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lw t4, 0, t1
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lw t5, 0, t2
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slt t6, t4, t5
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beq t6, zero, :next
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nop
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swap t4, t5
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addi t0, zero, 1
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sw t4, 0, t1
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sw t5, 0, t2
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label :next
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j :for
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addi t1, t1, 4
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############################ Inner loop ends ###############################
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label :exit_for
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bne t0, zero, :repeat
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add t0, zero, zero
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############################ Outer loop ends ###############################
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trace_data :data, :end
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}.run
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end
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def swap(reg1, reg2)
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xor reg1, reg1, reg2
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xor reg2, reg1, reg2
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xor reg1, reg1, reg2
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end
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end
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