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Bug #9184 ยป blocks.v

Sergey Smolov, 08/01/2018 04:04 PM

 
`timescale 1ns/1ps

// Test module including several one-block processes.
// Is implemented to test HDL parser backend.
module blocks(clk, rst);
input clk;
input rst;

reg x;
reg y;
reg [1:0] z;

always @(posedge clk)
begin
x <= 1'b1;
z[0:0] <= 1'b0;
end /* posedge clk */

always @(posedge clk)
begin
z[1:1] <= 1'b1;
end /* posedge clk */

always @(posedge rst)
begin
y <= 1'b0;
end /* posedge rst */

always @(posedge clk)
begin
y <= 1'b1;
z[1:1] <= 1'b0;
end /* posedge clk */

endmodule /* blocks */
    (1-1/1)