Bug #9184 ยป blocks.v
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`timescale 1ns/1ps |
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// Test module including several one-block processes.
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// Is implemented to test HDL parser backend.
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module blocks(clk, rst); |
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input clk; |
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input rst; |
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reg x; |
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reg y; |
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reg [1:0] z; |
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always @(posedge clk) |
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begin
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x <= 1'b1; |
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z[0:0] <= 1'b0; |
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end /* posedge clk */ |
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always @(posedge clk) |
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begin
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z[1:1] <= 1'b1; |
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end /* posedge clk */ |
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always @(posedge rst) |
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begin
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y <= 1'b0; |
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end /* posedge rst */ |
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always @(posedge clk) |
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begin
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y <= 1'b1; |
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z[1:1] <= 1'b0; |
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end /* posedge clk */ |
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endmodule /* blocks */ |