Project

General

Profile

Bug #9184 ยป blocks.v

Sergey Smolov, 08/01/2018 04:04 PM

 
1
`timescale 1ns/1ps
2

    
3
// Test module including several one-block processes.
4
// Is implemented to test HDL parser backend.
5
module blocks(clk, rst);
6
    input      clk;
7
    input      rst;
8

    
9
    reg        x;
10
    reg        y;
11
    reg  [1:0] z;
12

    
13
always @(posedge clk)
14
begin
15
    x <= 1'b1;
16
    z[0:0] <= 1'b0;
17
end /* posedge clk */
18

    
19
always @(posedge clk)
20
begin
21
    z[1:1] <= 1'b1;
22
end /* posedge clk */
23

    
24
always @(posedge rst)
25
begin
26
    y <= 1'b0;
27
end /* posedge rst */
28

    
29
always @(posedge clk)
30
begin
31
    y <= 1'b1;
32
    z[1:1] <= 1'b0;
33
end /* posedge clk */
34

    
35
endmodule /* blocks */
    (1-1/1)