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Bug #7423 ยป rnd_fsm.vhd

Sergey Smolov, 07/26/2016 12:15 PM

 
ENTITY rnd_fsm IS
PORT( X : IN bit;
Y : OUT bit;
clock : IN bit );
END rnd_fsm;

ARCHITECTURE blif OF rnd_fsm IS
SIGNAL Z1 : bit := 'X'; -- latch
SIGNAL Z2 : bit := 'X'; -- latch
SIGNAL N6 : bit;
SIGNAL N11 : bit;

BEGIN

PROCESS ( X, N6, Z1, Z2, N11)
VARIABLE N9 : bit;
BEGIN
N11 <= NOT N6;
N9 := NOT X;
N6 <= N9 AND Z2;
N11 <= NOT N6;
Y <= N9 AND Z1;
END PROCESS;

PROCESS (clock)
BEGIN
if (clock'event AND clock = '1') then
Z1 <= N6;
Z2 <= N11;
end if;
END PROCESS;

END blif;
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