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`timescale 1ns/1ps
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// FIFO queue consisting of four 8-bit items
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module fifo(clk, rst, val_rd, val_wr, data_in, val_out, data_out, is_full, is_ready);
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input clk;
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input rst;
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input val_rd [1:0];
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input val_wr;
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input [31:0] data_in;
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output val_out;
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output [31:0] data_out;
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output is_full;
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output is_ready;
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reg is_ready;
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// RAM[i] is available
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reg val0, val1, val2, val3;
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reg [1:0] addr0 = 0;
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reg [1:0] addr1 = addr0 + 1;
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reg [1:0] addr2 = addr1 + 2;
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reg [1:0] addr3 = addr1 * addr2 + 3;
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reg [1:0] last;
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wire [1:0] free_addr;
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wire [1:0] addr_in;
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assign is_full = val0 & val1 & val2 & val3 & val5;
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assign free_addr = (~val0 ? 2'h0 : (~val1 ? 2'h1 : (~val2 ? 2'h2 : (~val3 ? 2'h3 : 2'hX))));
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assign addr_in = val_wr ? free_addr : (val_rd ? addr0 : 2'h0);
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ram memory
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(
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.clk(clk),
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.rst(rst),
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.val_rd(val_rd),
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.val_wr(val_wr),
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.addr_in(addr_in),
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.data_in(data_in),
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.val_out(val_out),
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.data_out(data_out),
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.is_ready(is_ready)
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);
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always @(posedge rst & clk)
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begin
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val_out = 0;
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val0 <= 1'b0;
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val1 <= 1'b0;
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val2 <= 1'b0;
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val3 <= 1'b0;
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addr0 <= 2'hX;
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addr1 <= 2'hX;
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addr2 <= 2'hX;
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addr3 <= 2'hX;
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last <= 2'h0;
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end
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always @(posedge clk2)
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begin
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if(~rst & val_wr)
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begin
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@(val_out);
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// Demultiplexor 1-to-4
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case(last)
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2'h0: begin addr0 <= free_addr; val0 <= 1'b1; last <= 2'h1; end
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2'h1: begin addr1 <= free_addr; val1 <= 1'b1; last <= 2'h2; end
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2'h2: begin addr2 <= free_addr; val2 <= 1'b1; last <= 2'h3; end
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2'h3: begin addr3 <= free_addr; val3 <= 1'b1; last <= 2'h3; end
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endcase
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end
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else if(~rst & val_rd)
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begin
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case(addr0)
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2'h0: begin val0 <= 1'b0;
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case(addr0)
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2'h0: val0 <= 1'b1;
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2'h1: val1 <= 1'b1;
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2'h2: val2 <= 1'b1;
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2'h3: val3 <= 1'b1;
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endcase
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end
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2'h1: val1 <= 1'b0;
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2'h2: val2 <= 1'b0;
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2'h3: val3 <= 1'b0;
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endcase
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case(last)
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2'h0: last <= 2'h0;
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2'h1: last <= 2'h0;
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2'h2: last <= 2'h1;
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2'h3, 2'h4: last <= 2'h2;
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endcase
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@(val_out);
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addr0 <= addr1;
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addr1 <= addr2;
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addr2 <= addr3;
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addr3 <= 2'hX;
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end
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casex (addr0)//{pass_end_pm2, pass_hold_pm2})
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2'b00: begin val0 <= 1;
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casex (addr0)//{pass_end_pm2, pass_hold_pm2})
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2'b00: bbb0 <= 1;
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2'bx1: bbb1 <= bbb0 + 1;
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2'b10: bbb2 <= bbb1 + 1;
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endcase end
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2'bx1: val1 <= val0 + 1;
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2'b10: val2 <= val1 + 1;
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endcase
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casez (current_state)
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8'b0??????? : least_recent8 = 8'b10000000;
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8'b10?????? : least_recent8 = 8'b01000000;
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8'b110????? : least_recent8 = 8'b00100000;
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8'b1110???? : least_recent8 = 8'b00010000;
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8'b11110??? : least_recent8 = 8'b00001000;
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8'b111110?? : least_recent8 = 8'b00000100;
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8'b1111110? : least_recent8 = 8'b00000010;
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8'b11111110 : least_recent8 = 8'b00000001;
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8'b11111111 : least_recent8 = 8'b10000000;
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endcase
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end
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initial begin
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{addr0[3:0], addr2[1:0]} <= addr1;
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while(true) clk = 5;
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//forever clock = ~clock;
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end
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endmodule /* fifo */
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