Bug #8283

"X <= (others => '0')" should be translated properly when X is bit vector

Added by Sergey Smolov 17 days ago. Updated 10 days ago.

Status:ResolvedStart date:07/10/2017
Priority:NormalDue date:
Assignee:Sergey Smolov% Done:


Category:VHDL\Verilog ParsersSpent time:-
Target version:0.2
Detected in build:master Published in build:


Translate "others"-using construction into bit vector when traget variable is of corresponding data type.


#1 Updated by Sergey Smolov 13 days ago

  • Status changed from New to Open

run the tool on pps_ei.vhd for testing

#2 Updated by Sergey Smolov 10 days ago

  • Status changed from Open to Resolved
  • % Done changed from 0 to 100

Fixed in ebfd1b4a

Also available in: Atom PDF