Bug #8283

"X <= (others => '0')" should be translated properly when X is bit vector

Added by Sergey Smolov 4 months ago. Updated 2 months ago.

Status:ClosedStart date:07/10/2017
Priority:NormalDue date:
Assignee:Sergey Smolov% Done:

100%

Category:VHDL\Verilog ParsersSpent time:-
Target version:0.2
Detected in build:master Published in build:1.0.1-beta-170912
Platform:

Description

Translate "others"-using construction into bit vector when traget variable is of corresponding data type.

History

#1 Updated by Sergey Smolov 4 months ago

  • Status changed from New to Open

run the tool on pps_ei.vhd for testing

#2 Updated by Sergey Smolov 4 months ago

  • Status changed from Open to Resolved
  • % Done changed from 0 to 100

Fixed in ebfd1b4a

#3 Updated by Sergey Smolov 3 months ago

  • Status changed from Resolved to Verified

#4 Updated by Sergey Smolov 2 months ago

  • Status changed from Verified to Closed
  • Published in build set to 1.0.1-beta-170912

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