Package ru.ispras.verilog.parser
Class VerilogDesignBackends
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- ru.ispras.verilog.parser.VerilogDesignBackend
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- ru.ispras.verilog.parser.VerilogDesignBackends
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public final class VerilogDesignBackends extends VerilogDesignBackend
VerilogDesignBackends
implements a composite design-level back-end.
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Constructor Summary
Constructors Constructor Description VerilogDesignBackends()
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description void
add(VerilogDesignBackend backend)
Registers the back-end.void
start(VerilogDesign design)
Processes the elaborated design.-
Methods inherited from class ru.ispras.verilog.parser.VerilogDesignBackend
getName
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Method Detail
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add
public void add(VerilogDesignBackend backend)
Registers the back-end.- Parameters:
backend
- the back-end to be registered.
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start
public void start(VerilogDesign design)
Processes the elaborated design.- Specified by:
start
in classVerilogDesignBackend
- Parameters:
design
- the elaborated design.
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