Package ru.ispras.verilog.parser.walker
Class VerilogNodeVisitor
- java.lang.Object
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- ru.ispras.verilog.parser.walker.VerilogNodeVisitor
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- All Implemented Interfaces:
NodeVisitor<VerilogNode.Tag>
- Direct Known Subclasses:
VerilogEmptyVisitor
,VerilogNodePrinter
public abstract class VerilogNodeVisitor extends java.lang.Object implements NodeVisitor<VerilogNode.Tag>
This class represents a base Verilog node visitor.
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Nested Class Summary
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Nested classes/interfaces inherited from interface ru.ispras.verilog.parser.core.NodeVisitor
NodeVisitor.Result
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Constructor Summary
Constructors Constructor Description VerilogNodeVisitor()
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Method Summary
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Method Detail
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onActivityBegin
public abstract NodeVisitor.Result onActivityBegin(VerilogActivity node)
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onActivityEnd
public abstract NodeVisitor.Result onActivityEnd(VerilogActivity node)
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onAssignBegin
public abstract NodeVisitor.Result onAssignBegin(VerilogAssign node)
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onAssignEnd
public abstract NodeVisitor.Result onAssignEnd(VerilogAssign node)
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onAssignStatementBegin
public abstract NodeVisitor.Result onAssignStatementBegin(VerilogAssignStatement node)
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onAssignStatementEnd
public abstract NodeVisitor.Result onAssignStatementEnd(VerilogAssignStatement node)
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onAssignmentBegin
public abstract NodeVisitor.Result onAssignmentBegin(VerilogAssignment node)
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onAssignmentEnd
public abstract NodeVisitor.Result onAssignmentEnd(VerilogAssignment node)
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onAttributeBegin
public abstract NodeVisitor.Result onAttributeBegin(VerilogAttribute node)
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onAttributeEnd
public abstract NodeVisitor.Result onAttributeEnd(VerilogAttribute node)
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onBlockGenerateBegin
public abstract NodeVisitor.Result onBlockGenerateBegin(VerilogBlockGenerate node)
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onBlockGenerateEnd
public abstract NodeVisitor.Result onBlockGenerateEnd(VerilogBlockGenerate node)
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onBlockStatementBegin
public abstract NodeVisitor.Result onBlockStatementBegin(VerilogBlockStatement node)
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onBlockStatementEnd
public abstract NodeVisitor.Result onBlockStatementEnd(VerilogBlockStatement node)
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onCaseGenerateBegin
public abstract NodeVisitor.Result onCaseGenerateBegin(VerilogCaseGenerate node)
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onCaseGenerateEnd
public abstract NodeVisitor.Result onCaseGenerateEnd(VerilogCaseGenerate node)
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onCaseGenerateItemBegin
public abstract NodeVisitor.Result onCaseGenerateItemBegin(VerilogCaseGenerateItem node)
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onCaseGenerateItemEnd
public abstract NodeVisitor.Result onCaseGenerateItemEnd(VerilogCaseGenerateItem node)
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onCaseStatementBegin
public abstract NodeVisitor.Result onCaseStatementBegin(VerilogCaseStatement node)
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onCaseStatementEnd
public abstract NodeVisitor.Result onCaseStatementEnd(VerilogCaseStatement node)
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onCaseStatementItemBegin
public abstract NodeVisitor.Result onCaseStatementItemBegin(VerilogCaseStatementItem node)
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onCaseStatementItemEnd
public abstract NodeVisitor.Result onCaseStatementItemEnd(VerilogCaseStatementItem node)
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onCodeBegin
public abstract NodeVisitor.Result onCodeBegin(VerilogCode node)
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onCodeEnd
public abstract NodeVisitor.Result onCodeEnd(VerilogCode node)
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onDeclarationBegin
public abstract NodeVisitor.Result onDeclarationBegin(VerilogDeclaration node)
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onDeclarationEnd
public abstract NodeVisitor.Result onDeclarationEnd(VerilogDeclaration node)
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onDefineParameterBegin
public abstract NodeVisitor.Result onDefineParameterBegin(VerilogDefineParameter node)
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onDefineParameterEnd
public abstract NodeVisitor.Result onDefineParameterEnd(VerilogDefineParameter node)
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onDelayedStatementBegin
public abstract NodeVisitor.Result onDelayedStatementBegin(VerilogDelayedStatement node)
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onDelayedStatementEnd
public abstract NodeVisitor.Result onDelayedStatementEnd(VerilogDelayedStatement node)
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onDisableStatementBegin
public abstract NodeVisitor.Result onDisableStatementBegin(VerilogDisableStatement node)
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onDisableStatementEnd
public abstract NodeVisitor.Result onDisableStatementEnd(VerilogDisableStatement node)
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onGenerateBegin
public abstract NodeVisitor.Result onGenerateBegin(VerilogGenerate node)
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onGenerateEnd
public abstract NodeVisitor.Result onGenerateEnd(VerilogGenerate node)
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onIfGenerateBegin
public abstract NodeVisitor.Result onIfGenerateBegin(VerilogIfGenerate node)
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onIfGenerateEnd
public abstract NodeVisitor.Result onIfGenerateEnd(VerilogIfGenerate node)
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onIfGenerateBranchBegin
public abstract NodeVisitor.Result onIfGenerateBranchBegin(VerilogIfGenerateBranch node)
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onIfGenerateBranchEnd
public abstract NodeVisitor.Result onIfGenerateBranchEnd(VerilogIfGenerateBranch node)
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onIfStatementBegin
public abstract NodeVisitor.Result onIfStatementBegin(VerilogIfStatement node)
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onIfStatementEnd
public abstract NodeVisitor.Result onIfStatementEnd(VerilogIfStatement node)
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onIfStatementBranchBegin
public abstract NodeVisitor.Result onIfStatementBranchBegin(VerilogIfStatementBranch node)
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onIfStatementBranchEnd
public abstract NodeVisitor.Result onIfStatementBranchEnd(VerilogIfStatementBranch node)
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onInstantiationBegin
public abstract NodeVisitor.Result onInstantiationBegin(VerilogInstantiation node)
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onInstantiationEnd
public abstract NodeVisitor.Result onInstantiationEnd(VerilogInstantiation node)
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onLoopGenerateBegin
public abstract NodeVisitor.Result onLoopGenerateBegin(VerilogLoopGenerate node)
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onLoopGenerateEnd
public abstract NodeVisitor.Result onLoopGenerateEnd(VerilogLoopGenerate node)
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onLoopStatementBegin
public abstract NodeVisitor.Result onLoopStatementBegin(VerilogLoopStatement node)
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onLoopStatementEnd
public abstract NodeVisitor.Result onLoopStatementEnd(VerilogLoopStatement node)
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onModuleBegin
public abstract NodeVisitor.Result onModuleBegin(VerilogModule node)
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onModuleEnd
public abstract NodeVisitor.Result onModuleEnd(VerilogModule node)
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onNullStatementBegin
public abstract NodeVisitor.Result onNullStatementBegin(VerilogNullStatement node)
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onNullStatementEnd
public abstract NodeVisitor.Result onNullStatementEnd(VerilogNullStatement node)
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onPathDeclarationBegin
public abstract NodeVisitor.Result onPathDeclarationBegin(VerilogPathDeclaration node)
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onPathDeclarationEnd
public abstract NodeVisitor.Result onPathDeclarationEnd(VerilogPathDeclaration node)
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onPortBegin
public abstract NodeVisitor.Result onPortBegin(VerilogPort node)
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onPortEnd
public abstract NodeVisitor.Result onPortEnd(VerilogPort node)
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onPortConnectionBegin
public abstract NodeVisitor.Result onPortConnectionBegin(VerilogPortConnection node)
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onPortConnectionEnd
public abstract NodeVisitor.Result onPortConnectionEnd(VerilogPortConnection node)
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onProcedureBegin
public abstract NodeVisitor.Result onProcedureBegin(VerilogProcedure node)
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onProcedureEnd
public abstract NodeVisitor.Result onProcedureEnd(VerilogProcedure node)
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onPulseStyleBegin
public abstract NodeVisitor.Result onPulseStyleBegin(VerilogPulseStyle node)
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onPulseStyleEnd
public abstract NodeVisitor.Result onPulseStyleEnd(VerilogPulseStyle node)
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onShowCancelledBegin
public abstract NodeVisitor.Result onShowCancelledBegin(VerilogShowCancelled node)
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onShowCancelledEnd
public abstract NodeVisitor.Result onShowCancelledEnd(VerilogShowCancelled node)
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onSpecifyBegin
public abstract NodeVisitor.Result onSpecifyBegin(VerilogSpecify node)
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onSpecifyEnd
public abstract NodeVisitor.Result onSpecifyEnd(VerilogSpecify node)
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onTableBegin
public abstract NodeVisitor.Result onTableBegin(VerilogTable node)
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onTableEnd
public abstract NodeVisitor.Result onTableEnd(VerilogTable node)
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onTableEntryBegin
public abstract NodeVisitor.Result onTableEntryBegin(VerilogTableEntry node)
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onTableEntryEnd
public abstract NodeVisitor.Result onTableEntryEnd(VerilogTableEntry node)
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onTaskStatementBegin
public abstract NodeVisitor.Result onTaskStatementBegin(VerilogTaskStatement node)
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onTaskStatementEnd
public abstract NodeVisitor.Result onTaskStatementEnd(VerilogTaskStatement node)
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onTriggerStatementBegin
public abstract NodeVisitor.Result onTriggerStatementBegin(VerilogTriggerStatement node)
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onTriggerStatementEnd
public abstract NodeVisitor.Result onTriggerStatementEnd(VerilogTriggerStatement node)
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onWaitStatementBegin
public abstract NodeVisitor.Result onWaitStatementBegin(VerilogWaitStatement node)
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onWaitStatementEnd
public abstract NodeVisitor.Result onWaitStatementEnd(VerilogWaitStatement node)
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onSequenceDeclarationBegin
public abstract NodeVisitor.Result onSequenceDeclarationBegin(SvaSequenceDeclaration node)
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onSequenceDeclarationEnd
public abstract NodeVisitor.Result onSequenceDeclarationEnd(SvaSequenceDeclaration node)
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onPropertyDeclarationBegin
public abstract NodeVisitor.Result onPropertyDeclarationBegin(SvaPropertyDeclaration node)
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onPropertyDeclarationEnd
public abstract NodeVisitor.Result onPropertyDeclarationEnd(SvaPropertyDeclaration node)
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onAssertionStatementBegin
public abstract NodeVisitor.Result onAssertionStatementBegin(SvaAssertionStatement node)
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onAssertionStatementEnd
public abstract NodeVisitor.Result onAssertionStatementEnd(SvaAssertionStatement node)
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onSvaInstanceBegin
public abstract NodeVisitor.Result onSvaInstanceBegin(SvaInstantiation node)
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onSvaInstanceEnd
public abstract NodeVisitor.Result onSvaInstanceEnd(SvaInstantiation node)
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onBegin
public final NodeVisitor.Result onBegin(AbstractNode<VerilogNode.Tag> node)
Is called before traversing the child nodes.- Specified by:
onBegin
in interfaceNodeVisitor<VerilogNode.Tag>
- Parameters:
node
- the visiting node.- Returns:
- the visiting result.
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onEnd
public final NodeVisitor.Result onEnd(AbstractNode<VerilogNode.Tag> node)
Is called when all of the child nodes have been traversed.- Specified by:
onEnd
in interfaceNodeVisitor<VerilogNode.Tag>
- Parameters:
node
- the visiting node.- Returns:
- the visiting result.
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