Class VerilogTransformer
- java.lang.Object
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- ru.ispras.verilog.parser.walker.VerilogNodeVisitor
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- ru.ispras.verilog.parser.walker.VerilogEmptyVisitor
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- ru.ispras.verilog.parser.transformer.VerilogTransformer
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- All Implemented Interfaces:
NodeVisitor<VerilogNode.Tag>
- Direct Known Subclasses:
VerilogCallCollector
,VerilogTransformerBvconcat
,VerilogTransformerComposite
,VerilogTransformerOperation
,VerilogTransformerSvaInstance
,VerilogTransformerSvaStatement
,VerilogTransformerVariableRename
,VerilogTransformerVariableSubstitute
public abstract class VerilogTransformer extends VerilogEmptyVisitor
VerilogTransformer
implements an engine that transforms expressions.
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Nested Class Summary
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Nested classes/interfaces inherited from interface ru.ispras.verilog.parser.core.NodeVisitor
NodeVisitor.Result
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Constructor Summary
Constructors Constructor Description VerilogTransformer()
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Method Summary
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Methods inherited from class ru.ispras.verilog.parser.walker.VerilogEmptyVisitor
onActivityBegin, onActivityEnd, onAssertionStatementEnd, onAssignEnd, onAssignmentBegin, onAssignmentEnd, onAssignStatementEnd, onAttributeBegin, onAttributeEnd, onBlockGenerateBegin, onBlockGenerateEnd, onBlockStatementBegin, onBlockStatementEnd, onCaseGenerateBegin, onCaseGenerateEnd, onCaseGenerateItemBegin, onCaseGenerateItemEnd, onCaseStatementEnd, onCaseStatementItemEnd, onCodeBegin, onCodeEnd, onDeclarationEnd, onDefineParameterBegin, onDefineParameterEnd, onDelayedStatementEnd, onDisableStatementBegin, onDisableStatementEnd, onGenerateBegin, onGenerateEnd, onIfGenerateBegin, onIfGenerateBranchBegin, onIfGenerateBranchEnd, onIfGenerateEnd, onIfStatementBranchBegin, onIfStatementBranchEnd, onIfStatementEnd, onInstantiationBegin, onInstantiationEnd, onLoopGenerateBegin, onLoopGenerateEnd, onLoopStatementEnd, onModuleBegin, onModuleEnd, onNullStatementBegin, onNullStatementEnd, onPathDeclarationBegin, onPathDeclarationEnd, onPortBegin, onPortConnectionBegin, onPortConnectionEnd, onPortEnd, onProcedureBegin, onProcedureEnd, onPropertyDeclarationBegin, onPropertyDeclarationEnd, onPulseStyleBegin, onPulseStyleEnd, onSequenceDeclarationBegin, onSequenceDeclarationEnd, onShowCancelledBegin, onShowCancelledEnd, onSpecifyBegin, onSpecifyEnd, onSvaInstanceEnd, onTableBegin, onTableEnd, onTableEntryBegin, onTableEntryEnd, onTaskStatementEnd, onTriggerStatementBegin, onTriggerStatementEnd, onWaitStatementEnd
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Methods inherited from class ru.ispras.verilog.parser.walker.VerilogNodeVisitor
onBegin, onEnd
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Method Detail
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run
public final void run(VerilogNode node)
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onDeclarationBegin
public NodeVisitor.Result onDeclarationBegin(VerilogDeclaration node)
- Overrides:
onDeclarationBegin
in classVerilogEmptyVisitor
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onAssignBegin
public NodeVisitor.Result onAssignBegin(VerilogAssign node)
- Overrides:
onAssignBegin
in classVerilogEmptyVisitor
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onAssignStatementBegin
public NodeVisitor.Result onAssignStatementBegin(VerilogAssignStatement node)
- Overrides:
onAssignStatementBegin
in classVerilogEmptyVisitor
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onCaseStatementBegin
public NodeVisitor.Result onCaseStatementBegin(VerilogCaseStatement node)
- Overrides:
onCaseStatementBegin
in classVerilogEmptyVisitor
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onCaseStatementItemBegin
public NodeVisitor.Result onCaseStatementItemBegin(VerilogCaseStatementItem node)
- Overrides:
onCaseStatementItemBegin
in classVerilogEmptyVisitor
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onDelayedStatementBegin
public NodeVisitor.Result onDelayedStatementBegin(VerilogDelayedStatement node)
- Overrides:
onDelayedStatementBegin
in classVerilogEmptyVisitor
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onIfStatementBegin
public NodeVisitor.Result onIfStatementBegin(VerilogIfStatement node)
- Overrides:
onIfStatementBegin
in classVerilogEmptyVisitor
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onLoopStatementBegin
public NodeVisitor.Result onLoopStatementBegin(VerilogLoopStatement node)
- Overrides:
onLoopStatementBegin
in classVerilogEmptyVisitor
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onTaskStatementBegin
public NodeVisitor.Result onTaskStatementBegin(VerilogTaskStatement node)
- Overrides:
onTaskStatementBegin
in classVerilogEmptyVisitor
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onWaitStatementBegin
public NodeVisitor.Result onWaitStatementBegin(VerilogWaitStatement node)
- Overrides:
onWaitStatementBegin
in classVerilogEmptyVisitor
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onAssertionStatementBegin
public NodeVisitor.Result onAssertionStatementBegin(SvaAssertionStatement node)
- Overrides:
onAssertionStatementBegin
in classVerilogEmptyVisitor
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onSvaInstanceBegin
public NodeVisitor.Result onSvaInstanceBegin(SvaInstantiation node)
- Overrides:
onSvaInstanceBegin
in classVerilogEmptyVisitor
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transform
public abstract ru.ispras.fortress.expression.Node transform(ru.ispras.fortress.expression.Node node)
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