Package ru.ispras.verilog.parser.model
Class VerilogIfGenerateBranch
- java.lang.Object
-
- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
-
- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
-
- ru.ispras.verilog.parser.model.VerilogNode
-
- ru.ispras.verilog.parser.model.VerilogIfGenerateBranch
-
public final class VerilogIfGenerateBranch extends VerilogNode
VerilogIfGenerateBranch
represents if-then-else generate branches (then and else).
-
-
Nested Class Summary
Nested Classes Modifier and Type Class Description static class
VerilogIfGenerateBranch.Type
VerilogIfGenerateBranch.Type
contains the branch types.-
Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
-
Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
-
-
Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
-
Constructor Summary
Constructors Constructor Description VerilogIfGenerateBranch(VerilogIfGenerateBranch.Type type, VerilogBlockGenerate generate, VerilogNode parent)
Creates an if generate branch.VerilogIfGenerateBranch(VerilogIfGenerateBranch other, VerilogNode parent)
Creates a copy of the if generate branch.VerilogIfGenerateBranch(VerilogNode parent)
Creates an if generate branch.
-
Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description VerilogIfGenerateBranch
clone()
Clones the symbol table.VerilogExpression
getExpression()
Returns the condition associated with the branch.VerilogBlockGenerate
getGenerate()
Returns the branch body.VerilogIfGenerateBranch.Type
getType()
Returns the branch type (THEN
orELSE
).boolean
isElse()
Checks whether the branch isELSE
.boolean
isThen()
Checks whether the branch isTHEN
.void
setElse()
Sets the branch type toELSE
.void
setGenerate(VerilogBlockGenerate generate)
Sets the branch body.void
setThen()
Sets the branch type toTHEN
.void
setType(VerilogIfGenerateBranch.Type type)
Sets the branch type.-
Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
-
Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
-
Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
-
-
-
-
Field Detail
-
TAG
public static final VerilogNode.Tag TAG
-
TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
-
-
Constructor Detail
-
VerilogIfGenerateBranch
public VerilogIfGenerateBranch(VerilogNode parent)
Creates an if generate branch.- Parameters:
parent
- the node parent.
-
VerilogIfGenerateBranch
public VerilogIfGenerateBranch(VerilogIfGenerateBranch.Type type, VerilogBlockGenerate generate, VerilogNode parent)
Creates an if generate branch.- Parameters:
type
- the branch type.generate
- the branch body.parent
- the parent node.
-
VerilogIfGenerateBranch
public VerilogIfGenerateBranch(VerilogIfGenerateBranch other, VerilogNode parent)
Creates a copy of the if generate branch.- Parameters:
other
- the if generate branch to be copied.parent
- the parent node.
-
-
Method Detail
-
getType
public VerilogIfGenerateBranch.Type getType()
Returns the branch type (THEN
orELSE
).- Returns:
- the branch type.
-
setType
public void setType(VerilogIfGenerateBranch.Type type)
Sets the branch type.- Parameters:
type
- the branch type.
-
isThen
public boolean isThen()
Checks whether the branch isTHEN
.- Returns:
true
iff the branch isTHEN
.
-
isElse
public boolean isElse()
Checks whether the branch isELSE
.- Returns:
true
iff the branch isELSE
.
-
setThen
public void setThen()
Sets the branch type toTHEN
.
-
setElse
public void setElse()
Sets the branch type toELSE
.
-
getGenerate
public VerilogBlockGenerate getGenerate()
Returns the branch body.- Returns:
- the branch body.
-
setGenerate
public void setGenerate(VerilogBlockGenerate generate)
Sets the branch body.- Parameters:
generate
- the branch body.
-
getExpression
public VerilogExpression getExpression()
Returns the condition associated with the branch.- Returns:
- the branch condition.
-
clone
public VerilogIfGenerateBranch clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogNode
- Returns:
- a copy of the symbol table.
-
-