Class VerilogElaborator
- java.lang.Object
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- ru.ispras.verilog.parser.VerilogSyntaxBackend
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- ru.ispras.verilog.parser.elaborator.VerilogElaborator
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public final class VerilogElaborator extends VerilogSyntaxBackend
VerilogElaborator
implements a simple elaboration engine.[IEEE Std 1364-2005] 12.8 Elaboration Elaboration is the process that occurs between parsing and simulation. It binds modules to module instances, builds the model hierarchy, computes parameter values, resolves hierarchical names, establishes net connectivity, and prepares all of this for simulation. With the addition of generate constructs, the order in which these tasks occur becomes significant.
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Constructor Summary
Constructors Constructor Description VerilogElaborator(java.lang.String name)
Creates an elaboration engine.VerilogElaborator(java.lang.String name, java.lang.String moduleName)
Creates an elaboration engine.
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description VerilogDesign
getDesign()
Returns the elaborated design.java.lang.String
getModuleName()
Returns the name of the module to be elaborated.void
setModuleName(java.lang.String moduleName)
Sets the name of the module to be elaborated.void
start(VerilogNode rootNode)
Processes the abstract syntax tree (AST).-
Methods inherited from class ru.ispras.verilog.parser.VerilogSyntaxBackend
getName
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Constructor Detail
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VerilogElaborator
public VerilogElaborator(java.lang.String name)
Creates an elaboration engine.- Parameters:
name
- the back-end name.
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VerilogElaborator
public VerilogElaborator(java.lang.String name, java.lang.String moduleName)
Creates an elaboration engine.- Parameters:
name
- the back-end name.moduleName
- the name of the module to be elaborated.
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Method Detail
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getModuleName
public java.lang.String getModuleName()
Returns the name of the module to be elaborated.- Returns:
- the module name.
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setModuleName
public void setModuleName(java.lang.String moduleName)
Sets the name of the module to be elaborated.- Parameters:
moduleName
- the module name.
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getDesign
public VerilogDesign getDesign()
Returns the elaborated design.- Returns:
- the elaborated design.
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start
public void start(VerilogNode rootNode)
Description copied from class:VerilogSyntaxBackend
Processes the abstract syntax tree (AST).- Overrides:
start
in classVerilogSyntaxBackend
- Parameters:
rootNode
- the AST's root.
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