Package ru.ispras.verilog.parser
Class VerilogDesignBackend
- java.lang.Object
-
- ru.ispras.verilog.parser.VerilogDesignBackend
-
- Direct Known Subclasses:
AssignCheckerModule
,VerilogDesignBackends
,VerilogDesignPrinter
,VerilogTypeCaster
public abstract class VerilogDesignBackend extends java.lang.Object
VerilogDesignBackend
is a basic class for design-level back-ends.The
start
method should be override in a subclass.
-
-
Constructor Summary
Constructors Modifier Constructor Description protected
VerilogDesignBackend(java.lang.String name)
Creates a back-end.
-
Method Summary
All Methods Instance Methods Abstract Methods Concrete Methods Modifier and Type Method Description java.lang.String
getName()
Returns the name of the back-end.abstract void
start(VerilogDesign design)
Processes the elaborated design.
-
-
-
Method Detail
-
getName
public final java.lang.String getName()
Returns the name of the back-end.- Returns:
- the back-end name.
-
start
public abstract void start(VerilogDesign design)
Processes the elaborated design.- Parameters:
design
- the elaborated design.
-
-