Class VerilogStaticChecker
- java.lang.Object
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- ru.ispras.verilog.parser.walker.VerilogNodeVisitor
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- ru.ispras.verilog.parser.walker.VerilogEmptyVisitor
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- ru.ispras.verilog.parser.backends.syntax.checker.VerilogStaticChecker
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- All Implemented Interfaces:
NodeVisitor<VerilogNode.Tag>
public final class VerilogStaticChecker extends VerilogEmptyVisitor
VerilogStaticChecker
implements a Verilog static checker.
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Nested Class Summary
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Nested classes/interfaces inherited from interface ru.ispras.verilog.parser.core.NodeVisitor
NodeVisitor.Result
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Constructor Summary
Constructors Constructor Description VerilogStaticChecker()
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Method Summary
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Methods inherited from class ru.ispras.verilog.parser.walker.VerilogEmptyVisitor
onActivityBegin, onActivityEnd, onAssertionStatementEnd, onAssignEnd, onAssignmentBegin, onAssignmentEnd, onAssignStatementEnd, onAttributeBegin, onAttributeEnd, onBlockGenerateBegin, onBlockGenerateEnd, onBlockStatementEnd, onCaseGenerateEnd, onCaseGenerateItemBegin, onCaseGenerateItemEnd, onCaseStatementEnd, onCaseStatementItemBegin, onCaseStatementItemEnd, onDeclarationEnd, onDefineParameterEnd, onDelayedStatementEnd, onDisableStatementBegin, onDisableStatementEnd, onGenerateBegin, onGenerateEnd, onIfGenerateBranchBegin, onIfGenerateBranchEnd, onIfGenerateEnd, onIfStatementBranchBegin, onIfStatementBranchEnd, onIfStatementEnd, onInstantiationEnd, onLoopStatementEnd, onNullStatementBegin, onNullStatementEnd, onPathDeclarationBegin, onPathDeclarationEnd, onPortBegin, onPortConnectionEnd, onPortEnd, onProcedureBegin, onProcedureEnd, onPropertyDeclarationEnd, onPulseStyleBegin, onPulseStyleEnd, onSequenceDeclarationEnd, onShowCancelledBegin, onShowCancelledEnd, onSpecifyBegin, onSpecifyEnd, onSvaInstanceBegin, onSvaInstanceEnd, onTableBegin, onTableEnd, onTableEntryBegin, onTableEntryEnd, onTaskStatementEnd, onTriggerStatementBegin, onTriggerStatementEnd, onWaitStatementEnd
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Methods inherited from class ru.ispras.verilog.parser.walker.VerilogNodeVisitor
onBegin, onEnd
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Method Detail
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onAssignBegin
public NodeVisitor.Result onAssignBegin(VerilogAssign node)
- Overrides:
onAssignBegin
in classVerilogEmptyVisitor
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onAssignStatementBegin
public NodeVisitor.Result onAssignStatementBegin(VerilogAssignStatement node)
- Overrides:
onAssignStatementBegin
in classVerilogEmptyVisitor
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onBlockStatementBegin
public NodeVisitor.Result onBlockStatementBegin(VerilogBlockStatement node)
- Overrides:
onBlockStatementBegin
in classVerilogEmptyVisitor
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onCaseGenerateBegin
public NodeVisitor.Result onCaseGenerateBegin(VerilogCaseGenerate node)
- Overrides:
onCaseGenerateBegin
in classVerilogEmptyVisitor
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onCaseStatementBegin
public NodeVisitor.Result onCaseStatementBegin(VerilogCaseStatement node)
- Overrides:
onCaseStatementBegin
in classVerilogEmptyVisitor
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onCodeBegin
public NodeVisitor.Result onCodeBegin(VerilogCode node)
- Overrides:
onCodeBegin
in classVerilogEmptyVisitor
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onCodeEnd
public NodeVisitor.Result onCodeEnd(VerilogCode node)
- Overrides:
onCodeEnd
in classVerilogEmptyVisitor
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onDeclarationBegin
public NodeVisitor.Result onDeclarationBegin(VerilogDeclaration node)
- Overrides:
onDeclarationBegin
in classVerilogEmptyVisitor
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onDelayedStatementBegin
public NodeVisitor.Result onDelayedStatementBegin(VerilogDelayedStatement node)
- Overrides:
onDelayedStatementBegin
in classVerilogEmptyVisitor
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onIfGenerateBegin
public NodeVisitor.Result onIfGenerateBegin(VerilogIfGenerate node)
- Overrides:
onIfGenerateBegin
in classVerilogEmptyVisitor
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onInstantiationBegin
public NodeVisitor.Result onInstantiationBegin(VerilogInstantiation node)
- Overrides:
onInstantiationBegin
in classVerilogEmptyVisitor
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onIfStatementBegin
public NodeVisitor.Result onIfStatementBegin(VerilogIfStatement node)
- Overrides:
onIfStatementBegin
in classVerilogEmptyVisitor
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onLoopStatementBegin
public NodeVisitor.Result onLoopStatementBegin(VerilogLoopStatement node)
- Overrides:
onLoopStatementBegin
in classVerilogEmptyVisitor
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onLoopGenerateBegin
public NodeVisitor.Result onLoopGenerateBegin(VerilogLoopGenerate node)
- Overrides:
onLoopGenerateBegin
in classVerilogEmptyVisitor
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onLoopGenerateEnd
public NodeVisitor.Result onLoopGenerateEnd(VerilogLoopGenerate node)
- Overrides:
onLoopGenerateEnd
in classVerilogEmptyVisitor
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onModuleBegin
public NodeVisitor.Result onModuleBegin(VerilogModule node)
- Overrides:
onModuleBegin
in classVerilogEmptyVisitor
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onModuleEnd
public NodeVisitor.Result onModuleEnd(VerilogModule node)
- Overrides:
onModuleEnd
in classVerilogEmptyVisitor
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onDefineParameterBegin
public NodeVisitor.Result onDefineParameterBegin(VerilogDefineParameter node)
- Overrides:
onDefineParameterBegin
in classVerilogEmptyVisitor
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onPortConnectionBegin
public NodeVisitor.Result onPortConnectionBegin(VerilogPortConnection node)
- Overrides:
onPortConnectionBegin
in classVerilogEmptyVisitor
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onTaskStatementBegin
public NodeVisitor.Result onTaskStatementBegin(VerilogTaskStatement node)
- Overrides:
onTaskStatementBegin
in classVerilogEmptyVisitor
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onWaitStatementBegin
public NodeVisitor.Result onWaitStatementBegin(VerilogWaitStatement node)
- Overrides:
onWaitStatementBegin
in classVerilogEmptyVisitor
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onSequenceDeclarationBegin
public NodeVisitor.Result onSequenceDeclarationBegin(SvaSequenceDeclaration node)
- Overrides:
onSequenceDeclarationBegin
in classVerilogEmptyVisitor
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onPropertyDeclarationBegin
public NodeVisitor.Result onPropertyDeclarationBegin(SvaPropertyDeclaration node)
- Overrides:
onPropertyDeclarationBegin
in classVerilogEmptyVisitor
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onAssertionStatementBegin
public NodeVisitor.Result onAssertionStatementBegin(SvaAssertionStatement node)
- Overrides:
onAssertionStatementBegin
in classVerilogEmptyVisitor
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