Class VerilogDesign.Builder

  • Enclosing class:
    VerilogDesign

    public static final class VerilogDesign.Builder
    extends java.lang.Object
    • Constructor Detail

      • Builder

        public Builder()
    • Method Detail

      • setName

        public void setName​(java.lang.String name)
      • getParameters

        public java.util.Map<java.lang.String,​VerilogParameter> getParameters()
      • addParameter

        public void addParameter​(VerilogParameter.Type type,
                                 java.lang.String name,
                                 ru.ispras.fortress.data.Data data)
      • addSvaInstance

        public void addSvaInstance​(ru.ispras.fortress.expression.NodeVariable instVariable,
                                   VerilogInstantiator instantiator)
      • build

        public VerilogDesign build()
        Calculates the variables' bit sizes and modifies the expressions.
        Returns:
        the elaborated design.