Package ru.ispras.verilog.parser
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Class Summary Class Description VerilogDesignBackend VerilogDesignBackend
is a basic class for design-level back-ends.VerilogDesignBackends VerilogDesignBackends
implements a composite design-level back-end.VerilogFrontend VerilogFrontend
implements the Verilog front-end.VerilogLibrary VerilogLibrary
stores the standard declarations.VerilogLogger VerilogLogger
implements the logging facilities.VerilogSyntaxBackend VerilogSyntaxBackend
is a basic class for AST-level back-ends.VerilogSyntaxBackends VerilogSyntaxBackends
implements a composite AST-level back-end.VerilogTranslator VerilogTranslator
is the main class of the Verilog translator. -
Enum Summary Enum Description VerilogStandard VerilogStandard
contains Verilog standards' identifiers.