Package ru.ispras.verilog.parser.model
Class VerilogIfGenerate
- java.lang.Object
-
- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
-
- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
-
- ru.ispras.verilog.parser.model.VerilogNode
-
- ru.ispras.verilog.parser.model.VerilogIfGenerate
-
public final class VerilogIfGenerate extends VerilogNode
VerilogIfGenerate
represents if-then-else generate constructs.
-
-
Nested Class Summary
-
Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
-
Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
-
-
Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
-
Constructor Summary
Constructors Constructor Description VerilogIfGenerate(VerilogIfGenerate other, VerilogNode parent)
Creates a if-then-else generate construct.VerilogIfGenerate(VerilogNode parent)
Creates a if-then-else generate construct.
-
Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description VerilogIfGenerate
clone()
Clones the symbol table.VerilogBlockGenerate
getElseGenerate()
Returns the generate block related to the branchelse
.VerilogExpression
getExpression()
Returns the condition.VerilogBlockGenerate
getThenGenerate()
Returns the generate block related to the branchthen
.void
setElseGenerate(VerilogBlockGenerate elseGenerate)
Sets the generate block related to the else branch.void
setExpression(VerilogExpression expression)
Sets the condition.void
setThenGenerate(VerilogBlockGenerate thenGenerate)
Sets the generate block related to the branchthen
.-
Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
-
Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
-
Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
-
-
-
-
Field Detail
-
TAG
public static final VerilogNode.Tag TAG
-
TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
-
-
Constructor Detail
-
VerilogIfGenerate
public VerilogIfGenerate(VerilogNode parent)
Creates a if-then-else generate construct.- Parameters:
parent
- the parent node.
-
VerilogIfGenerate
public VerilogIfGenerate(VerilogIfGenerate other, VerilogNode parent)
Creates a if-then-else generate construct.- Parameters:
other
- the if-then-else generate construct to be copied.parent
- the parent node.
-
-
Method Detail
-
getExpression
public VerilogExpression getExpression()
Returns the condition.- Returns:
- the condition.
-
setExpression
public void setExpression(VerilogExpression expression)
Sets the condition.- Parameters:
expression
- the condition.
-
getThenGenerate
public VerilogBlockGenerate getThenGenerate()
Returns the generate block related to the branchthen
.- Returns:
- the
then
's generate block.
-
setThenGenerate
public void setThenGenerate(VerilogBlockGenerate thenGenerate)
Sets the generate block related to the branchthen
.- Parameters:
thenGenerate
- the generate block to be set.
-
getElseGenerate
public VerilogBlockGenerate getElseGenerate()
Returns the generate block related to the branchelse
.- Returns:
- the
else
's generate block.
-
setElseGenerate
public void setElseGenerate(VerilogBlockGenerate elseGenerate)
Sets the generate block related to the else branch.- Parameters:
elseGenerate
- the generate block to be set.
-
clone
public VerilogIfGenerate clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogNode
- Returns:
- a copy of the symbol table.
-
-