Package ru.ispras.verilog.parser.model
Class VerilogIfStatementBranch
- java.lang.Object
-
- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
-
- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
-
- ru.ispras.verilog.parser.model.VerilogNode
-
- ru.ispras.verilog.parser.model.VerilogIfStatementBranch
-
public final class VerilogIfStatementBranch extends VerilogNode
VerilogIfStatementBranch
represents if-then-else statement branches (then and else).
-
-
Nested Class Summary
Nested Classes Modifier and Type Class Description static class
VerilogIfStatementBranch.Type
VerilogIfStatementBranch.Type
contains the branch types.-
Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
-
Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
-
-
Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
-
Constructor Summary
Constructors Constructor Description VerilogIfStatementBranch(VerilogIfStatementBranch.Type type, VerilogStatement statement, VerilogNode parent)
Create an if-then-else statement branch.VerilogIfStatementBranch(VerilogIfStatementBranch other, VerilogNode parent)
VerilogIfStatementBranch(VerilogNode parent)
Creates an if-then-else statement branch.
-
Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description VerilogIfStatementBranch
clone()
Clones the symbol table.VerilogExpression
getExpression()
Returns the condition associated with the branch.VerilogStatement
getStatement()
Returns the branch body.VerilogIfStatementBranch.Type
getType()
Returns the branch type (THEN
orELSE
).boolean
isElse()
Checks whether the branch isELSE
.boolean
isThen()
Checks whether the branch isTHEN
.void
setElse()
Sets the branch type toELSE
.void
setStatement(VerilogStatement statement)
Sets the branch body.void
setThen()
Sets the branch type toTHEN
.void
setType(VerilogIfStatementBranch.Type type)
Sets the branch type.-
Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
-
Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
-
Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
-
-
-
-
Field Detail
-
TAG
public static final VerilogNode.Tag TAG
-
TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
-
-
Constructor Detail
-
VerilogIfStatementBranch
public VerilogIfStatementBranch(VerilogNode parent)
Creates an if-then-else statement branch.- Parameters:
parent
- the parent node.
-
VerilogIfStatementBranch
public VerilogIfStatementBranch(VerilogIfStatementBranch.Type type, VerilogStatement statement, VerilogNode parent)
Create an if-then-else statement branch.- Parameters:
type
- the branch type.statement
- the branch body.parent
- the parent node.
-
VerilogIfStatementBranch
public VerilogIfStatementBranch(VerilogIfStatementBranch other, VerilogNode parent)
-
-
Method Detail
-
getType
public VerilogIfStatementBranch.Type getType()
Returns the branch type (THEN
orELSE
).- Returns:
- the branch type.
-
setType
public void setType(VerilogIfStatementBranch.Type type)
Sets the branch type.- Parameters:
type
- the branch type.
-
isThen
public boolean isThen()
Checks whether the branch isTHEN
.- Returns:
true
iff the branch isTHEN
.
-
isElse
public boolean isElse()
Checks whether the branch isELSE
.- Returns:
true
iff the branch isELSE
.
-
setThen
public void setThen()
Sets the branch type toTHEN
.
-
setElse
public void setElse()
Sets the branch type toELSE
.
-
getStatement
public VerilogStatement getStatement()
Returns the branch body.- Returns:
- the branch body.
-
setStatement
public void setStatement(VerilogStatement statement)
Sets the branch body.- Parameters:
statement
- the branch body.
-
getExpression
public VerilogExpression getExpression()
Returns the condition associated with the branch.- Returns:
- the branch condition.
-
clone
public VerilogIfStatementBranch clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogNode
- Returns:
- a copy of the symbol table.
-
-