Class VerilogDesign
- java.lang.Object
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- ru.ispras.verilog.parser.elaborator.VerilogDesign
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public final class VerilogDesign extends java.lang.Object
VerilogDesign
represents an elaborated design.
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Nested Class Summary
Nested Classes Modifier and Type Class Description static class
VerilogDesign.Builder
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description java.lang.String
getName()
Returns the name of the design.java.util.Map<java.lang.String,VerilogParameter>
getParameters()
java.lang.Iterable<VerilogProcess>
getProcesses()
Returns the iterator over the design processes.java.util.Map<java.lang.String,SvaInstantiation>
getSvaInstances()
java.util.Map<java.lang.String,VerilogDescriptor>
getVariables()
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Method Detail
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getName
public java.lang.String getName()
Returns the name of the design.- Returns:
- the design name.
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getParameters
public java.util.Map<java.lang.String,VerilogParameter> getParameters()
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getVariables
public java.util.Map<java.lang.String,VerilogDescriptor> getVariables()
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getSvaInstances
public java.util.Map<java.lang.String,SvaInstantiation> getSvaInstances()
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getProcesses
public java.lang.Iterable<VerilogProcess> getProcesses()
Returns the iterator over the design processes.- Returns:
- the process iterator.
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