Package ru.ispras.verilog.parser.model
Class VerilogAttribute
- java.lang.Object
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- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
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- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
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- ru.ispras.verilog.parser.model.VerilogNode
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- ru.ispras.verilog.parser.model.VerilogAttribute
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public final class VerilogAttribute extends VerilogNode
VerilogAttribute
represents attributes.
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Nested Class Summary
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
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Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
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Constructor Summary
Constructors Constructor Description VerilogAttribute(VerilogAttribute other, VerilogNode parent)
Creates a copy of the attribute.VerilogAttribute(VerilogNode parent)
Creates an attribute.
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description VerilogAttribute
clone()
Clones the symbol table.VerilogExpression
getExpression()
Returns the expression of the attribute.void
setExpression(VerilogExpression expression)
Sets the expression of the attribute.-
Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
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Field Detail
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TAG
public static final VerilogNode.Tag TAG
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TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
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Constructor Detail
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VerilogAttribute
public VerilogAttribute(VerilogNode parent)
Creates an attribute.- Parameters:
parent
- the node parent.
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VerilogAttribute
public VerilogAttribute(VerilogAttribute other, VerilogNode parent)
Creates a copy of the attribute.- Parameters:
other
- the attribute to be copied.parent
- the parent node.
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Method Detail
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getExpression
public VerilogExpression getExpression()
Returns the expression of the attribute.- Returns:
- the expression.
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setExpression
public void setExpression(VerilogExpression expression)
Sets the expression of the attribute.- Parameters:
expression
- the expression to be set.
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clone
public VerilogAttribute clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogNode
- Returns:
- a copy of the symbol table.
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