Package ru.ispras.verilog.parser.model
Class VerilogTableEntry
- java.lang.Object
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- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
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- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
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- ru.ispras.verilog.parser.model.VerilogNode
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- ru.ispras.verilog.parser.model.VerilogTableEntry
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public final class VerilogTableEntry extends VerilogNode
VerilogTableEntry
represents UDP table entries.
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Nested Class Summary
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
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Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
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Constructor Summary
Constructors Constructor Description VerilogTableEntry(VerilogNode parent)
Creates a UDP table entry.VerilogTableEntry(VerilogTableEntry other, VerilogNode parent)
Creates a copy of the UDP table entry.
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description void
addEdge(java.lang.String edge)
Adds the edge to the list.void
addInput1(java.lang.String input1)
Adds the input to the list (1).void
addInput2(java.lang.String input2)
Adds the input to the list (2).void
addOutput(java.lang.String output)
Adds the output to the list.VerilogTableEntry
clone()
Clones the symbol table.java.util.List<java.lang.String>
getEdge()
Returns the edges.java.util.List<java.lang.String>
getInputs1()
Returns the input signals (1).java.util.List<java.lang.String>
getInputs2()
Returns the input signals (2).java.util.List<java.lang.String>
getOutputs()
Returns the output signals.-
Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
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Field Detail
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TAG
public static final VerilogNode.Tag TAG
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TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
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Constructor Detail
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VerilogTableEntry
public VerilogTableEntry(VerilogNode parent)
Creates a UDP table entry.- Parameters:
parent
- the parent node.
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VerilogTableEntry
public VerilogTableEntry(VerilogTableEntry other, VerilogNode parent)
Creates a copy of the UDP table entry.- Parameters:
other
- the UDP table entry,parent
- the parent node.
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Method Detail
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getInputs1
public java.util.List<java.lang.String> getInputs1()
Returns the input signals (1).- Returns:
- the list of input signals.
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addInput1
public void addInput1(java.lang.String input1)
Adds the input to the list (1).- Parameters:
input1
- the input to be added.
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getInputs2
public java.util.List<java.lang.String> getInputs2()
Returns the input signals (2).- Returns:
- the list of input signals.
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addInput2
public void addInput2(java.lang.String input2)
Adds the input to the list (2).- Parameters:
input2
- the input to be added.
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getEdge
public java.util.List<java.lang.String> getEdge()
Returns the edges.- Returns:
- the list of edges.
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addEdge
public void addEdge(java.lang.String edge)
Adds the edge to the list.- Parameters:
edge
- the edge to be added.
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getOutputs
public java.util.List<java.lang.String> getOutputs()
Returns the output signals.- Returns:
- the list of output signals.
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addOutput
public void addOutput(java.lang.String output)
Adds the output to the list.- Parameters:
output
- the output to be added.
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clone
public VerilogTableEntry clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogNode
- Returns:
- a copy of the symbol table.
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