Class VerilogDeclaration


  • public final class VerilogDeclaration
    extends VerilogNode
    VerilogDeclaration represents declarations.

    There are the following types of declarations:

    • input;
    • output;
    • inout;
    • event;
    • parameter;
    • specparam;
    • localparam;
    • genvar;
    • variable.
    • Constructor Detail

      • VerilogDeclaration

        public VerilogDeclaration​(VerilogNode parent)
        Creates a declaration.
        Parameters:
        parent - the parent node.
      • VerilogDeclaration

        public VerilogDeclaration​(VerilogDeclaration other,
                                  VerilogNode parent)
        Creates a copy of the declaration.
        Parameters:
        other - the declaration to be copied.
        parent - the parent node.
    • Method Detail

      • setType

        public void setType​(VerilogDeclaration.Type type)
        Sets the declaration type.
        Parameters:
        type - the type to be set.
      • isInput

        public boolean isInput()
        Checks whether the declaration is INPUT.
        Returns:
        true iff the declaration is INPUT.
      • isOutput

        public boolean isOutput()
        Checks whether the declaration is OUTPUT.
        Returns:
        true iff the declaration is OUTPUT.
      • isInout

        public boolean isInout()
        Checks whether the declaration is INOUT.
        Returns:
        true iff the declaration is INOUT.
      • isPort

        public boolean isPort()
        Checks whether the declaration is a port (INPUT, OUTPUT, or INOUT).
        Overrides:
        isPort in class VerilogNode
        Returns:
        true iff the declaration is a port.
      • isEvent

        public boolean isEvent()
        Checks whether the declaration is EVENT.
        Returns:
        true iff the declaration is EVENT.
      • isParameter

        public boolean isParameter()
        Checks whether the declaration is PARAMETER.
        Returns:
        true iff the declaration is PARAMETER.
      • isSpecparam

        public boolean isSpecparam()
        Checks whether the declaration is SPECPARAMETER.
        Returns:
        true iff the declaration is SPECPARAMETER.
      • isLocalparam

        public boolean isLocalparam()
        Checks whether the declaration is LOCALPARAM.
        Returns:
        true iff the declaration is LOCALPARAM.
      • isParam

        public boolean isParam()
        Checks whether the declaration is a parameter (PARAMETER, SPECPARAM, or LOCALPARAM).
        Returns:
        true iff the declaration is a port.
      • isGenvar

        public boolean isGenvar()
        Checks whether the declaration is GENVAR.
        Returns:
        true iff the declaration is GENVAR.
      • isVariable

        public boolean isVariable()
        Checks whether the declaration is VARIABLE.
        Returns:
        true iff the declaration is VARIABLE.
      • setInput

        public void setInput()
        Sets the type of the statement to INPUT.
      • setOutput

        public void setOutput()
        Sets the type of the statement to OUTPUT.
      • setInout

        public void setInout()
        Sets the type of the statement to INOUT.
      • setEvent

        public void setEvent()
        Sets the type of the statement to EVENT.
      • setParameter

        public void setParameter()
        Sets the type of the statement to PARAMETER.
      • setSpecparam

        public void setSpecparam()
        Sets the type of the statement to SPECPARAM.
      • setLocalparam

        public void setLocalparam()
        Sets the type of the statement to LOCALPARAM.
      • setGenvar

        public void setGenvar()
        Sets the type of the statement to GENVAR.
      • setVariable

        public void setVariable()
        Sets the type of the statement to VARIABLE.
      • getElementType

        public VerilogElementType getElementType()
        Returns the type of the declared element.
        Returns:
        the element type.
      • setElementType

        public void setElementType​(VerilogElementType elementType)
        Sets the type of the declared element.
        Parameters:
        elementType - the type to be set.
      • getDimensions

        public java.util.List<VerilogRange> getDimensions()
        Returns the dimensions of the declared element.
        Returns:
        the element dimensions.
      • addDimension

        public void addDimension​(VerilogRange range)
        Extends the dimension of the declared element.
        Parameters:
        range - the new dimension.
      • getExpression

        public VerilogMinTypMax getExpression()
        Returns the expression representing the initial value.
        Returns:
        the initial value expression.
      • setExpression

        public void setExpression​(VerilogMinTypMax expression)
        Sets the expression representing the initial value.
        Parameters:
        expression - the expression to be set.
      • addDeclaration

        public void addDeclaration​(VerilogDeclaration declaration)
        Merges this declaration with the given one.

        [IEEE Std 1364-2005] 12.3.3 Port declarations If a port declaration does not include a net or variable type, then the port can be again declared in a net or variable declaration. If the net or variable is declared as a vector, the range specification between the two declarations of a port shall be identical. Once a name is used in a port declaration, it shall not be declared again in another port declaration or in a data type declaration.

        Parameters:
        declaration - the declaration to be merged with this one.