Package ru.ispras.verilog.parser.model.basis
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Class Summary Class Description VerilogDelay VerilogDelay
represents the abstract syntax of the delay.VerilogElementType VerilogElementType
represents element types.VerilogEvent VerilogEvent
represents events.VerilogEventControl VerilogEventControl
represents event control constructs.VerilogExpression VerilogExpression
represents expressions.VerilogLiteral VerilogLiteral
represents numeric and string literals.VerilogMinTypMax VerilogMinTypMax
represents the min:typ:max expressions.VerilogPath VerilogPath
represents paths.VerilogPathDescription VerilogPathDescription
represents path descriptions.VerilogPathItem VerilogPathItem
represents path items.VerilogRange VerilogRange
represents ranges.VerilogReference VerilogReference
represents references.VerilogRepeatEvents VerilogRepeatEvents
represents repeat-event constructs.VerilogStrength VerilogStrength
represents signal strengths. -
Enum Summary Enum Description VerilogEdge VerilogEdge
represents signal edge types (positive, negative, or undefined).VerilogElementType.Type VerilogElementType.Type
contains the element types.VerilogLiteral.Type VerilogLiteral.Type
contains literal types.VerilogPathDescription.Polarity VerilogPathDescription.Polarity
contains the polarity types.VerilogPathDescription.Type VerilogPathDescription.Type
contains the path description types.VerilogRange.Type VerilogRange.Type
contains the range types.VerilogStrength.Type VerilogStrength.Type
contains the strengths.