Class VerilogTransformerVariableSubstitute
- java.lang.Object
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- ru.ispras.verilog.parser.walker.VerilogNodeVisitor
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- ru.ispras.verilog.parser.walker.VerilogEmptyVisitor
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- ru.ispras.verilog.parser.transformer.VerilogTransformer
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- ru.ispras.verilog.parser.transformer.VerilogTransformerVariableSubstitute
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- All Implemented Interfaces:
NodeVisitor<VerilogNode.Tag>
public final class VerilogTransformerVariableSubstitute extends VerilogTransformer
VerilogTransformerVariableSubstitute
implements an engine that substitutes variables with expressions taking into account bit ranges.
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Nested Class Summary
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Nested classes/interfaces inherited from interface ru.ispras.verilog.parser.core.NodeVisitor
NodeVisitor.Result
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Constructor Summary
Constructors Constructor Description VerilogTransformerVariableSubstitute(java.util.Map<java.lang.String,VerilogDescriptor> variables, VerilogContext context, java.util.Map<java.lang.String,VerilogParameter> parameters)
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Method Summary
All Methods Static Methods Instance Methods Concrete Methods Modifier and Type Method Description ru.ispras.fortress.expression.Node
transform(ru.ispras.fortress.expression.Node node)
static ru.ispras.fortress.expression.Node
transform(ru.ispras.fortress.expression.Node node, java.util.Map<java.lang.String,VerilogDescriptor> variables, VerilogContext context, java.util.Map<java.lang.String,VerilogParameter> parameters)
static void
transform(VerilogNode node, java.util.Map<java.lang.String,VerilogDescriptor> variables, VerilogContext context, java.util.Map<java.lang.String,VerilogParameter> parameters)
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Methods inherited from class ru.ispras.verilog.parser.transformer.VerilogTransformer
onAssertionStatementBegin, onAssignBegin, onAssignStatementBegin, onCaseStatementBegin, onCaseStatementItemBegin, onDeclarationBegin, onDelayedStatementBegin, onIfStatementBegin, onLoopStatementBegin, onSvaInstanceBegin, onTaskStatementBegin, onWaitStatementBegin, run
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Methods inherited from class ru.ispras.verilog.parser.walker.VerilogEmptyVisitor
onActivityBegin, onActivityEnd, onAssertionStatementEnd, onAssignEnd, onAssignmentBegin, onAssignmentEnd, onAssignStatementEnd, onAttributeBegin, onAttributeEnd, onBlockGenerateBegin, onBlockGenerateEnd, onBlockStatementBegin, onBlockStatementEnd, onCaseGenerateBegin, onCaseGenerateEnd, onCaseGenerateItemBegin, onCaseGenerateItemEnd, onCaseStatementEnd, onCaseStatementItemEnd, onCodeBegin, onCodeEnd, onDeclarationEnd, onDefineParameterBegin, onDefineParameterEnd, onDelayedStatementEnd, onDisableStatementBegin, onDisableStatementEnd, onGenerateBegin, onGenerateEnd, onIfGenerateBegin, onIfGenerateBranchBegin, onIfGenerateBranchEnd, onIfGenerateEnd, onIfStatementBranchBegin, onIfStatementBranchEnd, onIfStatementEnd, onInstantiationBegin, onInstantiationEnd, onLoopGenerateBegin, onLoopGenerateEnd, onLoopStatementEnd, onModuleBegin, onModuleEnd, onNullStatementBegin, onNullStatementEnd, onPathDeclarationBegin, onPathDeclarationEnd, onPortBegin, onPortConnectionBegin, onPortConnectionEnd, onPortEnd, onProcedureBegin, onProcedureEnd, onPropertyDeclarationBegin, onPropertyDeclarationEnd, onPulseStyleBegin, onPulseStyleEnd, onSequenceDeclarationBegin, onSequenceDeclarationEnd, onShowCancelledBegin, onShowCancelledEnd, onSpecifyBegin, onSpecifyEnd, onSvaInstanceEnd, onTableBegin, onTableEnd, onTableEntryBegin, onTableEntryEnd, onTaskStatementEnd, onTriggerStatementBegin, onTriggerStatementEnd, onWaitStatementEnd
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Methods inherited from class ru.ispras.verilog.parser.walker.VerilogNodeVisitor
onBegin, onEnd
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Constructor Detail
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VerilogTransformerVariableSubstitute
public VerilogTransformerVariableSubstitute(java.util.Map<java.lang.String,VerilogDescriptor> variables, VerilogContext context, java.util.Map<java.lang.String,VerilogParameter> parameters)
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Method Detail
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transform
public static ru.ispras.fortress.expression.Node transform(ru.ispras.fortress.expression.Node node, java.util.Map<java.lang.String,VerilogDescriptor> variables, VerilogContext context, java.util.Map<java.lang.String,VerilogParameter> parameters)
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transform
public static void transform(VerilogNode node, java.util.Map<java.lang.String,VerilogDescriptor> variables, VerilogContext context, java.util.Map<java.lang.String,VerilogParameter> parameters)
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transform
public ru.ispras.fortress.expression.Node transform(ru.ispras.fortress.expression.Node node)
- Specified by:
transform
in classVerilogTransformer
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