Class AssignCheckerModuleVisitor
- java.lang.Object
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- ru.ispras.verilog.parser.walker.VerilogNodeVisitor
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- ru.ispras.verilog.parser.walker.VerilogEmptyVisitor
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- ru.ispras.verilog.parser.backends.design.checker.AssignCheckerModuleVisitor
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- All Implemented Interfaces:
NodeVisitor<VerilogNode.Tag>
public class AssignCheckerModuleVisitor extends VerilogEmptyVisitor
AssignCheckerModuleVisitor
is a key component for Verilog assign checker back-end.
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Nested Class Summary
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Nested classes/interfaces inherited from interface ru.ispras.verilog.parser.core.NodeVisitor
NodeVisitor.Result
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Constructor Summary
Constructors Constructor Description AssignCheckerModuleVisitor()
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description NodeVisitor.Result
onAssignStatementBegin(VerilogAssignStatement node)
Performs checking assignment statement required by [IEEE Std 1364-2005].-
Methods inherited from class ru.ispras.verilog.parser.walker.VerilogEmptyVisitor
onActivityBegin, onActivityEnd, onAssertionStatementBegin, onAssertionStatementEnd, onAssignBegin, onAssignEnd, onAssignmentBegin, onAssignmentEnd, onAssignStatementEnd, onAttributeBegin, onAttributeEnd, onBlockGenerateBegin, onBlockGenerateEnd, onBlockStatementBegin, onBlockStatementEnd, onCaseGenerateBegin, onCaseGenerateEnd, onCaseGenerateItemBegin, onCaseGenerateItemEnd, onCaseStatementBegin, onCaseStatementEnd, onCaseStatementItemBegin, onCaseStatementItemEnd, onCodeBegin, onCodeEnd, onDeclarationBegin, onDeclarationEnd, onDefineParameterBegin, onDefineParameterEnd, onDelayedStatementBegin, onDelayedStatementEnd, onDisableStatementBegin, onDisableStatementEnd, onGenerateBegin, onGenerateEnd, onIfGenerateBegin, onIfGenerateBranchBegin, onIfGenerateBranchEnd, onIfGenerateEnd, onIfStatementBegin, onIfStatementBranchBegin, onIfStatementBranchEnd, onIfStatementEnd, onInstantiationBegin, onInstantiationEnd, onLoopGenerateBegin, onLoopGenerateEnd, onLoopStatementBegin, onLoopStatementEnd, onModuleBegin, onModuleEnd, onNullStatementBegin, onNullStatementEnd, onPathDeclarationBegin, onPathDeclarationEnd, onPortBegin, onPortConnectionBegin, onPortConnectionEnd, onPortEnd, onProcedureBegin, onProcedureEnd, onPropertyDeclarationBegin, onPropertyDeclarationEnd, onPulseStyleBegin, onPulseStyleEnd, onSequenceDeclarationBegin, onSequenceDeclarationEnd, onShowCancelledBegin, onShowCancelledEnd, onSpecifyBegin, onSpecifyEnd, onSvaInstanceBegin, onSvaInstanceEnd, onTableBegin, onTableEnd, onTableEntryBegin, onTableEntryEnd, onTaskStatementBegin, onTaskStatementEnd, onTriggerStatementBegin, onTriggerStatementEnd, onWaitStatementBegin, onWaitStatementEnd
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Methods inherited from class ru.ispras.verilog.parser.walker.VerilogNodeVisitor
onBegin, onEnd
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Method Detail
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onAssignStatementBegin
public NodeVisitor.Result onAssignStatementBegin(VerilogAssignStatement node)
Performs checking assignment statement required by [IEEE Std 1364-2005]. 4.9.3.1.2 Assignment to array elements- Overrides:
onAssignStatementBegin
in classVerilogEmptyVisitor
- Parameters:
node
- assign statement
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