Package ru.ispras.verilog.parser.model
Class VerilogIfStatement
- java.lang.Object
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- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
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- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
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- ru.ispras.verilog.parser.model.VerilogNode
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- ru.ispras.verilog.parser.model.VerilogStatement
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- ru.ispras.verilog.parser.model.VerilogIfStatement
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public final class VerilogIfStatement extends VerilogStatement
VerilogIfStatement
represents if-then-else statements.
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Nested Class Summary
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
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Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
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Fields inherited from class ru.ispras.verilog.parser.model.VerilogStatement
TAGS
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Constructor Summary
Constructors Constructor Description VerilogIfStatement(VerilogIfStatement other, VerilogNode parent)
Creates a copy of the if-then-else statement.VerilogIfStatement(VerilogNode parent)
Creates an if-then-else statement.
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description VerilogIfStatement
clone()
Clones the symbol table.VerilogStatement
getElseStatement()
Returns the statement related to the branchelse
.VerilogExpression
getExpression()
Returns the condition.VerilogStatement
getThenStatement()
Returns the statement related to the branchthen
.void
setElseStatement(VerilogStatement elseStatement)
Sets the statement related to the branchelse
.void
setExpression(VerilogExpression expression)
Sets the condition.void
setThenStatement(VerilogStatement thenStatement)
Sets the statement related to the branchthen
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Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
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Field Detail
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TAG
public static final VerilogNode.Tag TAG
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TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
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Constructor Detail
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VerilogIfStatement
public VerilogIfStatement(VerilogNode parent)
Creates an if-then-else statement.- Parameters:
parent
- the parent node.
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VerilogIfStatement
public VerilogIfStatement(VerilogIfStatement other, VerilogNode parent)
Creates a copy of the if-then-else statement.- Parameters:
other
- the if-then-else statement to be copied.parent
- the parent node.
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Method Detail
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getExpression
public VerilogExpression getExpression()
Returns the condition.- Returns:
- the condition.
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setExpression
public void setExpression(VerilogExpression expression)
Sets the condition.- Parameters:
expression
- the condition.
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getThenStatement
public VerilogStatement getThenStatement()
Returns the statement related to the branchthen
.- Returns:
- the
then
's statement.
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setThenStatement
public void setThenStatement(VerilogStatement thenStatement)
Sets the statement related to the branchthen
.- Parameters:
thenStatement
- the statement to be set.
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getElseStatement
public VerilogStatement getElseStatement()
Returns the statement related to the branchelse
.- Returns:
- the
else
's statement.
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setElseStatement
public void setElseStatement(VerilogStatement elseStatement)
Sets the statement related to the branchelse
.- Parameters:
elseStatement
- the statement to be set.
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clone
public VerilogIfStatement clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogStatement
- Returns:
- a copy of the symbol table.
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