Class VerilogCaseStatement


  • public final class VerilogCaseStatement
    extends VerilogStatement
    VerilogCaseStatement represents case statements.

    There are the following process types:

    • case (ordinary case statement);
    • casex (X-don't-care case statement);
    • casez (Z-don't-care case statement).
    • Constructor Detail

      • VerilogCaseStatement

        public VerilogCaseStatement​(VerilogNode parent)
        Creates a case statement.
        Parameters:
        parent - the parent node.
      • VerilogCaseStatement

        public VerilogCaseStatement​(VerilogCaseStatement other,
                                    VerilogNode parent)
        Creates a copy of the case statement.
        Parameters:
        other - the case statement to be copied.
        parent - the parent node.
    • Method Detail

      • setType

        public void setType​(VerilogCaseStatement.Type type)
        Sets the case statement type.
        Parameters:
        type - the type to be set.
      • isCase

        public boolean isCase()
        Checks whether the statement is CASE.
        Returns:
        true iff the statement is CASE.
      • isCaseX

        public boolean isCaseX()
        Checks whether the statement is CASEX.
        Returns:
        true iff the statement is CASEX.
      • isCaseZ

        public boolean isCaseZ()
        Checks whether the statement is CASEZ.
        Returns:
        true iff the statement is CASEZ.
      • setCase

        public void setCase()
        Sets the type of the statement to CASE.
      • setCaseX

        public void setCaseX()
        Sets the type of the statement to CASEX.
      • setCaseZ

        public void setCaseZ()
        Sets the type of the statement to CASEZ.
      • getExpression

        public VerilogExpression getExpression()
        Returns the case selection expression.
        Returns:
        the expression.
      • setExpression

        public void setExpression​(VerilogExpression expression)
        Sets the case selection expression.
        Parameters:
        expression - the expression to be set.
      • addCase

        public void addCase​(VerilogCaseStatementItem item)
        Adds the case to the case selection construct.
        Parameters:
        item - the case to be added.