Package ru.ispras.verilog.parser.model
Class VerilogPortConnection
- java.lang.Object
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- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
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- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
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- ru.ispras.verilog.parser.model.VerilogNode
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- ru.ispras.verilog.parser.model.VerilogPortConnection
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public final class VerilogPortConnection extends VerilogNode
VerilogPortConnection
represents port connections.
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Nested Class Summary
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
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Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
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Constructor Summary
Constructors Constructor Description VerilogPortConnection(VerilogNode parent)
Creates a port connection.VerilogPortConnection(VerilogPortConnection other, VerilogNode parent)
Creates a copy of the port connection.
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description VerilogPortConnection
clone()
Clones the symbol table.VerilogExpression
getExpression()
Returns the expression connected to the port.void
setExpression(VerilogExpression expression)
Sets the expression connected to the port.-
Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
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Field Detail
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TAG
public static final VerilogNode.Tag TAG
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TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
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Constructor Detail
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VerilogPortConnection
public VerilogPortConnection(VerilogNode parent)
Creates a port connection.- Parameters:
parent
- the parent node.
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VerilogPortConnection
public VerilogPortConnection(VerilogPortConnection other, VerilogNode parent)
Creates a copy of the port connection.- Parameters:
other
- the port connection to be copied.parent
- the parent node.
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Method Detail
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getExpression
public VerilogExpression getExpression()
Returns the expression connected to the port.- Returns:
- the port connection expression.
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setExpression
public void setExpression(VerilogExpression expression)
Sets the expression connected to the port.- Parameters:
expression
- the expression to be set.
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clone
public VerilogPortConnection clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogNode
- Returns:
- a copy of the symbol table.
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