Package ru.ispras.verilog.parser.model
Class VerilogDeclaration
- java.lang.Object
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- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
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- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
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- ru.ispras.verilog.parser.model.VerilogNode
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- ru.ispras.verilog.parser.model.VerilogDeclaration
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public final class VerilogDeclaration extends VerilogNode
VerilogDeclaration
represents declarations.There are the following types of declarations:
input
;output
;inout
;event
;parameter
;specparam
;localparam
;genvar
;variable
.
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Nested Class Summary
Nested Classes Modifier and Type Class Description static class
VerilogDeclaration.Type
VerilogDeclaration.Type
contains the declaration types.-
Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
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Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
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Constructor Summary
Constructors Constructor Description VerilogDeclaration(VerilogDeclaration other, VerilogNode parent)
Creates a copy of the declaration.VerilogDeclaration(VerilogNode parent)
Creates a declaration.
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description void
addDeclaration(VerilogDeclaration declaration)
Merges this declaration with the given one.void
addDimension(VerilogRange range)
Extends the dimension of the declared element.VerilogDeclaration
clone()
Clones the symbol table.java.util.List<VerilogRange>
getDimensions()
Returns the dimensions of the declared element.VerilogElementType
getElementType()
Returns the type of the declared element.VerilogMinTypMax
getExpression()
Returns the expression representing the initial value.VerilogDeclaration.Type
getType()
Returns the declaration type.boolean
isEvent()
Checks whether the declaration isEVENT
.boolean
isGenvar()
Checks whether the declaration isGENVAR
.boolean
isInout()
Checks whether the declaration isINOUT
.boolean
isInput()
Checks whether the declaration isINPUT
.boolean
isLocalparam()
Checks whether the declaration isLOCALPARAM
.boolean
isOutput()
Checks whether the declaration isOUTPUT
.boolean
isParam()
Checks whether the declaration is a parameter (PARAMETER
,SPECPARAM
, orLOCALPARAM
).boolean
isParameter()
Checks whether the declaration isPARAMETER
.boolean
isPort()
Checks whether the declaration is a port (INPUT
,OUTPUT
, orINOUT
).boolean
isSpecparam()
Checks whether the declaration isSPECPARAMETER
.boolean
isVariable()
Checks whether the declaration isVARIABLE
.void
setElementType(VerilogElementType elementType)
Sets the type of the declared element.void
setEvent()
Sets the type of the statement toEVENT
.void
setExpression(VerilogMinTypMax expression)
Sets the expression representing the initial value.void
setGenvar()
Sets the type of the statement toGENVAR
.void
setInout()
Sets the type of the statement toINOUT
.void
setInput()
Sets the type of the statement toINPUT
.void
setLocalparam()
Sets the type of the statement toLOCALPARAM
.void
setOutput()
Sets the type of the statement toOUTPUT
.void
setParameter()
Sets the type of the statement toPARAMETER
.void
setSpecparam()
Sets the type of the statement toSPECPARAM
.void
setType(VerilogDeclaration.Type type)
Sets the declaration type.void
setVariable()
Sets the type of the statement toVARIABLE
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Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
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Field Detail
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TAG
public static final VerilogNode.Tag TAG
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TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
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Constructor Detail
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VerilogDeclaration
public VerilogDeclaration(VerilogNode parent)
Creates a declaration.- Parameters:
parent
- the parent node.
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VerilogDeclaration
public VerilogDeclaration(VerilogDeclaration other, VerilogNode parent)
Creates a copy of the declaration.- Parameters:
other
- the declaration to be copied.parent
- the parent node.
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Method Detail
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getType
public VerilogDeclaration.Type getType()
Returns the declaration type.- Returns:
- the declaration type.
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setType
public void setType(VerilogDeclaration.Type type)
Sets the declaration type.- Parameters:
type
- the type to be set.
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isInput
public boolean isInput()
Checks whether the declaration isINPUT
.- Returns:
true
iff the declaration isINPUT
.
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isOutput
public boolean isOutput()
Checks whether the declaration isOUTPUT
.- Returns:
true
iff the declaration isOUTPUT
.
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isInout
public boolean isInout()
Checks whether the declaration isINOUT
.- Returns:
true
iff the declaration isINOUT
.
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isPort
public boolean isPort()
Checks whether the declaration is a port (INPUT
,OUTPUT
, orINOUT
).- Overrides:
isPort
in classVerilogNode
- Returns:
true
iff the declaration is a port.
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isEvent
public boolean isEvent()
Checks whether the declaration isEVENT
.- Returns:
true
iff the declaration isEVENT
.
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isParameter
public boolean isParameter()
Checks whether the declaration isPARAMETER
.- Returns:
true
iff the declaration isPARAMETER
.
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isSpecparam
public boolean isSpecparam()
Checks whether the declaration isSPECPARAMETER
.- Returns:
true
iff the declaration isSPECPARAMETER
.
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isLocalparam
public boolean isLocalparam()
Checks whether the declaration isLOCALPARAM
.- Returns:
true
iff the declaration isLOCALPARAM
.
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isParam
public boolean isParam()
Checks whether the declaration is a parameter (PARAMETER
,SPECPARAM
, orLOCALPARAM
).- Returns:
true
iff the declaration is a port.
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isGenvar
public boolean isGenvar()
Checks whether the declaration isGENVAR
.- Returns:
true
iff the declaration isGENVAR
.
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isVariable
public boolean isVariable()
Checks whether the declaration isVARIABLE
.- Returns:
true
iff the declaration isVARIABLE
.
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setInput
public void setInput()
Sets the type of the statement toINPUT
.
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setOutput
public void setOutput()
Sets the type of the statement toOUTPUT
.
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setInout
public void setInout()
Sets the type of the statement toINOUT
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setEvent
public void setEvent()
Sets the type of the statement toEVENT
.
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setParameter
public void setParameter()
Sets the type of the statement toPARAMETER
.
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setSpecparam
public void setSpecparam()
Sets the type of the statement toSPECPARAM
.
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setLocalparam
public void setLocalparam()
Sets the type of the statement toLOCALPARAM
.
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setGenvar
public void setGenvar()
Sets the type of the statement toGENVAR
.
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setVariable
public void setVariable()
Sets the type of the statement toVARIABLE
.
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getElementType
public VerilogElementType getElementType()
Returns the type of the declared element.- Returns:
- the element type.
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setElementType
public void setElementType(VerilogElementType elementType)
Sets the type of the declared element.- Parameters:
elementType
- the type to be set.
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getDimensions
public java.util.List<VerilogRange> getDimensions()
Returns the dimensions of the declared element.- Returns:
- the element dimensions.
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addDimension
public void addDimension(VerilogRange range)
Extends the dimension of the declared element.- Parameters:
range
- the new dimension.
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getExpression
public VerilogMinTypMax getExpression()
Returns the expression representing the initial value.- Returns:
- the initial value expression.
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setExpression
public void setExpression(VerilogMinTypMax expression)
Sets the expression representing the initial value.- Parameters:
expression
- the expression to be set.
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addDeclaration
public void addDeclaration(VerilogDeclaration declaration)
Merges this declaration with the given one.[IEEE Std 1364-2005] 12.3.3 Port declarations If a port declaration does not include a net or variable type, then the port can be again declared in a net or variable declaration. If the net or variable is declared as a vector, the range specification between the two declarations of a port shall be identical. Once a name is used in a port declaration, it shall not be declared again in another port declaration or in a data type declaration.
- Parameters:
declaration
- the declaration to be merged with this one.
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clone
public VerilogDeclaration clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogNode
- Returns:
- a copy of the symbol table.
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