Package ru.ispras.verilog.parser.model
Class VerilogCode
- java.lang.Object
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- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
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- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
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- ru.ispras.verilog.parser.model.VerilogNode
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- ru.ispras.verilog.parser.model.VerilogCode
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public final class VerilogCode extends VerilogNode
VerilogCode
represents source code.
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Nested Class Summary
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
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Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
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Constructor Summary
Constructors Constructor Description VerilogCode()
Creates a source code node.VerilogCode(VerilogCode other)
Creates a copy of the source code node.
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description VerilogCode
clone()
Clones the symbol table.java.lang.String
getFileName()
Returns the name of the source code file.void
setFileName(java.lang.String fileName)
Sets the name of the source code file.-
Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
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Field Detail
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TAG
public static final VerilogNode.Tag TAG
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TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
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Constructor Detail
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VerilogCode
public VerilogCode()
Creates a source code node.
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VerilogCode
public VerilogCode(VerilogCode other)
Creates a copy of the source code node.- Parameters:
other
- the source code entity to be copied.
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Method Detail
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getFileName
public java.lang.String getFileName()
Returns the name of the source code file.- Returns:
- the file name.
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setFileName
public void setFileName(java.lang.String fileName)
Sets the name of the source code file.- Parameters:
fileName
- the file name.
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clone
public VerilogCode clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogNode
- Returns:
- a copy of the symbol table.
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