Package ru.ispras.verilog.parser.model
Class VerilogModule
- java.lang.Object
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- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
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- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
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- ru.ispras.verilog.parser.model.VerilogNode
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- ru.ispras.verilog.parser.model.VerilogModule
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public final class VerilogModule extends VerilogNode
VerilogModule
represents the abstract syntax of the module declaration.
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Nested Class Summary
Nested Classes Modifier and Type Class Description static class
VerilogModule.Type
VerilogModule.Type
contains the module types.-
Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
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Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
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Constructor Summary
Constructors Constructor Description VerilogModule(VerilogModule other, VerilogNode parent)
Creates a copy of the module.VerilogModule(VerilogNode parent)
Creates a module.
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description void
addDeclaration(VerilogDeclaration declaration)
Adds the declaration to the module.void
addPort(VerilogPort port)
Adds the port to the signature of the module.VerilogModule
clone()
Clones the symbol table.java.util.List<VerilogPort>
getPorts()
Returns the signature of the module (i.e., the list of its ports).VerilogModule.Type
getType()
Returns the type of the module.boolean
isGatePrimitive()
Checks whether the module isGATE_PRIMITIVE
.boolean
isMacromodule()
Checks whether the module isMACROMODULE
.boolean
isModule()
Checks whether the module isMODULE
.boolean
isUserPrimitive()
Checks whether the module isUSER_PRIMITIVE
.void
setGatePrimitive()
Sets the type of the module toGATE_PRIMITIVE
.void
setMacromodule()
Sets the type of the module toMACROMODULE
.void
setModule()
Sets the type of the module toMODULE
.void
setType(VerilogModule.Type type)
Sets the type of the module.void
setUserPrimitive()
Sets the type of the module toUSER_PRIMITIVE
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Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
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Field Detail
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TAG
public static final VerilogNode.Tag TAG
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TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
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Constructor Detail
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VerilogModule
public VerilogModule(VerilogNode parent)
Creates a module.- Parameters:
parent
- the parent node.
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VerilogModule
public VerilogModule(VerilogModule other, VerilogNode parent)
Creates a copy of the module.- Parameters:
other
- the module to be copied.parent
- the parent node.
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Method Detail
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getType
public VerilogModule.Type getType()
Returns the type of the module.- Returns:
- the type of the module.
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setType
public void setType(VerilogModule.Type type)
Sets the type of the module.- Parameters:
type
- the type to be set.
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isModule
public boolean isModule()
Checks whether the module isMODULE
.- Overrides:
isModule
in classVerilogNode
- Returns:
true
iff the module isMODULE
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isMacromodule
public boolean isMacromodule()
Checks whether the module isMACROMODULE
.- Returns:
true
iff the module isMACROMODULE
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isUserPrimitive
public boolean isUserPrimitive()
Checks whether the module isUSER_PRIMITIVE
.- Returns:
true
iff the module isUSER_PRIMITIVE
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isGatePrimitive
public boolean isGatePrimitive()
Checks whether the module isGATE_PRIMITIVE
.- Returns:
true
iff the module isGATE_PRIMITIVE
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setModule
public void setModule()
Sets the type of the module toMODULE
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setMacromodule
public void setMacromodule()
Sets the type of the module toMACROMODULE
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setUserPrimitive
public void setUserPrimitive()
Sets the type of the module toUSER_PRIMITIVE
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setGatePrimitive
public void setGatePrimitive()
Sets the type of the module toGATE_PRIMITIVE
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getPorts
public java.util.List<VerilogPort> getPorts()
Returns the signature of the module (i.e., the list of its ports).- Returns:
- the signature of the module.
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addPort
public void addPort(VerilogPort port)
Adds the port to the signature of the module.- Parameters:
port
- the port to be added.
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addDeclaration
public void addDeclaration(VerilogDeclaration declaration)
Adds the declaration to the module.- Parameters:
declaration
- the declaration to be added.
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clone
public VerilogModule clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogNode
- Returns:
- a copy of the symbol table.
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