Package ru.ispras.verilog.parser.model
Class VerilogDelayedStatement
- java.lang.Object
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- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
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- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
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- ru.ispras.verilog.parser.model.VerilogNode
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- ru.ispras.verilog.parser.model.VerilogStatement
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- ru.ispras.verilog.parser.model.VerilogDelayedStatement
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public final class VerilogDelayedStatement extends VerilogStatement
VerilogDelayedStatement
represents delayed statements.
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Nested Class Summary
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
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Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
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Fields inherited from class ru.ispras.verilog.parser.model.VerilogStatement
TAGS
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Constructor Summary
Constructors Constructor Description VerilogDelayedStatement(VerilogDelayedStatement other, VerilogNode parent)
Creates a delayed statement.VerilogDelayedStatement(VerilogNode parent)
Creates a delayed statement.
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description VerilogDelayedStatement
clone()
Clones the symbol table.VerilogEventControl
getEventControl()
Returns the delay of the delayed statement.VerilogStatement
getStatement()
Returns the statement of the delayed statement.void
setEventControl(VerilogEventControl control)
Sets the delay of the delayed statement.void
setStatement(VerilogStatement statement)
Sets the statement of the delayed statement.-
Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
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Field Detail
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TAG
public static final VerilogNode.Tag TAG
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TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
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Constructor Detail
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VerilogDelayedStatement
public VerilogDelayedStatement(VerilogNode parent)
Creates a delayed statement.- Parameters:
parent
- the parent node.
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VerilogDelayedStatement
public VerilogDelayedStatement(VerilogDelayedStatement other, VerilogNode parent)
Creates a delayed statement.- Parameters:
other
- the delayed statement to be copied.parent
- the parent node.
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Method Detail
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getEventControl
public VerilogEventControl getEventControl()
Returns the delay of the delayed statement.- Returns:
- the delay.
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setEventControl
public void setEventControl(VerilogEventControl control)
Sets the delay of the delayed statement.- Parameters:
control
- the delay.
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getStatement
public VerilogStatement getStatement()
Returns the statement of the delayed statement.- Returns:
- the statement.
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setStatement
public void setStatement(VerilogStatement statement)
Sets the statement of the delayed statement.- Parameters:
statement
- the statement.
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clone
public VerilogDelayedStatement clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogStatement
- Returns:
- a copy of the symbol table.
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