Package ru.ispras.verilog.parser.model
Class VerilogAssign
- java.lang.Object
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- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
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- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
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- ru.ispras.verilog.parser.model.VerilogNode
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- ru.ispras.verilog.parser.model.VerilogAssign
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public final class VerilogAssign extends VerilogNode
VerilogAssign
represents continuous assignments (assign
).
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Nested Class Summary
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
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Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
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Constructor Summary
Constructors Constructor Description VerilogAssign(VerilogAssign other, VerilogNode parent)
Creates a copy of the continuous assignment.VerilogAssign(VerilogNode parent)
Constructs a continuous assignment.
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description VerilogAssign
clone()
Clones the symbol table.VerilogAssignment
getAssignment()
Returns the assignment itself.VerilogDelay
getDelay()
Returns the assignment delay.VerilogStrength
getStrength()
Returns the drive strength.void
setAssignment(VerilogAssignment assignment)
Sets the assignment.void
setDelay(VerilogDelay delay)
Sets the assignment delay.void
setStrength(VerilogStrength strength)
Sets the drive strength.-
Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
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Field Detail
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TAG
public static final VerilogNode.Tag TAG
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TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
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Constructor Detail
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VerilogAssign
public VerilogAssign(VerilogNode parent)
Constructs a continuous assignment.- Parameters:
parent
- the parent node.
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VerilogAssign
public VerilogAssign(VerilogAssign other, VerilogNode parent)
Creates a copy of the continuous assignment.- Parameters:
other
- the continuous assignment to be copied.parent
- the parent node.
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Method Detail
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getStrength
public VerilogStrength getStrength()
Returns the drive strength.- Returns:
- the drive strength.
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setStrength
public void setStrength(VerilogStrength strength)
Sets the drive strength.- Parameters:
strength
- the strength to be set.
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getDelay
public VerilogDelay getDelay()
Returns the assignment delay.- Returns:
- the assignment delay.
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setDelay
public void setDelay(VerilogDelay delay)
Sets the assignment delay.- Parameters:
delay
- the delay to be set.
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getAssignment
public VerilogAssignment getAssignment()
Returns the assignment itself.- Returns:
- the assignment.
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setAssignment
public void setAssignment(VerilogAssignment assignment)
Sets the assignment.- Parameters:
assignment
- the assignment to be set.
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clone
public VerilogAssign clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogNode
- Returns:
- a copy of the symbol table.
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