Package ru.ispras.verilog.parser.model
Class VerilogNullStatement
- java.lang.Object
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- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
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- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
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- ru.ispras.verilog.parser.model.VerilogNode
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- ru.ispras.verilog.parser.model.VerilogStatement
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- ru.ispras.verilog.parser.model.VerilogNullStatement
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public final class VerilogNullStatement extends VerilogStatement
VerilogNullStatement
represents null statements.
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Nested Class Summary
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
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Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
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Fields inherited from class ru.ispras.verilog.parser.model.VerilogStatement
TAGS
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Constructor Summary
Constructors Constructor Description VerilogNullStatement(VerilogNode parent)
Creates a null statement.VerilogNullStatement(VerilogNullStatement other, VerilogNode parent)
Creates a copy of the null statement.
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description VerilogNullStatement
clone()
Clones the symbol table.-
Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
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Field Detail
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TAG
public static final VerilogNode.Tag TAG
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TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
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Constructor Detail
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VerilogNullStatement
public VerilogNullStatement(VerilogNode parent)
Creates a null statement.- Parameters:
parent
- the parent node.
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VerilogNullStatement
public VerilogNullStatement(VerilogNullStatement other, VerilogNode parent)
Creates a copy of the null statement.- Parameters:
other
- the null statement to be copied.parent
- the parent node.
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Method Detail
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clone
public VerilogNullStatement clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogStatement
- Returns:
- a copy of the symbol table.
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