Class VerilogDesign.Builder
- java.lang.Object
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- ru.ispras.verilog.parser.elaborator.VerilogDesign.Builder
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- Enclosing class:
- VerilogDesign
public static final class VerilogDesign.Builder extends java.lang.Object
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Constructor Summary
Constructors Constructor Description Builder()
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description void
addParameter(VerilogParameter.Type type, java.lang.String name, ru.ispras.fortress.data.Data data)
void
addProcess(VerilogInstantiator instantiator)
void
addSvaInstance(ru.ispras.fortress.expression.NodeVariable instVariable, VerilogInstantiator instantiator)
void
addVariable(VerilogVariable variable, VerilogInstantiator instantiator)
VerilogDesign
build()
Calculates the variables' bit sizes and modifies the expressions.java.util.Map<java.lang.String,VerilogParameter>
getParameters()
void
setName(java.lang.String name)
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Method Detail
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setName
public void setName(java.lang.String name)
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getParameters
public java.util.Map<java.lang.String,VerilogParameter> getParameters()
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addParameter
public void addParameter(VerilogParameter.Type type, java.lang.String name, ru.ispras.fortress.data.Data data)
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addVariable
public void addVariable(VerilogVariable variable, VerilogInstantiator instantiator)
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addProcess
public void addProcess(VerilogInstantiator instantiator)
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addSvaInstance
public void addSvaInstance(ru.ispras.fortress.expression.NodeVariable instVariable, VerilogInstantiator instantiator)
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build
public VerilogDesign build()
Calculates the variables' bit sizes and modifies the expressions.- Returns:
- the elaborated design.
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