Package ru.ispras.verilog.parser.sva
Class SvaDeclaration
- java.lang.Object
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- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
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- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
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- ru.ispras.verilog.parser.model.VerilogNode
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- ru.ispras.verilog.parser.sva.SvaDeclaration
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- Direct Known Subclasses:
SvaPropertyDeclaration
,SvaSequenceDeclaration
public abstract class SvaDeclaration extends VerilogNode
SvaDeclaration
represents the declaration of a property or a sequence.
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Nested Class Summary
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
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Field Summary
Fields Modifier and Type Field Description protected java.util.List<SvaPort>
ports
Ports.protected java.util.List<VerilogDeclaration>
variables
Variable declarations.
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Constructor Summary
Constructors Modifier Constructor Description protected
SvaDeclaration(VerilogNode.Tag tag, java.util.EnumSet<VerilogNode.Tag> childrenTags, AbstractNode.NodeKind kind, VerilogNode parent)
protected
SvaDeclaration(SvaDeclaration other, VerilogNode parent)
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description void
addDeclaration(VerilogDeclaration variable)
Adds a variable to the property variable list.void
addPort(SvaPort port)
Adds a port to the property ports list.java.util.List<SvaPort>
getPorts()
Returns the property ports.java.util.List<VerilogDeclaration>
getVariables()
Returns the property variables.-
Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
clone, getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
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Field Detail
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ports
protected java.util.List<SvaPort> ports
Ports.
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variables
protected java.util.List<VerilogDeclaration> variables
Variable declarations.
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Constructor Detail
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SvaDeclaration
protected SvaDeclaration(VerilogNode.Tag tag, java.util.EnumSet<VerilogNode.Tag> childrenTags, AbstractNode.NodeKind kind, VerilogNode parent)
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SvaDeclaration
protected SvaDeclaration(SvaDeclaration other, VerilogNode parent)
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Method Detail
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getVariables
public java.util.List<VerilogDeclaration> getVariables()
Returns the property variables.- Returns:
- the list of property variables.
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addDeclaration
public void addDeclaration(VerilogDeclaration variable)
Adds a variable to the property variable list.- Parameters:
variable
- - the specified variable declaration.
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getPorts
public java.util.List<SvaPort> getPorts()
Returns the property ports.- Returns:
- the list of ports.
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addPort
public void addPort(SvaPort port)
Adds a port to the property ports list.- Parameters:
port
- - the specified port.
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