Package ru.ispras.verilog.parser.model
Class VerilogAssignment
- java.lang.Object
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- ru.ispras.verilog.parser.core.AbstractSymbolTable<Tag>
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- ru.ispras.verilog.parser.core.AbstractNode<VerilogNode.Tag>
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- ru.ispras.verilog.parser.model.VerilogNode
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- ru.ispras.verilog.parser.model.VerilogAssignment
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public final class VerilogAssignment extends VerilogNode
VerilogAssignment
represents assignments.
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Nested Class Summary
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.model.VerilogNode
VerilogNode.Tag
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Nested classes/interfaces inherited from class ru.ispras.verilog.parser.core.AbstractNode
AbstractNode.NodeKind
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Field Summary
Fields Modifier and Type Field Description static VerilogNode.Tag
TAG
static java.util.EnumSet<VerilogNode.Tag>
TAGS_CHILDREN
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Constructor Summary
Constructors Constructor Description VerilogAssignment(VerilogAssignment other, VerilogNode parent)
Creates a copy of the assignment.VerilogAssignment(VerilogNode parent)
Creates an assignment.
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Method Summary
All Methods Instance Methods Concrete Methods Modifier and Type Method Description void
addReference(VerilogReference reference)
Adds the reference to the l-value.VerilogAssignment
clone()
Clones the symbol table.ru.ispras.fortress.expression.Node
getLhsNode()
Returns the expression representation of the assignment's left hand side.java.util.List<VerilogReference>
getReferences()
Returns the l-value (reference) of the assignment.VerilogMinTypMax
getRhsExpression()
Returns the r-value (expression) of the assignment.void
setRhsExpression(VerilogMinTypMax expression)
Sets the r-value (expression) of the assignment.-
Methods inherited from class ru.ispras.verilog.parser.model.VerilogNode
getAttributes, getParentNode, isActivity, isAssertionStatement, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPropertyDeclaration, isPulseStyle, isSequenceDeclaration, isShowCancelled, isSpecify, isSvaPort, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractNode
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
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Methods inherited from class ru.ispras.verilog.parser.core.AbstractSymbolTable
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
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Field Detail
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TAG
public static final VerilogNode.Tag TAG
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TAGS_CHILDREN
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
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Constructor Detail
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VerilogAssignment
public VerilogAssignment(VerilogNode parent)
Creates an assignment.- Parameters:
parent
- the parent node.
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VerilogAssignment
public VerilogAssignment(VerilogAssignment other, VerilogNode parent)
Creates a copy of the assignment.- Parameters:
other
- the assignment to be copied.parent
- the parent node.
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Method Detail
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getReferences
public java.util.List<VerilogReference> getReferences()
Returns the l-value (reference) of the assignment.- Returns:
- the reference.
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addReference
public void addReference(VerilogReference reference)
Adds the reference to the l-value.- Parameters:
reference
- the reference to be added.
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getLhsNode
public ru.ispras.fortress.expression.Node getLhsNode()
Returns the expression representation of the assignment's left hand side.- Returns:
- the left hand side.
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getRhsExpression
public VerilogMinTypMax getRhsExpression()
Returns the r-value (expression) of the assignment.- Returns:
- the expression.
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setRhsExpression
public void setRhsExpression(VerilogMinTypMax expression)
Sets the r-value (expression) of the assignment.- Parameters:
expression
- the expression to be set.
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clone
public VerilogAssignment clone()
Description copied from class:AbstractSymbolTable
Clones the symbol table.- Specified by:
clone
in classVerilogNode
- Returns:
- a copy of the symbol table.
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