public abstract class VerilogNode extends AbstractNode<VerilogNode.Tag>
VerilogNode
represents a basic AST node for the Verilog HDL.Modifier and Type | Class and Description |
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static class |
VerilogNode.Tag
VerilogNode.Tag contains the node types. |
AbstractNode.NodeKind
Modifier | Constructor and Description |
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protected |
VerilogNode(VerilogNode.Tag tag,
java.util.EnumSet<VerilogNode.Tag> childrenTags,
AbstractNode.NodeKind kind)
Creates a top-level node (i.e.
|
protected |
VerilogNode(VerilogNode.Tag tag,
java.util.EnumSet<VerilogNode.Tag> childrenTags,
AbstractNode.NodeKind kind,
VerilogNode parent)
Creates a node.
|
protected |
VerilogNode(VerilogNode other,
VerilogNode parent)
Creates a copy of the node.
|
Modifier and Type | Method and Description |
---|---|
abstract VerilogNode |
clone()
Clones the symbol table.
|
java.util.Collection<VerilogAttribute> |
getAttributes()
Returns the attributes of the node.
|
VerilogNode |
getParentNode()
Returns the parent node.
|
boolean |
isActivity()
Checks whether the node is
ACTIVITY . |
boolean |
isAssign()
Checks whether the node is
ASSIGN . |
boolean |
isAssignment()
Checks whether the node is
ASSIGNMENT . |
boolean |
isAssignStatement()
Checks whether the node is
ASSIGN_STATEMENT . |
boolean |
isAttribute()
Checks whether the node is
ATTRIBUTE . |
boolean |
isBlockGenerate()
Checks whether the node is
BLOCK_GENERATE . |
boolean |
isBlockStatement()
Checks whether the node is
BLOCK_STATEMENT . |
boolean |
isCaseGenerate()
Checks whether the node is
CASE_GENERATE . |
boolean |
isCaseGenerateItem()
Checks whether the node is
CASE_GENERATE_ITEM . |
boolean |
isCaseStatement()
Checks whether the node is
CASE_STATEMENT . |
boolean |
isCaseStatementItem()
Checks whether the node is
CASE_STATEMENT_ITEM . |
boolean |
isCode()
Checks whether the node is
CODE . |
boolean |
isConnection()
Checks whether the node is
PORT_CONNECTION . |
boolean |
isDeclaration()
Checks whether the node is
DECLARATION . |
boolean |
isDelayedStatement()
Checks whether the node is
DELAYED_STATEMENT . |
boolean |
isDisableStatement()
Checks whether the node is
DISABLE_STATEMENT . |
boolean |
isGenerate()
Checks whether the node is
GENERATE . |
boolean |
isIfGenerate()
Checks whether the node is
IF_GENERATE . |
boolean |
isIfGenerateBranch()
Checks whether the node is
IF_GENERATE_BRANCH . |
boolean |
isIfStatement()
Checks whether the node is
IF_STATEMENT . |
boolean |
isIfStatementBranch()
Checks whether the node is
IF_STATEMENT_BRANCH . |
boolean |
isInstantiation()
Checks whether the node is
INSTANTIATION . |
boolean |
isLoopGenerate()
Checks whether the node is
LOOP_GENERATE . |
boolean |
isLoopStatement()
Checks whether the node is
LOOP_STATEMENT . |
boolean |
isModule()
Checks whether the node is
MODULE . |
boolean |
isNullStatement()
Checks whether the node is
NULL_STATEMENT . |
boolean |
isPathDeclaration()
Checks whether the node is
PATH_DECLARATION . |
boolean |
isPort()
Checks whether the node is
PORT . |
boolean |
isPortConnection()
Checks whether the node is
PORT_CONNECTION . |
boolean |
isProcedure()
Checks whether the node is
PROCEDURE . |
boolean |
isPulseStyle()
Checks whether the node is
PULSE_STYLE . |
boolean |
isShowCancelled()
Checks whether the node is
SHOW_CANCELLED . |
boolean |
isSpecify()
Checks whether the node is
SPECIFY . |
boolean |
isTable()
Checks whether the node is
TABLE . |
boolean |
isTableEntry()
Checks whether the node is
TABLE_ENTRY . |
boolean |
isTaskStatement()
Checks whether the node is
TASK_STATEMENT . |
boolean |
isTriggerStatement()
Checks whether the node is
TRIGGER_STATEMENT . |
boolean |
isWaitStatement()
Checks whether the node is
WAIT_STATEMENT . |
void |
setAttributes(java.util.Collection<VerilogAttribute> attributes)
Sets attributes of the node.
|
static java.util.EnumSet<VerilogNode.Tag> |
union(java.util.EnumSet<VerilogNode.Tag> lhs,
java.util.EnumSet<VerilogNode.Tag> rhs)
Unites two sets of tags.
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add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
protected VerilogNode(VerilogNode.Tag tag, java.util.EnumSet<VerilogNode.Tag> childrenTags, AbstractNode.NodeKind kind, VerilogNode parent)
tag
- the tag.childrenTags
- the tags of admissible children.kind
- the kind.parent
- the parent node.protected VerilogNode(VerilogNode.Tag tag, java.util.EnumSet<VerilogNode.Tag> childrenTags, AbstractNode.NodeKind kind)
null
parent).tag
- the tag.childrenTags
- the tags of admissible children.kind
- the kind.protected VerilogNode(VerilogNode other, VerilogNode parent)
other
- the node to be copied.parent
- the parent node to be set.public static java.util.EnumSet<VerilogNode.Tag> union(java.util.EnumSet<VerilogNode.Tag> lhs, java.util.EnumSet<VerilogNode.Tag> rhs)
lhs
- the set of tags.rhs
- the set of tags.public boolean isCode()
CODE
.true
iff the node is CODE
.public boolean isModule()
MODULE
.true
iff the node is MODULE
.public boolean isPort()
PORT
.true
iff the node is PORT
.public boolean isDeclaration()
DECLARATION
.true
iff the node is DECLARATION
.public boolean isActivity()
ACTIVITY
.true
iff the node is ACTIVITY
.public boolean isAssign()
ASSIGN
.true
iff the node is ASSIGN
.public boolean isAssignment()
ASSIGNMENT
.true
iff the node is ASSIGNMENT
.public boolean isInstantiation()
INSTANTIATION
.true
iff the node is INSTANTIATION
.public boolean isConnection()
PORT_CONNECTION
.true
iff the node is PORT_CONNECTION
.public boolean isProcedure()
PROCEDURE
.true
iff the node is PROCEDURE
.public boolean isTable()
TABLE
.true
iff the node is TABLE
.public boolean isTableEntry()
TABLE_ENTRY
.true
iff the node is TABLE_ENTRY
.public boolean isNullStatement()
NULL_STATEMENT
.true
iff the node is NULL_STATEMENT
.public boolean isAssignStatement()
ASSIGN_STATEMENT
.true
iff the node is ASSIGN_STATEMENT
.public boolean isTaskStatement()
TASK_STATEMENT
.true
iff the node is TASK_STATEMENT
.public boolean isWaitStatement()
WAIT_STATEMENT
.true
iff the node is WAIT_STATEMENT
.public boolean isDisableStatement()
DISABLE_STATEMENT
.true
iff the node is DISABLE_STATEMENT
.public boolean isTriggerStatement()
TRIGGER_STATEMENT
.true
iff the node is TRIGGER_STATEMENT
.public boolean isDelayedStatement()
DELAYED_STATEMENT
.true
iff the node is DELAYED_STATEMENT
.public boolean isIfStatement()
IF_STATEMENT
.true
iff the node is IF_STATEMENT
.public boolean isIfStatementBranch()
IF_STATEMENT_BRANCH
.true
iff the node is IF_STATEMENT_BRANCH
.public boolean isCaseStatement()
CASE_STATEMENT
.true
iff the node is CASE_STATEMENT
.public boolean isCaseStatementItem()
CASE_STATEMENT_ITEM
.true
iff the node is CASE_STATEMENT_ITEM
.public boolean isLoopStatement()
LOOP_STATEMENT
.true
iff the node is LOOP_STATEMENT
.public boolean isBlockStatement()
BLOCK_STATEMENT
.true
iff the node is BLOCK_STATEMENT
.public boolean isGenerate()
GENERATE
.true
iff the node is GENERATE
.public boolean isIfGenerate()
IF_GENERATE
.true
iff the node is IF_GENERATE
.public boolean isIfGenerateBranch()
IF_GENERATE_BRANCH
.true
iff the node is IF_GENERATE_BRANCH
.public boolean isCaseGenerate()
CASE_GENERATE
.true
iff the node is CASE_GENERATE
.public boolean isCaseGenerateItem()
CASE_GENERATE_ITEM
.true
iff the node is CASE_GENERATE_ITEM
.public boolean isLoopGenerate()
LOOP_GENERATE
.true
iff the node is LOOP_GENERATE
.public boolean isBlockGenerate()
BLOCK_GENERATE
.true
iff the node is BLOCK_GENERATE
.public boolean isSpecify()
SPECIFY
.true
iff the node is SPECIFY
.public boolean isPulseStyle()
PULSE_STYLE
.true
iff the node is PULSE_STYLE
.public boolean isShowCancelled()
SHOW_CANCELLED
.true
iff the node is SHOW_CANCELLED
.public boolean isPathDeclaration()
PATH_DECLARATION
.true
iff the node is PATH_DECLARATION
.public boolean isAttribute()
ATTRIBUTE
.true
iff the node is ATTRIBUTE
.public boolean isPortConnection()
PORT_CONNECTION
.true
iff the node is PORT_CONNECTION
.public java.util.Collection<VerilogAttribute> getAttributes()
public void setAttributes(java.util.Collection<VerilogAttribute> attributes)
attributes
- the attributes to be set.public VerilogNode getParentNode()
public abstract VerilogNode clone()
AbstractSymbolTable
clone
in class AbstractNode<VerilogNode.Tag>