public final class VerilogLoopGenerate extends VerilogNode
VerilogLoopGenerate
represents generate loops.VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogLoopGenerate(VerilogLoopGenerate other,
VerilogNode parent)
Creates a copy of the generate loop.
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VerilogLoopGenerate(VerilogNode parent)
Creates a generate loop.
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Modifier and Type | Method and Description |
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VerilogLoopGenerate |
clone()
Clones the symbol table.
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VerilogExpression |
getExpression()
Returns the continue condition of the loop.
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VerilogBlockGenerate |
getGenerate()
Returns the loop body.
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VerilogAssignment |
getInitialization()
Returns the initialization assignment of the loop.
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VerilogAssignment |
getIteration()
Returns the iteration assignment of the loop.
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void |
setExpression(VerilogExpression expression)
Sets the continue condition of the loop.
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void |
setGenerate(VerilogBlockGenerate generate)
Sets the loop body.
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void |
setInitialization(VerilogAssignment initialization)
Sets the initialization assignment of the loop.
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void |
setIteration(VerilogAssignment iteration)
Sets the iteration assignment of the loop.
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getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogLoopGenerate(VerilogNode parent)
parent
- the parent node.public VerilogLoopGenerate(VerilogLoopGenerate other, VerilogNode parent)
other
- the generate loop to be copied.parent
- the parent node.public VerilogAssignment getInitialization()
public void setInitialization(VerilogAssignment initialization)
initialization
- the assignment to be set.public VerilogExpression getExpression()
public void setExpression(VerilogExpression expression)
expression
- the condition to be set.public VerilogAssignment getIteration()
public void setIteration(VerilogAssignment iteration)
iteration
- the assignment to be set.public VerilogBlockGenerate getGenerate()
public void setGenerate(VerilogBlockGenerate generate)
generate
- the body to be set.public VerilogLoopGenerate clone()
AbstractSymbolTable
clone
in class VerilogNode