public final class VerilogElaborator extends VerilogSyntaxBackend
VerilogElaborator
implements a simple elaboration engine.
[IEEE Std 1364-2005] 12.8 Elaboration Elaboration is the process that occurs between parsing and simulation. It binds modules to module instances, builds the model hierarchy, computes parameter values, resolves hierarchical names, establishes net connectivity, and prepares all of this for simulation. With the addition of generate constructs, the order in which these tasks occur becomes significant.
Constructor and Description |
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VerilogElaborator(java.lang.String name)
Creates an elaboration engine.
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VerilogElaborator(java.lang.String name,
java.lang.String moduleName)
Creates an elaboration engine.
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Modifier and Type | Method and Description |
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VerilogDesign |
getDesign()
Returns the elaborated design.
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java.lang.String |
getModuleName()
Returns the name of the module to be elaborated.
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void |
setModuleName(java.lang.String moduleName)
Sets the name of the module to be elaborated.
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void |
start(VerilogNode rootNode)
Processes the abstract syntax tree (AST).
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getName
public VerilogElaborator(java.lang.String name)
name
- the back-end name.public VerilogElaborator(java.lang.String name, java.lang.String moduleName)
name
- the back-end name.moduleName
- the name of the module to be elaborated.public java.lang.String getModuleName()
public void setModuleName(java.lang.String moduleName)
moduleName
- the module name.public VerilogDesign getDesign()
public void start(VerilogNode rootNode)
VerilogSyntaxBackend
start
in class VerilogSyntaxBackend
rootNode
- the AST's root.