public final class VerilogPort extends VerilogNode
VerilogPort
represents port declarations.VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogPort(VerilogNode parent)
Creates a port.
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VerilogPort(VerilogPort other,
VerilogNode parent)
Creates a copy of the port.
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Modifier and Type | Method and Description |
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void |
addReference(VerilogReference reference)
Adds the reference to the port references.
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VerilogPort |
clone()
Clones the symbol table.
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java.util.List<VerilogReference> |
getReferences()
Returns the port references.
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getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogPort(VerilogNode parent)
parent
- the parent node.public VerilogPort(VerilogPort other, VerilogNode parent)
other
- the port to be copied.parent
- the parent node.public java.util.List<VerilogReference> getReferences()
public void addReference(VerilogReference reference)
reference
- the reference to be added.public VerilogPort clone()
AbstractSymbolTable
clone
in class VerilogNode