public final class VerilogModule extends VerilogNode
VerilogModule
represents the abstract syntax of the module declaration.Modifier and Type | Class and Description |
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static class |
VerilogModule.Type
VerilogModule.Type contains the module types. |
VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogModule(VerilogModule other,
VerilogNode parent)
Creates a copy of the module.
|
VerilogModule(VerilogNode parent)
Creates a module.
|
Modifier and Type | Method and Description |
---|---|
void |
addDeclaration(VerilogDeclaration declaration)
Adds the declaration to the module.
|
void |
addPort(VerilogPort port)
Adds the port to the signature of the module.
|
VerilogModule |
clone()
Clones the symbol table.
|
java.util.List<VerilogPort> |
getPorts()
Returns the signature of the module (i.e., the list of its ports).
|
VerilogModule.Type |
getType()
Returns the type of the module.
|
boolean |
isGatePrimitive()
Checks whether the module is
GATE_PRIMITIVE . |
boolean |
isMacromodule()
Checks whether the module is
MACROMODULE . |
boolean |
isModule()
Checks whether the module is
MODULE . |
boolean |
isUserPrimitive()
Checks whether the module is
USER_PRIMITIVE . |
void |
setGatePrimitive()
Sets the type of the module to
GATE_PRIMITIVE . |
void |
setMacromodule()
Sets the type of the module to
MACROMODULE . |
void |
setModule()
Sets the type of the module to
MODULE . |
void |
setType(VerilogModule.Type type)
Sets the type of the module.
|
void |
setUserPrimitive()
Sets the type of the module to
USER_PRIMITIVE . |
getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogModule(VerilogNode parent)
parent
- the parent node.public VerilogModule(VerilogModule other, VerilogNode parent)
other
- the module to be copied.parent
- the parent node.public VerilogModule.Type getType()
public void setType(VerilogModule.Type type)
type
- the type to be set.public boolean isModule()
MODULE
.isModule
in class VerilogNode
true
iff the module is MODULE
.public boolean isMacromodule()
MACROMODULE
.true
iff the module is MACROMODULE
.public boolean isUserPrimitive()
USER_PRIMITIVE
.true
iff the module is USER_PRIMITIVE
.public boolean isGatePrimitive()
GATE_PRIMITIVE
.true
iff the module is GATE_PRIMITIVE
.public void setModule()
MODULE
.public void setMacromodule()
MACROMODULE
.public void setUserPrimitive()
USER_PRIMITIVE
.public void setGatePrimitive()
GATE_PRIMITIVE
.public java.util.List<VerilogPort> getPorts()
public void addPort(VerilogPort port)
port
- the port to be added.public void addDeclaration(VerilogDeclaration declaration)
declaration
- the declaration to be added.public VerilogModule clone()
AbstractSymbolTable
clone
in class VerilogNode