public final class VerilogPathDeclaration extends VerilogNode
VerilogPathDeclaration
represents path declarations.Modifier and Type | Class and Description |
---|---|
static class |
VerilogPathDeclaration.Type
VerilogPathDeclaration.Type contains the path declaration types. |
VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
---|---|
static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
---|
VerilogPathDeclaration(VerilogNode parent)
Creates a path declaration.
|
VerilogPathDeclaration(VerilogPathDeclaration other,
VerilogNode parent)
Creates a copy of path declaration.
|
Modifier and Type | Method and Description |
---|---|
VerilogPathDeclaration |
clone()
Clones the symbol table.
|
VerilogDelay |
getDelay()
Returns the path delay value (only for
SIMPLE ). |
VerilogPathDescription |
getDescription()
Returns the path description (only for
SIMPLE ). |
VerilogExpression |
getExpression()
Returns the condition of the path declaration (only for
IF ). |
VerilogPathDeclaration |
getThen()
Returns the child path declaration (only for
IF and IF_NONE ). |
VerilogPathDeclaration.Type |
getType()
Returns the type of the path declaration.
|
boolean |
isIf()
Checks whether the path declaration is
IF . |
boolean |
isIfNone()
Checks whether the path declaration is
IF_NONE . |
void |
setDelay(VerilogDelay delay)
Sets the path delay value (only for
SIMPLE ). |
void |
setDescription(VerilogPathDescription description)
Sets the path description (only for
SIMPLE ). |
void |
setExpression(VerilogExpression expression)
Sets the condition of the path declaration (only for
IF ). |
void |
setIf()
Sets the path declaration type to
IF . |
void |
setIfNone()
Sets the path declaration type to
IF_NONE . |
void |
setThen(VerilogPathDeclaration then)
Sets the child path declaration (only for
IF ). |
void |
setType(VerilogPathDeclaration.Type type)
Sets the type of the path declaration.
|
getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogPathDeclaration(VerilogNode parent)
parent
- the parent node.public VerilogPathDeclaration(VerilogPathDeclaration other, VerilogNode parent)
other
- the path declaration to be copied.parent
- the parent node.public VerilogPathDeclaration.Type getType()
public void setType(VerilogPathDeclaration.Type type)
type
- the type to be set.public boolean isIf()
IF
.true
iff the path declaration is IF
.public boolean isIfNone()
IF_NONE
.true
iff the path declaration is IF_NONE
.public void setIf()
IF
.public void setIfNone()
IF_NONE
.public VerilogExpression getExpression()
IF
).public void setExpression(VerilogExpression expression)
IF
).expression
- the condition to be set.public VerilogPathDescription getDescription()
SIMPLE
).public void setDescription(VerilogPathDescription description)
SIMPLE
).description
- the description to be set.public VerilogDelay getDelay()
SIMPLE
).public void setDelay(VerilogDelay delay)
SIMPLE
).delay
- the delay to be set.public VerilogPathDeclaration getThen()
IF
and IF_NONE
).public void setThen(VerilogPathDeclaration then)
IF
).then
- the declaration to be set.public VerilogPathDeclaration clone()
AbstractSymbolTable
clone
in class VerilogNode