public abstract class VerilogStatement extends VerilogNode
VerilogStatement
represents statements.VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static java.util.EnumSet<VerilogNode.Tag> |
TAGS
All possible statements.
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Constructor and Description |
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VerilogStatement(VerilogNode.Tag tag,
java.util.EnumSet<VerilogNode.Tag> childrenTags,
AbstractNode.NodeKind kind,
VerilogNode parent)
Creates a statement.
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VerilogStatement(VerilogNode.Tag tag,
VerilogNode parent)
Creates a statement with no children.
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VerilogStatement(VerilogNode parent)
Creates a null statement.
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VerilogStatement(VerilogStatement other,
VerilogNode parent)
Creates a copy of the statement.
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Modifier and Type | Method and Description |
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abstract VerilogStatement |
clone()
Clones the symbol table.
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getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final java.util.EnumSet<VerilogNode.Tag> TAGS
public VerilogStatement(VerilogNode.Tag tag, java.util.EnumSet<VerilogNode.Tag> childrenTags, AbstractNode.NodeKind kind, VerilogNode parent)
tag
- the statement tag.childrenTags
- the children tags.kind
- the statement kind.parent
- the parent node.public VerilogStatement(VerilogNode.Tag tag, VerilogNode parent)
tag
- the statement tag.parent
- the parent node.public VerilogStatement(VerilogNode parent)
parent
- the parent node.public VerilogStatement(VerilogStatement other, VerilogNode parent)
other
- the statement to be copied.parent
- the parent node.public abstract VerilogStatement clone()
AbstractSymbolTable
clone
in class VerilogNode