public final class VerilogPulseStyle extends VerilogNode
VerilogPulseStyle
represents pulse style specifications.Modifier and Type | Class and Description |
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static class |
VerilogPulseStyle.Type
VerilogPulseStyle contains the pulse style types. |
VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogPulseStyle(VerilogNode parent)
Creates a pulse style specification.
|
VerilogPulseStyle(VerilogPulseStyle other,
VerilogNode parent)
Creates a copy of the pulse style specification.
|
Modifier and Type | Method and Description |
---|---|
void |
addReference(VerilogReference reference)
Adds the reference to the pulse style specification.
|
VerilogPulseStyle |
clone()
Clones the symbol table.
|
java.util.List<VerilogReference> |
getReferences()
Returns the references of the pulse style specification.
|
VerilogPulseStyle.Type |
getType()
Returns the type of the pulse style specification.
|
boolean |
isOnDetect()
Checks whether the pulse style is
ON_DETECT . |
boolean |
isOnEvent()
Checks whether the pulse style is
ON_EVENT . |
void |
setOnDetect()
Sets a pulse style type to
ON_DETECT . |
void |
setOnEvent()
Sets a pulse style type to
ON_EVENT . |
void |
setType(VerilogPulseStyle.Type type)
Sets the type of the pulse style specification.
|
getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogPulseStyle(VerilogNode parent)
parent
- the parent node.public VerilogPulseStyle(VerilogPulseStyle other, VerilogNode parent)
other
- the pulse style specification to be copied.parent
- the parent node.public VerilogPulseStyle.Type getType()
public void setType(VerilogPulseStyle.Type type)
type
- the type to be set.public boolean isOnEvent()
ON_EVENT
.true
iff the pulse style is ON_EVENT
.public boolean isOnDetect()
ON_DETECT
.true
iff the pulse style is ON_DETECT
.public void setOnEvent()
ON_EVENT
.public void setOnDetect()
ON_DETECT
.public java.util.List<VerilogReference> getReferences()
public void addReference(VerilogReference reference)
reference
- the reference to be added.public VerilogPulseStyle clone()
AbstractSymbolTable
clone
in class VerilogNode