public final class VerilogDefineParameter extends VerilogNode
VerilogAssign
represents parameter definition statements (defparam
).VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
---|---|
static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
---|
VerilogDefineParameter(VerilogDefineParameter other,
VerilogNode parent)
Constructs a copy of the parameter definition statement.
|
VerilogDefineParameter(VerilogNode parent)
Constructs a parameter definition statement.
|
Modifier and Type | Method and Description |
---|---|
VerilogDefineParameter |
clone()
Clones the symbol table.
|
VerilogMinTypMax |
getExpression()
Returns the parameter expression.
|
VerilogPath |
getPath()
Returns the parameter path.
|
void |
setExpression(VerilogMinTypMax expression)
Sets the parameter expression.
|
void |
setPath(VerilogPath path)
Sets the parameter path.
|
getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogDefineParameter(VerilogNode parent)
parent
- the parent node.public VerilogDefineParameter(VerilogDefineParameter other, VerilogNode parent)
other
- the parameter definition statement to be copied.parent
- the parent node.public VerilogPath getPath()
public void setPath(VerilogPath path)
path
- the path to be set.public VerilogMinTypMax getExpression()
public void setExpression(VerilogMinTypMax expression)
expression
- the expression to be set.public VerilogDefineParameter clone()
AbstractSymbolTable
clone
in class VerilogNode