public final class VerilogIfStatement extends VerilogStatement
VerilogIfStatement
represents if-then-else statements.VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
TAGS
Constructor and Description |
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VerilogIfStatement(VerilogIfStatement other,
VerilogNode parent)
Creates a copy of the if-then-else statement.
|
VerilogIfStatement(VerilogNode parent)
Creates an if-then-else statement.
|
Modifier and Type | Method and Description |
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VerilogIfStatement |
clone()
Clones the symbol table.
|
VerilogStatement |
getElseStatement()
Returns the statement related to the branch
else . |
VerilogExpression |
getExpression()
Returns the condition.
|
VerilogStatement |
getThenStatement()
Returns the statement related to the branch
then . |
void |
setElseStatement(VerilogStatement elseStatement)
Sets the statement related to the branch
else . |
void |
setExpression(VerilogExpression expression)
Sets the condition.
|
void |
setThenStatement(VerilogStatement thenStatement)
Sets the statement related to the branch
then . |
getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogIfStatement(VerilogNode parent)
parent
- the parent node.public VerilogIfStatement(VerilogIfStatement other, VerilogNode parent)
other
- the if-then-else statement to be copied.parent
- the parent node.public VerilogExpression getExpression()
public void setExpression(VerilogExpression expression)
expression
- the condition.public VerilogStatement getThenStatement()
then
.then
's statement.public void setThenStatement(VerilogStatement thenStatement)
then
.thenStatement
- the statement to be set.public VerilogStatement getElseStatement()
else
.else
's statement.public void setElseStatement(VerilogStatement elseStatement)
else
.elseStatement
- the statement to be set.public VerilogIfStatement clone()
AbstractSymbolTable
clone
in class VerilogStatement