public final class VerilogAssign extends VerilogNode
VerilogAssign
represents continuous assignments (assign
).VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
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static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
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VerilogAssign(VerilogAssign other,
VerilogNode parent)
Creates a copy of the continuous assignment.
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VerilogAssign(VerilogNode parent)
Constructs a continuous assignment.
|
Modifier and Type | Method and Description |
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VerilogAssign |
clone()
Clones the symbol table.
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VerilogAssignment |
getAssignment()
Returns the assignment itself.
|
VerilogDelay |
getDelay()
Returns the assignment delay.
|
VerilogStrength |
getStrength()
Returns the drive strength.
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void |
setAssignment(VerilogAssignment assignment)
Sets the assignment.
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void |
setDelay(VerilogDelay delay)
Sets the assignment delay.
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void |
setStrength(VerilogStrength strength)
Sets the drive strength.
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getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogAssign(VerilogNode parent)
parent
- the parent node.public VerilogAssign(VerilogAssign other, VerilogNode parent)
other
- the continuous assignment to be copied.parent
- the parent node.public VerilogStrength getStrength()
public void setStrength(VerilogStrength strength)
strength
- the strength to be set.public VerilogDelay getDelay()
public void setDelay(VerilogDelay delay)
delay
- the delay to be set.public VerilogAssignment getAssignment()
public void setAssignment(VerilogAssignment assignment)
assignment
- the assignment to be set.public VerilogAssign clone()
AbstractSymbolTable
clone
in class VerilogNode