Class | Description |
---|---|
VerilogActivity |
VerilogActivity represents processes. |
VerilogAssign |
VerilogAssign represents continuous assignments (assign ). |
VerilogAssignment |
VerilogAssignment represents assignments. |
VerilogAssignStatement |
VerilogAssignment represents assignment statements. |
VerilogAttribute |
VerilogAttribute represents attributes. |
VerilogBlockGenerate |
VerilogBlockGenerate represents generate blocks. |
VerilogBlockStatement |
VerilogBlockStatement represents block statements. |
VerilogCaseGenerate |
VerilogCaseGenerate represents generate case constructs. |
VerilogCaseGenerateItem |
VerilogCaseGenerateItem represents generate case items. |
VerilogCaseStatement |
VerilogCaseStatement represents case statements. |
VerilogCaseStatementItem |
VerilogCaseStatementItem represents case statement items. |
VerilogCode |
VerilogCode represents source code. |
VerilogDeclaration |
VerilogDeclaration represents declarations. |
VerilogDefineParameter |
VerilogAssign represents parameter definition statements (defparam ). |
VerilogDelayedStatement |
VerilogDelayedStatement represents delayed statements. |
VerilogDisableStatement |
VerilogDisableStatement represents disable statements. |
VerilogGenerate |
VerilogGenerate represents the abstract syntax of the generate construct. |
VerilogIfGenerate |
VerilogIfGenerate represents if-then-else generate constructs. |
VerilogIfGenerateBranch |
VerilogIfGenerateBranch represents if-then-else generate branches (then and else). |
VerilogIfStatement |
VerilogIfStatement represents if-then-else statements. |
VerilogIfStatementBranch |
VerilogIfStatementBranch represents if-then-else statement branches (then and else). |
VerilogInstantiation |
VerilogInstantiation represents module instantiations. |
VerilogLoopGenerate |
VerilogLoopGenerate represents generate loops. |
VerilogLoopStatement |
VerilogLoopStatement represents loop statements. |
VerilogModule |
VerilogModule represents the abstract syntax of the module declaration. |
VerilogNode |
VerilogNode represents a basic AST node for the Verilog HDL. |
VerilogNullStatement |
VerilogNullStatement represents null statements. |
VerilogPathDeclaration |
VerilogPathDeclaration represents path declarations. |
VerilogPort |
VerilogPort represents port declarations. |
VerilogPortConnection |
VerilogPortConnection represents port connections. |
VerilogProcedure |
VerilogProcedure represents functions and tasks. |
VerilogPulseStyle |
VerilogPulseStyle represents pulse style specifications. |
VerilogShowCancelled |
VerilogShowCancelled represents show-cancelled constructs. |
VerilogSpecify |
VerilogSpecify represents the abstract syntax of the specify construct. |
VerilogStatement |
VerilogStatement represents statements. |
VerilogTable |
VerilogTable represents UDP tables. |
VerilogTableEntry |
VerilogTableEntry represents UDP table entries. |
VerilogTaskStatement |
VerilogTaskStatement represents task statements. |
VerilogTriggerStatement |
VerilogTriggerStatement represents trigger statements. |
VerilogWaitStatement |
VerilogWaitStatement represents the abstract syntax of the wait statement. |