public final class VerilogCaseGenerate extends VerilogNode
VerilogCaseGenerate
represents generate case constructs.VerilogNode.Tag
AbstractNode.NodeKind
Modifier and Type | Field and Description |
---|---|
static VerilogNode.Tag |
TAG |
static java.util.EnumSet<VerilogNode.Tag> |
TAGS_CHILDREN |
Constructor and Description |
---|
VerilogCaseGenerate(VerilogCaseGenerate other,
VerilogNode parent)
Creates a copy of the generate case construct.
|
VerilogCaseGenerate(VerilogNode parent)
Creates a generate case construct.
|
Modifier and Type | Method and Description |
---|---|
void |
addCase(VerilogCaseGenerateItem item)
Adds the case to the case selection construct.
|
VerilogCaseGenerate |
clone()
Clones the symbol table.
|
java.util.List<VerilogCaseGenerateItem> |
getCases()
Returns the cases.
|
VerilogExpression |
getExpression()
Returns the case selection expression.
|
void |
setExpression(VerilogExpression expression)
Sets the case selection expression.
|
getAttributes, getParentNode, isActivity, isAssign, isAssignment, isAssignStatement, isAttribute, isBlockGenerate, isBlockStatement, isCaseGenerate, isCaseGenerateItem, isCaseStatement, isCaseStatementItem, isCode, isConnection, isDeclaration, isDelayedStatement, isDisableStatement, isGenerate, isIfGenerate, isIfGenerateBranch, isIfStatement, isIfStatementBranch, isInstantiation, isLoopGenerate, isLoopStatement, isModule, isNullStatement, isPathDeclaration, isPort, isPortConnection, isProcedure, isPulseStyle, isShowCancelled, isSpecify, isTable, isTableEntry, isTaskStatement, isTriggerStatement, isWaitStatement, setAttributes, union
add, find, getFullName, getName, getParent, getTag, hasName, hasScope, isTransparent, items, items, items, remove, replace, setName, setParent, setRedefinitionHandler, setTag, toString
addAll, findAroundRecursively, findAroundRecursively, findRecursively, findRecursively, getUpperTable, items, items, setUpperTable
public static final VerilogNode.Tag TAG
public static final java.util.EnumSet<VerilogNode.Tag> TAGS_CHILDREN
public VerilogCaseGenerate(VerilogNode parent)
parent
- the parent node.public VerilogCaseGenerate(VerilogCaseGenerate other, VerilogNode parent)
other
- the generate case construct to be copied.parent
- the parent node.public VerilogExpression getExpression()
public void setExpression(VerilogExpression expression)
expression
- the expression to be set.public java.util.List<VerilogCaseGenerateItem> getCases()
public void addCase(VerilogCaseGenerateItem item)
item
- the case to be added.public VerilogCaseGenerate clone()
AbstractSymbolTable
clone
in class VerilogNode